775 CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Features • • • • • • • • • • • • • Output frequency range: 8.3 MHz to 200 MHz Input frequency range: 4.2 MHz to 125 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 1 Feedback clock output 2 LVCMOS reference clock inputs 150 ps max output-output skew PLL bypass mode Spread Aware™ Output enable/disable Industrial temperature range: –40°C to +85°C 52-Pin 1.0-mm TQFP package Description The CY29775 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29775 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 8.3 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Pin Configuration Block Diagram V C O _ S E L(1 ,0) QB0 NC VDDQB VDDQA QA0 F B _O U T VSS ÷4 / ÷6 / ÷8 / ÷12 V SS QB1 V DDQB QB2 V SS QB3 V DDQB QB4 FB_IN V SS FB_OUT V DDFB NC 14 15 16 17 18 19 20 21 22 23 24 25 26 QA1 VDDQA C LK _ S TP # QA2 QC0 QC1 QC2 QC3 VSS QC3 CLK STOP 39 38 37 36 35 34 33 32 31 30 29 28 27 CY29775 FB_SEL1 ÷4 / ÷6 S E LC VDDQC QB0 QB1 Q B2 QB3 QB4 S E LB VSS CLK STOP 1 2 3 4 5 6 7 8 9 10 11 12 13 QA3 VDDQA ÷2 / ÷4 SELA 52 51 50 49 48 47 46 45 44 43 42 41 40 V SS MR#/OE CLK_STP# SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 V CO_SEL1 V DD A V DD QA4 AVSS Q A0 Q A1 Q A2 Q A3 Q A4 FB_SEL0 CLK S TO P ÷2 / ÷4 ÷4 QC2 ÷2 VSS FB _IN PLL 20 0 5 00M H z QC1 VDDQC TC LK 0 T C LK 1 QC0 VSS VCO_SEL0 P L L_ E N TC LK _ S EL F B _S E L(1,0) M R #/O E Cypress Semiconductor Corporation Document #: 38-07480 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 28, 2003 CY29775 Pin Description[1] Pin Name I/O Type Description 9 TCLK0 I, PD LVCMOS LVCMOS/LVTTL reference clock input 10 TCLK1 I, PU LVCMOS LVCMOS/LVTTL reference clock input 16, 18, 21, 23, 25 QA(4:0) O LVCMOS Clock output bank A 32, 34, 36, 38, 40 QB(4:0) O LVCMOS Clock output bank B 44, 46, 48, 50 QC(3:0) O LVCMOS Clock output bank C 29 FB_OUT O LVCMOS Feedback clock output. Connect to FB_IN for normal operation. 31 FB_IN I, PU LVCMOS Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. 2 MR#/OE I, PU LVCMOS Output enable/disable input. See Table 2. 3 CLK_STP# I, PU LVCMOS Clock stop enable/disable input. See Table 2. 6 PLL_EN I, PU LVCMOS PLL enable/disable input. See Table 2. 8 TCLK_SEL I, PD LVCMOS Reference select input. See Table 2. 11, 52 VCO_SEL(1,0) I, PD LVCMOS VCO divider select input. See Tables 2, 3 and 4. 7, 4, 5 SEL(A:C) I, PD LVCMOS Frequency select input, Bank (A:C). See Table 3. 20, 14 FB_SEL(1,0) I, PD LVCMOS Feedback dividers select inputs. See Table 4. 17, 22, 26 VDDQA Supply VDD 2.5V or 3.3V Power supply for bank A output clocks[2,3] 33, 37, 41 VDDQB Supply VDD 2.5V or 3.3V Power supply for bank B output clocks[2,3] 45, 49 VDDQC Supply VDD 2.5V or 3.3V Power supply for bank C output clocks[2,3] 28 VDDFB Supply VDD 2.5V or 3.3V Power supply for feedback output clock[2,3] 13 AVDD Supply VDD 2.5V or 3.3V Power supply for PLL[2,3] 12 VDD Supply VDD 2.5V or 3.3V Power supply for core and inputs[2,3] 15 AVSS Supply Ground Analog Ground 1, 19, 24, 30, 35, 39, 43, 47, 51 VSS Supply Ground Common Ground 27, 42 NC No Connection Notes: 1. PU = Internal pull-up, PD = Internal pull-down 2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (<0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQA, VDDQB, VDDQC, and VDDFB power supply pins. Document #: 38-07480 Rev. ** Page 2 of 10 CY29775 Table 1. Frequency Table Feedback Output Divider VCO Input Frequency Range (AVDD = 3.3V) Input Frequency Range (AVDD = 2.5V) ÷8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz ÷12 Input Clock * 12 16.6 MHz to 41.6 MHz 16.6 MHz to 33.3 MHz ÷16 Input Clock * 16 12.5 MHz to 31.25 MHz 12.5 MHz to 25 MHz ÷24 Input Clock * 24 8.3 MHz to 20.8 MHz 8.3 MHz to 16.6 MHz ÷32 Input Clock * 32 6.25 MHz to 15.625 MHz 6.25 MHz to 12.5 MHz ÷48 Input Clock * 48 4.2 MHz to 10.4 MHz 4.2 MHz to 8.3 MHz ÷4 Input Clock * 4 50 MHz to 125 MHz 50 MHz to 100 MHz ÷6 Input Clock * 6 33.3 MHz to 83.3 MHz 33.3 MHz to 66.6 MHz ÷8 Input Clock * 8 25 MHz to 62.5 MHz 25 MHz to 50 MHz ÷12 Input Clock * 12 16.6 MHz to 41.6 MHz 16.6 MHz to 33.3 MHz Table 2. Function Table (configuration controls) Control Default 0 1 TCLK_SEL 0 TCLK0 TCLK1 VCO_SEL0 0 VCO÷2 (mid input frequency range) VCO÷4 (low input frequency range) VCO_SEL1 0 Gated by VCO_SEL0 VCO (high input frequency range) PLL_EN 1 Bypass mode, PLL disabled. The input clock connects to the output dividers PLL enabled. The VCO output connects to the output dividers MR#/OE 1 Outputs disabled (three-state) and reset of the device. During reset/output disable the PLL feedback loop is open and the VCO running at its minimum frequency. The device is reset by the internal power-on reset (POR) circuitry during power-up. Outputs enabled CLK_STP# 1 QA, QB, and QC outputs disabled in LOW state. FB_OUT is not affected by CLK_STP#. Outputs enabled Table 3. Function Table (Bank A, B, and C) VCO_SEL1 VCO_SEL0 SELA QA(4:0) SELB QB(4:0) SELC QC(3:0) 0 0 0 0 ÷4 0 ÷8 0 0 1 ÷4 ÷8 1 ÷8 1 ÷12 0 1 0 ÷8 0 ÷8 0 ÷16 0 1 1 ÷16 1 ÷16 1 ÷24 1 x 0 ÷2 0 ÷2 0 ÷4 1 x 1 ÷4 1 ÷4 1 ÷6 Document #: 38-07480 Rev. ** Page 3 of 10 CY29775 Table 4. Function Table (FB_OUT) VCO_SEL1 VCO_SEL0 FB_SEL1 FB_SEL0 FB_OUT 0 0 0 0 ÷8 0 0 0 1 ÷16 0 0 1 0 ÷12 0 0 1 1 ÷24 0 1 0 0 ÷16 0 1 0 1 ÷32 0 1 1 0 ÷24 0 1 1 1 ÷48 1 x 0 0 ÷4 1 x 0 1 ÷8 1 x 1 0 ÷6 1 x 1 1 ÷12 Absolute Maximum Conditions Parameter Description VDD DC Supply Voltage VDD DC Operating Voltage VIN VOUT Condition Min. Max. Unit –0.3 5.5 V Functional 2.375 3.465 V DC Input Voltage Relative to VSS –0.3 VDD + 0.3 V DC Output Voltage Relative to VSS –0.3 VDD + 0.3 V – VDD ÷ 2 V Functional 200 – mA VTT Output termination Voltage LU Latch Up Immunity RPS Power Supply Ripple Ripple Frequency < 100 kHz – 150 mVp-p TS Temperature, Storage Non Functional –65 +150 °C TA Temperature, Operating Ambient Functional –40 +85 °C TJ Temperature, Junction Functional – 150 °C ØJC Dissipation, Junction to Case Functional – 23 °C/W ØJA Dissipation, Junction to Ambient Functional – 55 °C/W – Volts ESDH FIT ESD Protection (Human Body Model) Failure in Time Document #: 38-07480 Rev. ** 2000 Manufacturing test 10 ppm Page 4 of 10 CY29775 DC Electrical Specifications (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description Condition Min. Typ. Max. Unit VIL Input Voltage, Low LVCMOS – – 0.8 V VIH Input Voltage, High LVCMOS 2.0 – VDD+0.3 V IOL = 24 mA – – 0.55 V IOL = 12 mA – – 0.30 2.4 – – V VOL VOH IIL Output Voltage, Low[4] [4] Output Voltage, High Input Current, IOH = –24 mA Low[5] VIL = VSS – – –100 µA [5] IIH Input Current, High VIL = VDD – – 100 µA IDDA PLL Supply Current AVDD only – 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD – – 1 mA Dynamic Supply Current Outputs loaded @ 100 MHz – 225 – mA Outputs loaded @ 200 MHz – 290 – Input Pin Capacitance – 4 – pF Output Impedance 12 15 18 Ω Min. Typ. Max. Unit IDD CIN ZOUT DC Electrical Specifications (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description Condition VIL Input Voltage, Low LVCMOS – – 0.7 V VIH Input Voltage, High LVCMOS 1.7 – VDD+0.3 V – – 0.6 V 1.8 – – V VOL VOH IIL IIH Output Voltage, Low[4] IOL = 15 mA Output Voltage, High[4] IOH = –15 mA [5] VIL = VSS – – –100 µA High[5] VIL = VDD – – 100 µA Input Current, Low Input Current, IDDA PLL Supply Current AVDD only – 5 10 mA IDDQ Quiescent Supply Current All VDD pins except AVDD – – 1 mA Dynamic Supply Current Outputs loaded @ 100 MHz – 135 – mA Outputs loaded @ 200 MHz – 160 – Input Pin Capacitance – 4 – pF Output Impedance 14 18 22 Ω IDD CIN ZOUT Notes: 4. Driving one 50Ω parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50Ω series terminated transmission lines. 5. Inputs have pull-up or pull-down resistors that affect the input current. Document #: 38-07480 Rev. ** Page 5 of 10 CY29775 AC Electrical Specifications[6] (VDD= 2.5V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency Condition Min. Typ. Max. Unit 200 – 400 MHz ÷4 Feedback 50 – 100 MHz ÷6 Feedback 33.3 – 66.6 ÷8 Feedback 25 – 50 ÷12 Feedback 16.7 – 33.3 ÷16 Feedback 12.5 – 25 ÷24 Feedback 8.3 – 16.7 ÷32 Feedback 6.3 – 12.5 ÷48 Feedback 4.2 – 8.3 0 – 200 25 – 75 % – – 1.0 ns MHz Bypass mode (PLL_EN = 0) frefDC Input Duty Cycle tr , tf TCLK Input Rise/FallTime 0.7V to 1.7V fMAX Maximum Output Frequency ÷2 Output 100 – 200 ÷4 Output 50 – 100 ÷6 Output 33.3 – 66.6 ÷8 Output 25 – 50 ÷12 Output 16.7 – 33.3 ÷16 Output 12.5 – 25 ÷24 Output 8.3 – 16.7 45 – 55 % 0.1 – 1.0 ns –100 – 100 ps DC Output Duty Cycle tr , tf Output Rise/Fall times 0.7V to 1.8V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, does not include jitter tsk(O) Output-to-Output Skew Skew within Bank – – 150 ps tsk(B) Bank-to-Bank Skew Banks at same frequency – – 150 ps Banks at different frequency – – 225 tPLZ, HZ Output Disable Time – – 10 ns tPZL, ZH Output Enable Time – – 10 ns BW PLL Closed Loop Bandwidth (–3 dB) VCO_SEL = 0 – 0.5 - 1.0 – MHz VCO_SEL = 1 – 1.0 - 2.0 – Cycle-to-Cycle Jitter Same frequency – – 150 Multiple frequencies – – 300 tJIT(CC) ps tJIT(PER) Period Jitter – – 100 ps tJIT(φ) I/O Phase Jitter – – 150 ps tLOCK Maximum PLL Lock Time – – 1 ms Note: 6. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. Document #: 38-07480 Rev. ** Page 6 of 10 CY29775 AC Electrical Specifications [6] (VDD= 3.3V ± 5%, TA = –40°C to +85°C) Parameter Description fVCO VCO Frequency fin Input Frequency Condition Min. Typ. Max. Unit 200 – 500 MHz ÷4 Feedback 50 – 125 MHz ÷6 Feedback 33.3 – 83.3 ÷8 Feedback 25 – 62.5 ÷12 Feedback 16.7 – 41.6 ÷16 Feedback 12.5 – 31.3 ÷24 Feedback 8.3 – 20.8 ÷32 Feedback 6.3 – 15.6 ÷48 Feedback 4.2 – 10.4 0 – 200 25 – 75 % – – 1.0 ns MHz Bypass mode (PLL_EN = 0) frefDC Input Duty Cycle tr , tf TCLK Input Rise/FallTime 0.8V to 2.0V fMAX Maximum Output Frequency ÷2 Output 100 – 200 ÷4 Output 50 – 125 ÷6 Output 33.3 – 83.3 ÷8 Output 25 – 62.5 ÷12 Output 16.7 – 41.6 ÷16 Output 12.5 – 31.3 ÷24 Output 8.3 – 20.8 45 – 55 % 0.1 – 1.0 ns –100 – 100 ps DC Output Duty Cycle tr , tf Output Rise/Fall times 0.8V to 2.4V t(φ) Propagation Delay (static phase offset) TCLK to FB_IN, same VDD, does not include jitter tsk(O) Output-to-Output Skew Skew within Bank – – 150 ps tsk(B) Bank-to-Bank Skew Banks at same voltage, same frequency – – 150 ps Banks at same voltage, different frequency – – 225 Banks at different voltage – – 250 tPLZ, HZ Output Disable Time – – 10 ns tPZL, ZH Output Enable Time – – 10 ns BW PLL Closed Loop Bandwidth (–3dB) VCO_SEL = 0 – 0.5 - 1.0 – MHz VCO_SEL = 1 – 1.0 - 2.0 – Cycle-to-Cycle Jitter Same frequency – – 150 Multiple frequencies – – 300 – – 100 ps – – 150 ps – – 1 ms tJIT(CC) tJIT(PER) Period Jitter tJIT(φ) I/O Phase Jitter tLOCK Maximum PLL Lock Time Document #: 38-07480 Rev. ** I/O at same VDD ps Page 7 of 10 CY29775 Zo = 50 ohm Pulse Generator Z = 50 ohm Zo = 50 ohm R T = 50 ohm R T = 50 ohm VTT VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V VDD LVCMOS_CLK VDD/2 GND VDD FB_IN VDD/2 t(φ) GND Figure 2. Propagation Delay t(φ), Static Phase Offset VDD VDD/2 tP GND T0 DC = tP / T0 x 100% Figure 3. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(O) GND Figure 4. Output-to-Output Skew, tsk(O) Document #: 38-07480 Rev. ** Page 8 of 10 CY29775 Ordering Information Part Number Package Type Product Flow CY29775AI 52-pin TQFP Industrial, –40°C to +85°C CY29775AIT 52-pin TQFP -Tape and Reel Industrial, –40°C to 85°C Package Drawing and Dimension 52-Lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B 51-85158-** Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07480 Rev. ** Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29775 Document History Page Document Title:CY29775 2.5V or 3.3V, 200-MHz, 14 Output Zero Delay Buffer Document #: 38-07480 Rev. ECN No. Issue Date Orig. of Change ** 125955 04/29/03 RGL Document #: 38-07480 Rev. ** Description of Change New Data Sheet Page 10 of 10