NJRC NJW1341

NJW1341
8input-2output Video Switch
with Isolation Amplifier & small AC-coupled Video Driver
■ GENERAL DESCRIPTION
The NJW1341 is 8-Input,2-Output Video Switch.
The NJW1341 consists of switch and isolation
amplifiers(2input) and Video Driver which features small
AC-coupled(1output).
All of functions are controlled by I2C Bus.
■ PACKAGE OUTLINE
NJW1341VC3
■APPLICATIONS
●Car AVN
●Any Video System
■ FEATURES
● Operating Voltage
● Small AC-coupled video amplifier (VOUT2)
● Isolation Amplifiers(VIN1,2)
● 8in-2out Video Switch
● Common Mode Rejection Ratio -50dB typ
● Bi-CMOS Technology
2
● I C BUS interface
● Package Outline
4.5 to 9.5V
SSOP20-C3
■ BLOCK DIAGRAM
VIN1
+
-
Buffer
VGND1
VIN2
VOUT1
+
-
Mute
VGND2
6dB
VIN3
75Ω Driver
47µF 75Ω
+
VIN4
VOUT2
SREF
Mute
VIN5
VSAG
VIN6
SSIG
VIN7
SDA
I2C BUS
VIN8
SCL
VDD
V+
GND
Ver.2
-1-
NJW1341
„ ABSOLUTE MAXIMUM RATING (Ta=25°C)
PARAMETER
SYMBOL
Supply Voltage
V
Power Dissipation
+
RATINGS
UNIT
VCC:+13,VDD:+7
V
mW
PD
1,000(note1)
Operating Temperature Range
Topr
-40 to +85
°C
Storage Temperature Range
Tstg
-40 to +150
°C
(note1)At on a board of EIA/JEDEC specification. (114.3 x 76.2 x 1.6mm 2 layers, FR-4)
+
o
„ ELECTRICAL CHARACTERISTICS(V =5V,Ta=25 C)
PARAMETER
SYMBOL
TEST CONDITION
MIN.
TYP.
MAX.
UNIT
Operating Voltage 1
VCC
4.5
5
9.5
V
Operating Voltage 1
VDD
4.5
5
5.5
V
Operating Current 1
ICC1
No,signal
-
25
40
mA
Operating Current 2
ICC2
OUT2 power save
-
10
15
mA
Operating Current 3
ICC3
OUT1power save
-
20
35
mA
Operating Current 4
Isave
OUT1,OUT2 power save
2
4
mA
2.4
-
-
Vp-p
-1.0
0
1.0
dB
5.5
6.0
6.5
dB
-1.0
0
1.0
dB
Maximum
Output Voltage
Vvom
Voltage Gain1
Gv1
Voltage Gain2
Gv2
f=100kHz,THD=1%
OUT1,Vin=1MHz,1.0Vp-p,Sine
Signal
OUT2,Vin=1MHz,1.0Vp-p,Sine
Signal
Vin=10MHz /1MHz, 1.0Vp-p sine
wave
Low Pass Filter
Characteristic 1
Gf
Differential Gain
DG
Vin=1.0Vp-p,10step Video Signal
-
0.5
-
%
Differential Phase
DP
Vin=1.0Vp-p,10step Video Signal
-
0.5
-
deg
S/N Ratio
SN
Vin=1.0Vp-p, 100% White video
signal,RL=75Ω, 100KHz to 6MHz
-
60
-
dB
CMR
Vin=20kHz, 1.0Vp-p Sine Signal
-
-55
-
dB
Common mode
Rejection Ratio
CrossTalk
-2-
CT
Vin=4.43MHz, 1.0Vp-p Sine Signal
-60
dB
NJW1341
■ TEST CIRCUIT
1
75Ω
IN1
VOUT1
+
20
22u
1u
2
IN1G
SREF
19
3
IN2
VSAG
18
2kΩ
1u
75Ω
1u
4
IN2G
5
IN3
SSIG
17
VOUT2
16
68k
1u
68k
0.1u
1u
75Ω
47u
1u
6
75Ω
75Ω
75Ω
75Ω
75Ω
+
IN4
VCC
75Ω
75Ω
15
0.1u
1u
7
IN5
GND
14
8
IN6
VDD
13
+
47u
VCC
4.5V-9.5V
1u
+
1u
9
IN7
SDA
12
10
IN8
SCL
11
47u
VDD
4.5V-5.5V
1u
1u
-3-
NJW1341
2
„TIMING on the I C BUS (SDA, SCL)
SDA
tf
tr
tf
tHD:ST A
tSP
tBUF
tr
tSU:DAT
SCL
tHD:ST A
S
tLOW
tSU:STA
tHD:DAT
tHIGH
tSU:ST O
Sr
S
P
2
„CHARACTERISTICS OF BUS LINES (SDA, SCL) FOR I C BUS DEVICES
2
I C BUS Load Conditions
STANDARD MODE :
FAST MODE :
Pull up resistance 4kΩ (Connected to +3.3V), Load capacitance 200pF (Connected to GND)
Pull up resistance 4kΩ (Connected to +3.3V), Load capacitance 50pF (Connected to GND)
Standard mode
Fast mode
SYM
BOL
MIN.
TYP.
MAX
.
MIN.
TYP.
MAX.
Low Level Input Voltage
VIL
0.0
-
1.5
0.0
-
1.5
V
High Level Input Voltage
VIH
2.7
-
5.0
2.7
-
5.0
V
Hysteresis of Schmitt Trigger Inputs
Vhys
-
-
-
0.25
-
-
V
Low level Output Voltage (3mA at SDA pin)
VOL
0
-
0.4
0
-
0.4
V
-
250
ns
PARAMETER
UNIT
tof
-
-
250
20
+0.1Cb
tSP
-
-
-
0
-
50
ns
Ii
-10
-
10
-10
-
10
µA
Ci
-
-
10
-
-
10
pF
fSCL
-
-
100
-
-
400
kHz
tHD:STA
4.0
-
-
0.6
-
-
µs
Low Level Clock Pulse Width
tLOW
4.7
-
-
1.3
-
-
µs
High Level Clock Pulse Width
tHIGH
4.0
-
-
0.6
-
-
µs
tSU:STA
4.7
-
-
0.6
-
-
µs
tHD:DAT
0.0
-
3.45
0.0
-
0.9
µs
tSU:DAT
250
-
-
100
-
-
ns
Rise Time
tr
-
-
1000
-
-
300
ns
Fall Time
tf
-
-
300
-
-
300
ns
tSU:STO
4.0
-
-
0.6
-
-
µs
Data Change Minimum Waiting Time
tBUF
4.7
-
-
1.3
-
-
µs
Capacitive load for each bus line
Cb
-
-
400
-
-
400
pF
Noise Margin at the Low Level
VnL
0.5
-
-
0.5
-
-
V
Noise Margin at the High Level
VnH
1
-
-
1
-
-
V
Output Fall Time From VIHmin to VILmax with a Bus
Capacitance from 10pF to 400pF
Pulse width of spikes which must be suppressed
by the input filter
Input Current each I/O pin with an Input
Voltage between 0.1 and 0.9VDDmax
Capacitance for each I/O pin
SCL Clock Frequency
Data Transfer Start Minimum Waiting Time
Minimum Start Preparation Waiting Time
Minimum Data Hold Time
NOTE)
Minimum Data Preparation Time
Minimum Stop Preparation Waiting Time
Cb ; total capacitance of one bus line in pF.
NOTE). Please hold the Data Hold Time (tHD:DAT) to 300ns or more to avoid status of unstable at SCL falling edge.
-4-
NJW1341
2
■ DEFINITION OF I C REGISTER
2
♦I C BUS FORMAT
MSB
S
LSB
Slave Address
MSB
A
1bit
8bit
S: Starting Term
A: Acknowledge Bit
P: Ending Term
1bit
LSB
Data
A
P
8bit
1bit
1bit
♦SLAVE ADDRESS
MSB
0
0
1
0
0
0
0
LSB
0
R/W=0: Receive Only
R/W=1: Data is not transmitted.
♦CONTROL REGISTER DEFAULT VALUE
Control register default values are as follows :
BIT
Data
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
D2
D1
D0
♦INSTRUCTION CODE
BIT
D7
Data
OUT1
MUTE
D6
D5
OUT1 Select
D4
D3
OUT2
MUTE
OUT2 Select
♦MUTE TABLE
MUTE
OUT1
D7
0
MUTE OFF
1
MUTE ON
MUTE
OUT2
D3
0
MUTE OFF
1
MUTE ON
MUTE OFF: Active mode
MUTE ON: Power save mode
-5-
NJW1341
♦VOUT SELECT TABLE
OUT1 Select
OUT1
D6
D5
D4
0
0
0
VIN1
0
0
1
VIN2
0
1
0
VIN3
0
1
1
VIN4
1
0
0
VIN5
1
0
1
VIN6
1
1
0
VIN7
1
1
1
VIN8
OUT2 Select
OUT2
D2
D1
D0
0
0
0
VIN1
0
0
1
VIN2
0
1
0
VIN3
0
1
1
VIN4
1
0
0
VIN5
1
0
1
VIN6
1
1
0
VIN7
1
1
1
VIN8
[CAUTION]
The specifications on this databook are only
given for information , without any guarantee
as regards either mistakes or omissions. The
application circuits in this databook are
described only to show representative usages
of the product and not intended for the
guarantee or permission of any right including
the industrial rights.
-6-