NJW1321 WIDE BAND VIDEO SWITCH WITH I2C BUS ■ GENERAL DESCRIPTION 2 The NJW1321 is a Wide Band Video Switch with I C BUS. The NJW1321 includes switch of 4-input 2-output and 6dB amplifier. It is suitable for RGB or Y, Pb, and Pr signal because frequency range is 100MHz. The NJW1321 includes external logic control terminals and external logic discernment terminals. The NJW1321 is suitable for PTV, DTV, PDP and other high quality AV systems. ■ FEATURES ● Operating Voltage 2 ● I C BUS Interface ● 4-input 2-output 3-Circuits ● Wide frequency range ■ PACKAGE OUTLINE NJW1321FP1 +9.0V 0dB at 100MHz typ. -3dB at 300MHz typ. ● Internal 6dB amplifier (Selectable Bypass or 6dB) ● External logic discernment terminal ● External logic control terminal ● Selectable slave address ● Power Save Circuit ● Bi-CMOS Technology ● Package Outline QFP48 ■ BLOCK DIAGRAM Y/R IN1 Y/R IN2 6dB Y/R OUT1 6dB Y/R OUT2 6dB Pb/G OUT1 6dB Pb/G OUT2 6dB Pr/B OUT1 6dB Pr/B OUT2 Y/R IN3 Y/R IN4 Pb/G IN1 Pb/G IN2 Pb/G IN3 Pb/G IN4 Pr/B IN1 Pr/B IN2 Pr/B IN3 Pr/B IN4 PORT 0 ADDRESS PORT 1 SDA PORT 2 SCL I2C BUS PORT 3 AUX 1 V+ GND VREF AUX 0 BIAS AUX 2 AUX 3 DGND Ver.3 -1- NJW1321 Pb IN4 V+ Y IN4 V+ Y OUT1 GND Pb OUT1 GND Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 AUX0 ■PIN CONFIGURATION 38 -2- 24 48 15 1 14 Pb IN2 GND Pr IN2 GND Y IN1 V+ Pb IN1 V+ Pr IN1 GND PORT3 PORT2 ADR 39 V+ GND Pr IN4 V+ Y IN3 GND Pb IN3 V+ Pr IN3 GND Y IN2 25 1. V+ 13. PORT2 25. AUX0 37. V+ 2. Pb IN2 14. ADR 26. AUX1 38. Pb IN4 3. GND 15. SCL 27. Y OUT2 39. GND 4. Pr IN2 16. SDA 28. AUX2 40. Pr IN4 5. GND 17. GND 29. AUX3 41. V+ 6. Y IN1 18. DGND 30. Pr OUT1 42. Y IN3 7. V+ 19. VREG 31. GND 43. GND 8. Pb IN1 20. V+ 32. Pb OUT1 44. Pb IN3 9. V+ 21. Pr OUT2 33. GND 45. V+ 10. Pr IN1 22. PORT1 34. Y OUT1 46. Pr IN3 11. GND 23. PORT 0 35. V+ 47. GND 12. PORT3 24. Pb OUT2 36. Y IN4 48. Y IN2 Pb OUT2 PORT0 PORT1 Pr OUT2 V+ VREF DGND GND SDA SCL NJW1321 ■ ABSOLUTE MAXIMUM RATINGS (Ta=25°C) PARAMETER SYMBOL RATINGS UNIT + Supply Voltage V 12.0 V Power Dissipation PD 1875(note) mW Topr -40 to +75 Operating Temperature Range °C Tstg -40 to +150 Storage Temperature Range °C (Note) At on a board of EIA/JEDEC specification. (76.2 × 114.3 × 1.6mm Two layers, FR-4) ■ RECOMMENDED OPEARATING CONDITION (Ta=25°C) PARAMETER Operating Voltage SYMBOL Vopr TEST CONDITION MIN. 8.5 TYP. 9.0 MAX. 9.5 UNIT V MIN. TYP. MAX. UNIT - 85 100 mA 2.0 2.5 - Vp-p 6.0 6.4 6.8 dB -0.5 0.0 0.5 dB - 0 - dB - 0 - dB - -3.0 - dB - -3.0 - dB - -60 -50 dB + ■ ELECTRICAL CHARACTERISTICS (V =9.0V, RL=10KΩ, Ta=25°C) ●VIDEO PARAMETER SYMBOL TEST CONDITION Operating Current Icc No signal Maximum Output Voltage Vom Voltage Gain 1 Gv1 Voltage Gain 2 Gv2 Frequency Characteristic 1 Frequency Characteristic 2 Frequency Characteristic 3 Frequency Characteristic 4 Cross talk 1 CTB1 f=100kHz, THD=1% 6dB Mode Vin=100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=100kHz, 1.0Vp-p Sin signal 6dB Mode Vin=100MHz / 100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=100MHz / 100kHz, 1.0Vp-p Sin signal 6dB Mode Vin=300MHz / 100kHz, 1.0Vp-p Sin signal Bypass Mode Vin=300MHz / 100kHz, 1.0Vp-p Sin signal Vin=4.43MHz,1.0Vp-p Sin signal Cross talk 2 CTB2 Vin=50MHz,1.0Vp-p Sin signal - -40 - dB Gf1 Gf2 Gf3 Gf4 Differential Gain DG Vin=1.0Vp-p 10step Video signal - 0.3 - % Differential Phase DP Vin=1.0Vp-p 10step Video signal - 0.3 - deg S/N SNv Vin=1.0Vp-p,100% White Video Signal - 65 - dB MIN. TYP. MAX. UNIT ●PORT, AUX PARAMETER SYMBOL TEST CONDITION PORT Input Voltage H VPTH 3.5 - 5.5 V PORT Input Voltage M VPTM 1.4 - 2.4 V PORY Input Voltage L VPTL 0 - 0.8 V AUX Output Voltage H VAUXH 3.5 - 5.5 V AUX Output Voltage M AUX Output Voltage L ADR Input Voltage H VAUXM VAUXL VADRH 1.4 0 3.5 - 2.4 0.8 5.0 V V V ADR Input Voltage L VADRL 0 - 1.0 V -3- NJW1321 2 ■ I C BUS BLOCK CHARACTERISTICS (SDA,SCL) PARAMETER SYMBOL MIN. TYP. MAX. UNIT High Level Input Voltage VIH 3.0 - 5.0 V Low Level Input Voltage VIL 0 - 1.5 V High Level Input Current IIH - - 10 µA Low Level Input Current IIL - - 10 µA Low Level Output Voltage (3mA at SDA pin) VOL 0 - 0.4 V Maximum Output Current IOL -3.0 - - mA Maximum Clock Frequency fSCL - - 100 kHz Data Change Minimum Waiting Time tBUF 4.7 - - µs tHD:STA 4.0 - - µs Low Level Clock Pulse Width tLOW 4.7 - - µs High Level Clock Pulse Width tHIGH 4.0 - - µs Minimum Start Preparation Waiting Time tSU:STA 4.0 - - µs Minimum Data Hold Time tHD:DAT 0.0 - 3.45 µs Minimum Data Preparation Time tSU:DAT 250 - - ns Rise Time tR - - 1.0 µs Fall Time tF - - 300 ns tSU:STO 4.0 - - µs Data Transfer Start Minimum Waiting Time Minimum Stop Preparation Waiting Time 2 I C BUS Load Condition: Pull up resistance 4kΩ (Connected to +5V) Load capacitance 200pF (Connected to GND) SDA tBUF tR tF tHD:STA SCL tHD:STA tLOW P -4- S tHD:DAT tHIGH tSU:STA tSU:DAT Sr tSU:STO P NJW1321 ■EQUIVALENT CIRCUIT PIN No. NAME 6 8 10 48 2 4 42 44 46 36 38 40 Y IN1 Pb IN1 Pr IN1 Y IN2 Pb IN2 Pr IN2 Y IN3 Pb IN3 Pr IN3 Y IN4 Pb IN4 Pr IN4 FUNCTION INSIDE EQUIVALENT CIRCUIT V+ Y,Pb,Pr Input RGB Input V+ V+ 150kΩ 100Ω V+ 34 32 30 27 24 21 Y OUT1 Pb OUT1 Pr OUT1 Y OUT2 Pb OUT2 Pr OUT2 VOLTAGE 4.4V V+ Y,Pb,Pr Output RGB Output 3.0V 50Ω V+ 23 22 13 12 PORT0 PORT1 PORT2 PORT3 V+ Logic input terminal 66Ω 100kΩ V+ V+ V+ 1kΩ 25 26 28 29 AUX0 AUX1 AUX2 AUX3 Auxiliary 3 values voltage output terminal 66Ω 0V 1.9V 5.0V -5- NJW1321 PIN No. NAME FUNCTION INSIDE EQUIVALENT CIRCUIT V+ 14 ADR V+ VOLTAGE VREF Slave address setting terminal 66Ω 15 16 SCL SDA 2 I C clock terminal 2 I C data terminal V+ 19 VREF Reference voltage terminal - 4kΩ V+ V+ 66Ω 4.8V 48kΩ 1 7 9 20 35 37 41 45 V+ Supply voltage terminal - 3 5 11 17 31 33 39 43 47 GND Ground terminal - 18 DGND Ground terminal - -6- NJW1321 2 ■ DEFINITION OF I C REGISTER ♦I C BUS FORMAT 2 MSB S LSB Slave Address 1bit 8bit MSB LSB A Data 1bit 8bit MSB A 1bit LSB Data A 8bit 1bit 1bit P S: Starting Term A: Acknowledge Bit P: Ending Term ♦SLAVE ADDRESS R/W: Set the Write Mode or Read Mode. ADR : Set the Slave Address by “ADR” terminal. Slave Address Hex MSB 1 0 0 0 LSB - 0 0 ADR R/W - ◆ R/W = 0 : Write Mode, ADR = 0/1 - 1 0 0 1 0 1 0 0 94(h) 1 0 0 1 0 1 1 0 96(h) ◆ R/W = 1 : Read Mode, ADR = 0/1 - 1 0 0 1 0 1 0 1 95(h) 1 0 0 1 0 1 1 1 97(h) ♦CONTROL REGISTER TABLE < Write Mode > No. Data1 BIT D7 D6 PS1 PS2 Data2 D4 D5 D3 D2 OUT1 AUX0 D1 D0 OUT2 AUX1 AUX2 AUX3 < Read Mode > No. BIT D7 D6 D4 D5 PORT0 Data D3 PORT1 D2 D1 PORT2 D0 PORT3 ♦CONTROL REGISTER DEFAULT VALUE Control register default value is all “0”. No. Data1 Data2 BIT D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -7- NJW1321 !INSTRUCTION CODE ♦POWER SAVE, OUTPUT SETTING No. Data1 BIT D7 D6 PS1 PS2 D4 D5 D3 D2 OUT1 •PS1, PS2: Power Save Setting Power Save OUT1 ON OUT2 ON OUT1 ON OUT2 OFF OUT1 OFF OUT2 ON OUT1 OFF OUT2 OFF D7 0 0 1 1 D6 0 1 0 1 ON: Power Save OFF, OFF: Power Save ON (Mute) •OUT1: Output 1 Setting YIN1 YIN2 YIN3 YIN4 Output 1 PbIN1 PbIN2 PbIN3 PbIN4 PrIN1 PrIN2 PrIN3 PrIN4 D5 0 0 1 1 D4 0 1 0 1 Gain 6dB 0dB D3 0 1 D2 0 0 1 1 D1 0 1 0 1 Gain 6dB 0dB D0 0 1 •OUT2: Output 2 Setting YIN1 YIN2 YIN3 YIN4 -8- Output 2 PbIN1 PbIN2 PbIN3 PbIN4 PrIN1 PrIN2 PrIN3 PrIN4 D1 OUT2 D0 NJW1321 ♦ AUX: AUXILIARY SETTING No. BIT D7 Data2 D6 D4 D5 AUX0 D3 AUX1 AUX0 L M H D7 0 0 1 D6 0 1 1 AUX1 L M H D5 0 0 1 D4 0 1 1 AUX2 L M H D3 0 0 1 D2 0 1 1 AUX3 L M H D1 0 0 1 D0 0 1 1 D2 D1 AUX2 D0 AUX3 ♦PORT: PORT SETTING No. Data BIT D7 D6 PORT0 D4 D5 PORT1 PORT0 OPEN L M H D7 0 0 0 1 D6 0 0 1 1 PORT1 OPEN L M H D5 0 0 0 1 D4 0 0 1 1 PORT2 OPEN L M H D3 0 0 0 1 D2 0 0 1 1 PORT3 OPEN L M H D1 0 0 0 1 D0 0 0 1 1 D3 D2 PORT2 D1 D0 PORT3 -9- NJW1321 ■TEST CIRCUIT Pb IN4 Y IN4 50Ω/75Ω 1uF + 0.1uF 38 39 10kΩ 50Ω/75Ω 1uF + Pb OUT1 Y OUT1 10uF + 0.1uF + 10uF Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 10kΩ 10kΩ 0.1uF 10uF + 0.1uF 10kΩ 10kΩ 10uF 10kΩ + AUX0 10kΩ 10kΩ 0.1uF 0.1uF 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + 10uF 0.1uF Pr IN4 50Ω/75Ω Y IN3 50Ω/75Ω 50Ω/75Ω Pr IN3 50Ω/75Ω Y IN2 + 40 23 PORT0 41 22 PORT1 42 21 0.1uF 1uF + NJW1321 NJW1320 19 45 18 46 17 47 16 SDA 15 14 SCL 1uF 0.1uF 1uF + 0.1uF 1uF + 48 2 3 4 5 6 7 8 9 10 11 12 13 0.1uF + + 0.1uF Pb IN2 V+ + - 10 - + 44 1uF 100uF 10uF 20 1uF + + 0.1uF 0.1uF 1 50Ω/75Ω Pb OUT2 1uF 43 Pb IN3 10kΩ 0.1uF 50Ω/75Ω + 1uF 0.1uF Pr IN2 50Ω/75Ω + + 1uF 0.1uF Y IN1 50Ω/75Ω 1uF 1uF 0.1uF 0.1uF Pb IN1 50Ω/75Ω Pr IN1 50Ω/75Ω PORT3 PORT2 ADR Pr OUT2 10kΩ NJW1321 ■APPLICATION CIRCUIT Pb IN4 Y IN4 75Ω Pb OUT1 Y OUT1 Pr OUT1 AUX3 AUX2 Y OUT2 AUX1 75Ω 10kΩ 1uF + 1uF + 0.1uF 38 39 AUX0 10uF + 0.1uF + 10uF 10uF + 0.1uF 0.1uF 10kΩ 10uF 10kΩ 10kΩ + 0.1uF 0.1uF 37 36 35 34 33 32 31 30 29 28 27 26 25 24 + 10uF 0.1uF Pr IN4 75Ω Y IN3 75Ω + 40 23 PORT0 41 22 PORT1 42 21 0.1uF 1uF + NJW1321 NJW1320 75Ω Pr IN3 75Ω Y IN2 75Ω 10uF Pr OUT2 20 1uF + + 0.1uF 0.1uF 43 Pb IN3 Pb OUT2 1uF + 44 19 45 18 46 17 47 16 SDA 15 14 SCL 1uF 0.1uF 1uF + 0.1uF 1uF + 48 1 2 3 4 5 6 7 8 9 10 11 12 13 0.1uF + 1uF + 0.1uF 1uF 75Ω Pb IN2 0.1uF + + + 1uF 1uF 1uF 75Ω Pr IN2 0.1uF 75Ω Y IN1 Pb IN1 0.1uF 0.1uF 75Ω 75Ω PORT3 PORT2 ADR Pr IN1 V+ + 100uF 0.1uF - 11 - NJW1321 ■TYPICAL CHARACTERISTICS Voltege Gain vs. Frequency 10 0 Gv[dB] -10 -20 -30 0dB 6dB -40 10 6 10 7 8 10 Frequency[Hz] ■NOTE Please all connect V+ terminal and GND terminal. When the power supply voltage is not impressing, please do not impress voltage to the ADR terminal. [CAUTION] The specifications on this databook are only given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights. - 12 -