INF85116 2048 х 8 -Bit CMOS EEPROM with I2С-bus interface The INF85116N is an 16-Kbits (2048 x 8-bit) floating gate Electrically Erasable Programmable Read Only Memory (EEPROM). Power consumption is low due to the full CMOS technology used. The programming voltage is generated on-chip, using a voltage multiplier. As data bytes are received and transmitted via the serial I2C-bus, a package using eight pins is sufficient. Only one INF85116N device is required to support all eight blocks of 256 x 8-bit each. FEATURES • Low power CMOS -maximum active current 1.0 mA -maximum standby current 10 µA (at 5.5 V), typical 4 µA • Non-volatile storage of 16-Kbits organized as eight blocks of 256x8-bits during 20 years ( at 55oC ) • Single supply (Ucc=2,7 ÷ 5,5 V); • Automatically increased word's address • On-chip voltage multiplier • Serial input/output I2C-bus • 1000000 ERASE/WRITE cycles per byte • Internal timer for writing (no external components) • Write operations: multi byte write mode to 32 bytes • Write - protection input • Power-on-reset Temperature range: -40oC ÷ +85oC PIN DESCRIPTION Simbol n. c. n. c n. c Uss SDA SCL WP Ucc Pin 1 2 3 4 5 6 7 8 PIN CONFIGURATION Description not connected not connected not connected negative supply voltage serial data input/output ( I2Cbus) serial clock input ( I2C-bus) write - protection input positive supply voltage n. c. 1 8 n. c. 2 7 n. c. 3 6 SCL Uss 4 5 SDA Ucc WP INF85116N Table 1. Quick reference data Symbol Parameter min 1 max Unit INF85116 UDD IOL Tamb Supply voltage LOW level output current Operating ambient temperature 2.7 -40 5.5 6 +85 V mА °С BLOCK DIAGRAM 7 VDD 8 SCL 6 5 SDA Input filter VSS Test mode register I2C-bus control logic Address comparator Address pointer Shift register Sequenser HV generator Column decoder Divider Page register EEPROM ARRAY (8x256x8) Row dec Oscillator Power-on-reset 4 WP VSS Table 2. Limiting values Symbol UDD Ui Ii Io Tstg Parameter Supply voltage Input voltage on any pin /Zi/>500 Ω Input current on any pin Output current Storage temperature 2 min -0.3 -0.8 max 6.5 6.5 Unit V V -65 1 10 +150 mА mА °С INF85116 Table 3. Characteristics Symbol IDD(stb) Parameter Standby supply current ICCR Supply current READ ICCW Supply current E / W WP input (pin 7) UIL LOW level input voltage UIH HIGH level input voltage SCL input (pin 6) UIL LOW level input voltage UIH HIGH level input voltage ILI Input leakage current fSCL Clock input frequency tsp Pulse width of spikes suppressed by filter СI Input capacitance SDA input/output (pin 5) UIL LOW level input voltage UIH HIGH level input voltage UOL1 LOW level output voltage UOL2 ILO tO(F) Output leakage current Output fall time from UIHmin to UILmax tSP Pulse width of spikes suppressed by filter Input capacitance E/W cycle time E/W cycle per byte СI tE/W NE/W Conditions UDD = 2.7V UDD = 5.5V fSСL=400кHz, UDD = 5.5V fSСL=400кHz, UDD = 5.5V UI=UDD or USS UI= USS IOL=3mА, UDD = UDD (min) IOL=6mА, UDD = UDD (min) UOH=UDD with up to 3mА sink current at UOL1 with up to 6mА sink current at UOL2 UI=0V min - max 6 10 1 Unit µА µА mА - 1 mА -0.8 0.9UDD +0.1UDD UDD+0.8 V V -0.8 0.7UDD 0 0 +0.3UDD 6.5 ±1 400 V V µА kHz 100 ns 7 pF 0.3UDD 6.5 0.4 V V V -0.8 0.7UDD - 0.6 - 1 µА 20+0.1 CB* 250 ns 20+0.1 CB 250 ns 0 100 ns 10 10 100000 Тamb =(-40-+85) оС, 1000000 Тamb =22оС tS Data retention time Тamb = 55оС 20 ∗ - The bus capacitance ranges from 10 to 400pF ( CB = total capacitance of one bus line in pF) 3 pF ms years INF85116 Таble 4. I2C-bus characteristics Symbol fSCL tBUF tHD, STA tLOW tHIGH tSU, STA tHD, DAT Parameter Conditions Clock frequency Time the bus must be free before START condition hold time after which first clock pulse is generated LOW level clock period HIGH level clock period Set-up time for START condition tHD, DAT tSU, DAT tR Data hold time for CBUS compatible masters Data hold time for I2C - bus devices Data set-up time SDA and SCL rise time tF SDA and SCL fall time Standard mode min max 0 100 4.7 4.0 - Fast mode Unit min 0 1.3 0.6 max 400 - kHz µs µs repeated start - 4.7 4.0 4.7 - 1.3 0.6 0.6 - µs µs µs 5 - - - µs note 1 - 0 250 - 1000 300 ns ns ns - - 300 0 100 20+0. 1 Cb(2) 20+0. 1 Cb(2) 0.6 300 ns - tSU, STO Set-up time for STOP condition 4.0 µs Notes: 1. The hold time required (not greater than 300 ns) to bridge the undefined region of the falling edge of SCL must be internally provided by a transmitter. 2. Cb = total capacitance of one bus line in pF. 4