CYPRESS CY7C1021CV26

CY7C1021CV26
1-Mbit (64K x 16) Static RAM
Features
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A15). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A15).
• Temperature Range
— Automotive: –40°C to 125°C
• High speed
— tAA = 15 ns
• Optimized voltage range: 2.5V–2.7V
• Low active power: 360 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• CMOS for optimum speed/power
• Package offered: 44-pin TSOP II
Functional Description
The CY7C1021CV26 is a high-performance CMOS static
RAM organized as 65,536 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the end of this data sheet for a complete
description of Read and Write modes.
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a Write operation
(CE LOW, and WE LOW).
Logic Block Diagram
64K x 16
RAM Array
512 X 2048
SENSE AMPS
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
I/O1–I/O8
I/O9–I/O16
COLUMN DECODER
A8
A9
A10
A11
A12
A13
A14
A15
BHE
WE
CE
OE
BLE
Selection Guide
CY7C1021CV26-15
Maximum Access Time (ns)
15
Maximum Operating Current (mA)
80
Maximum CMOS Standby Current (mA)
10
Note:
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25°C.
Cypress Semiconductor Corporation
Document #: 38-05589 Rev. **
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised June 22, 2004
CY7C1021CV26
Pin Configuration
TSOP II -Top View
A4
A3
A2
A1
A0
CE
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE
A15
A14
A13
A12
NC
1
44
2
3
43
42
4
41
40
39
38
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
Pin Definitions
Pin Name
Pin Number
I/O Type
Description
A0–A15
1–5, 18–21, Input
24–27,
42–44
Address Inputs used to select one of the address locations.
I/O1–I/O16
7–10,
13–16,
29–32,
35–38
Input/Output
Bidirectional Data I/O lines. Used as input or output lines depending on
operation.
NC
22, 23, 28
No Connect
No Connects. This pin is not connected to the die.
WE
17
Input/Control
Write Enable Input, active LOW. When selected LOW, a Write is conducted.
When selected HIGH, a Read is conducted.
CE
6
Input/Control
Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
BHE, BLE
39, 40
Input/Control
Byte Write Select Inputs, active LOW. BLE controls I/O8–I/O1, BHE controls
I/O16–I/O9.
OE
41
Input/Control
Output Enable, active LOW. Controls the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
VSS
12, 34
Ground
Ground for the device. Should be connected to ground of the system.
VCC
11, 33
Power Supply
Power Supply inputs to the device.
Note:
2. NC pins are not connected on the die.
Document #: 38-05589 Rev. **
Page 2 of 9
CY7C1021CV26
Maximum Ratings
DC Input Voltage[3] ................................ –0.5V to VCC + 0.5V
(Above which the useful life may be impaired. For user guidelines, not tested.)
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage............................................ >2001V
(per MIL-STD-883, Method 3015)
Storage Temperature ................................. –65°C to +150°C
Latch-up Current...................................................... >200 mA
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Operating Range
Supply Voltage on VCC to Relative GND[3] .... –0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[3] ......................................–0.5V to VCC+0.5V
Ambient
Temperature
VCC
–40°C to +125°C
2.5V–2.7V
Range
Automotive
Electrical Characteristics Over the Operating Range
CY7C1021CV26-15
Parameter
Description
Test Conditions
VOH
Output HIGH Voltage
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 1.0 mA
Min.
Max.
Unit
2.3
V
VOL
Output LOW Voltage
0.4
V
VIH
Input HIGH Voltage
2.0
VCC + 0.3
V
VIL
Input LOW Voltage[3]
–0.3
0.8
V
IIX
Input Load Current
GND < VI < VCC
–3
+3
µA
IOZ
Output Leakage Current
GND < VI < VCC, Output Disabled
–3
+3
µA
IOS
Output Short Circuit Current[4]
VCC = Max., VOUT = GND
–300
mA
ICC
VCC Operating Supply Current
VCC = Max., IOUT = 0 mA,
f = fMAX = 1/tRC
80
mA
ISB1
Automatic CE Power-Down
Current —TTL Inputs
Max. VCC, CE > VIH
VIN > VIH or VIN < VIL, f = fMAX
15
mA
ISB2
Automatic CE Power-Down
Current —CMOS Inputs
Max. VCC,
CE > VCC – 0.3V, VIN > VCC – 0.3V,
or VIN < 0.3V, f = 0
10
mA
Capacitance[5]
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 2.6V
Max.
Unit
8
pF
8
pF
Thermal Resistance[5]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)[5]
ΘJC
Thermal Resistance
(Junction to Case)[5]
Test Conditions
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
44-lead
TSOP-II
Unit
76.92
°C/W
15.86
°C/W
Notes:
3. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
4. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
5. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05589 Rev. **
Page 3 of 9
CY7C1021CV26
AC Test Loads and Waveforms[6]
R1
1830Ω
2.6 V
ALL INPUT PULSES
2.6V
OUTPUT
90%
GND
10%
R2
30 pF
INCLUDING
JIG AND
SCOPE
90%
10%
1976Ω
(a)
Fall Time: 1 V/ns
Rise Time: 1 V/ns
High-Z characteristics:
(b)
2.6V
R 317Ω
OUTPUT
R2
351Ω
5 pF
(c)
Switching Characteristics Over the Operating Range[7]
CY7C1021CV26-15
Parameter
Description
Min.
Max.
Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Address Change
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z[8]
15
15
3
OE HIGH to
tLZCE
CE LOW to Low-Z[8]
15
ns
7
ns
ns
7
3
High-Z[8, 9]
ns
ns
0
High-Z[8, 9]
tHZOE
ns
ns
ns
tHZCE
CE HIGH to
tPU[10]
tPD[10]
CE LOW to Power-Up
CE HIGH to Power-Down
15
ns
tDBE
Byte Enable to Data Valid
7
ns
tLZBE
Byte Enable to Low-Z
tHZBE
Byte Disable to High-Z
Write
7
0
ns
ns
0
ns
7
ns
Cycle[11]
tWC
Write Cycle Time
15
ns
tSCE
CE LOW to Write End
10
ns
tAW
Address Set-Up to Write End
10
ns
tHA
Address Hold from Write End
0
ns
tSA
Address Set-Up to Write Start
0
ns
tPWE
WE Pulse Width
10
ns
tSD
Data Set-Up to Write End
8
ns
tHD
Data Hold from Write End
0
ns
Notes:
6. AC characteristics (except High-Z) are tested using the Thevenin load shown in Figure (a). High-Z characteristics are tested for all speeds using the test load
shown in Figure (c).
7. Test conditions assume signal transition time of 2.6 ns or less, timing reference levels of 1.3V, input pulse levels of 0 to 2.6V.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. This parameter is guaranteed by design and is not tested.
11. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write,
and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
Document #: 38-05589 Rev. **
Page 4 of 9
CY7C1021CV26
Switching Characteristics Over the Operating Range[7] (continued)
CY7C1021CV26-15
Parameter
Description
Min.
WE HIGH to Low-Z[8]
tLZWE
Max.
ns
[8, 9]
tHZWE
WE LOW to High-Z
tBW
Byte Enable to End of Write
Unit
3
7
ns
9
ns
Switching Waveforms
Read Cycle No. 1[12, 13]
tRC
ADDRESS
tOHA
DATA OUT
tAA
PREVIOUS DATA VALID
DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
ADDRESS
tRC
CE
tACE
OE
tHZOE
tDOE
BHE, BLE
tLZOE
tHZCE
tDBE
tLZBE
DATA OUT
HIGH IMPEDANCE
tLZCE
VCC
SUPPLY
CURRENT
tHZBE
DATA VALID
HIGH
IMPEDANCE
tPD
tPU
50%
50%
IICC
CC
IISB
SB
Notes:
12. Device is continuously selected. OE, CE, BHE and/or BLE = VIL.
13. WE is HIGH for Read cycle.
14. Address valid prior to or coincident with CE transition LOW.
Document #: 38-05589 Rev. **
Page 5 of 9
CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 1 (CE Controlled)[15, 16]
tWC
ADDRESS
CE
tSA
tSCE
tAW
tHA
tPWE
WE
tBW
BHE, BLE
tSD
tHD
DATA I/O
Write Cycle No. 2 (BLE or BHE Controlled)
tWC
ADDRESS
BHE, BLE
tSA
tBW
tAW
tHA
tPWE
WE
tSCE
CE
tSD
tHD
DATA I/O
Notes:
15. Data I/O is high-impedance if OE or BHE and/or BLE= VIH.
16. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 38-05589 Rev. **
Page 6 of 9
CY7C1021CV26
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, LOW)
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE, BLE
tHZWE
tSD
tHD
DATA I/O
tLZWE
Truth Table
CE
OE
WE
H
X
X
X
X
High-Z
High-Z
Power-down
Standby (ISB)
L
L
H
L
L
Data Out
Data Out
Read – All bits
Active (ICC)
L
H
Data Out
High-Z
Read – Lower bits only
Active (ICC)
H
L
High-Z
Data Out
Read – Upper bits only
Active (ICC)
L
L
Data In
Data In
Write – All bits
Active (ICC)
L
H
Data In
High-Z
Write – Lower bits only
Active (ICC)
L
X
L
BLE
BHE
I/O1–I/O8
I/O9–I/O16
Mode
Power
H
L
High-Z
Data In
Write – Upper bits only
Active (ICC)
L
H
H
X
X
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
L
X
X
H
H
High-Z
High-Z
Selected, Outputs Disabled
Active (ICC)
Ordering Information
Speed
(ns)
15
Ordering Code
CY7C1021CV26-15ZE
Document #: 38-05589 Rev. **
Package
Name
Z44
Package Type
44-lead TSOP Type II
Operating
Range
Automotive
Page 7 of 9
CY7C1021CV26
Package Diagrams
44-pin TSOP II Z44
51-85087-*A
All products and company names mentioned in this document are the trademarks of their respective holders.
Document #: 38-05589 Rev. **
Page 8 of 9
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C1021CV26
Document History Page
Document Title: CY7C1021CV26 1-Mbit (64K x 16) Static RAM
Document Number: 38-05589
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
238454
See ECN
RKF
Document #: 38-05589 Rev. **
Description of Change
New datasheet for Automotive
Page 9 of 9