CY7C1020CV33 512K (32K x 16) Static RAM Features Functional Description • Pin- and function-compatible with CY7C1020V33 • Temperature Ranges — Commercial: 0°C to 70°C — Industrial: –40°C to 85°C The CY7C1020CV33 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). — Automotive: –40°C to 125°C • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — 325 mW (max.) • Automatic power-down when deselected • Independent control of upper and lower bits • Available in Pb-free and non Pb-free 44-pin TSOP II package Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1020CV33 is available in standard 44-pin TSOP Type II package. Logic Block Diagram PinConfiguration[1] TSOP II Top View SENSE AMPS A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K × 16 RAM Array I/O1–I/O8 I/O9–I/O16 COLUMN DECODER A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE NC A3 A2 A1 A0 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A4 A14 A13 A12 NC 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A8 A9 A10 A11 NC Note: 1. NC pins are not connected on the die Cypress Semiconductor Corporation Document #: 38-05133 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 3, 2006 [+] Feedback CY7C1020CV33 Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current -10 -12 -15 Unit 10 12 15 ns Com’l/Ind’l 90 85 80 mA Automotive - - 85 mA Com’l/Ind’l 5 5 5 mA Automotive - - 10 mA Pin Definitions Pin Name TSOP - Pin Number I/O Type A0–A14 5, 4, 3, 2, 18, 44, 43, 42, 27, 26, 25, 24, 21, 20, 19 Input I/O1–I/O16 7-10, 13-16, 29-32, 35-38 NC 1, 22, 23, 28 WE 17 Input/Control Write Enable Input, active LOW. When selected LOW, a Write is conducted. When deselected HIGH, a Read is conducted. CE 6 Input/Control Chip Enable Input, active LOW. When LOW, selects the chip. When HIGH, deselects the chip. BHE, BLE 40, 39 OE 41 VSS 12, 34 VCC 11, 33 Document #: 38-05133 Rev. *E Description Address Inputs used to select one of the address locations. Input/Output Bidirectional Data I/O lines. Used as input or output lines depending on operation. No Connect No Connects. Not connected to the die. Input/Control Byte Write Select Inputs, active LOW. BHE controls I/O16–I/O9, BLE controls I/O8–I/O1. Input/Control Output Enable, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. Ground Ground for the device. Should be connected to ground of the system. Power Supply Power Supply inputs to the device. Page 2 of 9 [+] Feedback CY7C1020CV33 Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied............................................. –55°C to +125°C Supply Voltage on VCC to Relative GND[1] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V [2] DC Input Voltage .................................–0.5V to VCC + 0.5V Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Operating Range Range Ambient Temperature VCC 0°C to +70°C 3.3V ± 10% Industrial –40°C to +85°C 3.3V ± 10% Automotive –40°C to +125°C 3.3V ± 10% Commercial Electrical Characteristics Over the Operating Range -10 Parameter Description Test Conditions Min. -12 Max. -15 Max. Min. VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 VCC + 0.3 2.0 VCC + 0.3 VIL Input LOW Voltage[2] −0.3 0.8 –0.3 0.8 IIX Input Leakage Current −1 +1 –1 +1 IOZ ICC ISB1 ISB2 GND < VI < VCC 2.4 Min. 2.4 0.4 Com’l/Ind’l 2.4 0.4 Auto Output Leakage GND < VI < VCC, Current Output Disabled Com’l/Ind’l VCC Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX = 1/tRC Com’l/Ind’l −1 +1 –1 +1 Auto 90 Max. VCC, CE > VIH Com’l/Ind’l VIN > VIH or VIN < VIL, Auto f = fMAX 15 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 5 Com’l/Ind’l Unit V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V –1 +1 µA –20 +20 µA –1 +1 µA –20 +20 µA 80 mA 85 mA 15 mA 20 mA 5 mA 10 mA 85 Auto Automatic CE Power-down Current —TTL Inputs Max. 15 5 Auto Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 3.3V Max. Unit 8 pF 8 pF Thermal Resistance[3] Parameter ΘJA ΘJC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions 44-pin TSOP-II Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 76.92 °C/W 15.86 °C/W Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05133 Rev. *E Page 3 of 9 [+] Feedback CY7C1020CV33 AC Test Loads and Waveforms[4] R 317Ω 3.0V 90% 90% OUTPUT R2 351Ω 30 pF High-Z characteristics: R 317 Ω 3.3V ALL INPUT PULSES 3.3V GND 10% 10% OUTPUT R2 351Ω 5 pF (a) (b) Rise Time: 1 V/ns Fall Time: 1 V/ns (c) Switching Characteristics Over the Operating Range[4] -10 Parameter Description Min. -12 Max. Min. -15 Max. Min. Max. Unit Read Cycle tRC Read Cycle Time tAA Address to Data Valid 10 tOHA Data Hold from Address Change tACE CE LOW to Data Valid 10 12 15 ns tDOE OE LOW to Data Valid 5 6 7 ns OE LOW to Low-Z[5] tHZOE OE HIGH to High-Z[5, 6] tLZCE CE LOW to Low-Z[5] tLZOE 12 10 3 3 0 5 ns 15 3 0 3 High-Z[5, 6] 15 12 ns 0 6 3 ns ns 7 ns 3 ns tHZCE CE HIGH to tPU[7] tPD[7] CE LOW to Power-up CE HIGH to Power-down 10 12 15 ns tDBE Byte Enable to Data Valid 5 6 7 ns tLZBE Byte Enable to Low-Z tHZBE Byte Disable to High-Z 5 0 6 0 0 ns 0 0 5 7 ns 0 6 ns 7 ns Write Cycle[8] tWC Write Cycle Time 10 12 15 ns tSCE CE LOW to Write End 8 9 10 ns tAW Address Set-up to Write End 7 8 10 ns tHA Address Hold from Write End 0 0 0 ns tSA Address Set-up to Write Start 0 0 0 ns tPWE WE Pulse Width 7 8 10 ns tSD Data Set-up to Write End 5 6 8 ns tHD Data Hold from Write End 0 0 0 ns [5] tLZWE WE HIGH to Low-Z tHZWE WE LOW to High-Z[5, 6] tBW Byte Enable to End of Write 3 3 5 7 3 6 8 ns 7 9 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. 5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 6. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (c) of AC Test Loads. Transition is measured ± 500 mV from steady-state voltage. 7. This parameter is guaranteed by design and is not tested. 8. The internal Write time of the memory is defined by the overlap of CE LOW, WE LOW and BHE/BLE LOW. CE, WE and BHE/BLE must be LOW to initiate a Write, and the transition of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. Document #: 38-05133 Rev. *E Page 4 of 9 [+] Feedback CY7C1020CV33 Switching Waveforms Read Cycle No. 1[9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[10, 11] ADDRESS tRC CE tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB Notes: 9. Device is continuously selected. OE, CE, BHE and/or BHE = VIL. 10. WE is HIGH for Read cycle. 11. Address valid prior to or coincident with CE transition LOW. Document #: 38-05133 Rev. *E Page 5 of 9 [+] Feedback CY7C1020CV33 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[12, 13] tWC ADDRESS CE tSA tSCE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATA I/O Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATA I/O Notes: 12. Data I/O is high impedance if OE or BHE and/or BLE = VIH. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05133 Rev. *E Page 6 of 9 [+] Feedback CY7C1020CV33 Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE OE WE H X X X X High-Z High-Z Power-down Standby (ISB) L L H L L Data Out Data Out Read—All bits Active (ICC) L H Data Out High-Z Read—Lower bits only Active (ICC) L X L BLE BHE I/O1–I/O8 I/O9–I/O16 Mode Power H L High-Z Data Out Read—Upper bits only Active (ICC) L L Data In Data In Write—All bits Active (ICC) L H Data In High-Z Write—Lower bits only Active (ICC) H L High-Z Data In Write—Upper bits only Active (ICC) L H H X X High-Z High-Z Selected, Outputs Disabled Active (ICC) L X X H H High-Z High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Diagram 10 CY7C1020CV33-10ZC 51-85087 CY7C1020CV33-10ZXC 44-pin TSOP Type II (Pb-Free) 12 CY7C1020CV33-12ZC 44-pin TSOP Type II Commercial 15 CY7C1020CV33-15ZC 44-pin TSOP Type II Commercial CY7C1020CV33-15ZE 44-pin TSOP Type II Automotive CY7C1020CV33-15ZSXE 44-pin TSOP Type II (Pb-Free) Document #: 38-05133 Rev. *E Package Type 44-pin TSOP Type II Operating Range Commercial Page 7 of 9 [+] Feedback CY7C1020CV33 Package Diagrams 44-Pin TSOP II (51-85087) DIMENSION IN MM (INCH) MAX MIN. PIN 1 I.D. 1 23 10.262 (0.404) 10.058 (0.396) 11.938 (0.470) 11.735 (0.462) 22 EJECTOR PIN 44 TOP VIEW 0.800 BSC (0.0315) OR E K X A SG BOTTOM VIEW 0.400(0.016) 0.300 (0.012) 10.262 (0.404) 10.058 (0.396) BASE PLANE 0.210 (0.0083) 0.120 (0.0047) 0°-5° 0.10 (.004) 0.150 (0.0059) 0.050 (0.0020) 1.194 (0.047) 0.991 (0.039) 18.517 (0.729) 18.313 (0.721) SEATING PLANE 0.597 (0.0235) 0.406 (0.0160) 51-85087-*A All products and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-05133 Rev. *E Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1020CV33 Document History Page Document Title: CY7C1020CV33 512K (32K x 16) Static RAM Document Number: 38-05133 REV. ECN NO. Issue Date Orig. of Change ** 109428 12/16/01 HGK New Data Sheet *A 115045 05/30/02 HGK ICC and ISB1 data modified *B 117615 08/14/02 DFP Pin 1= NC Pin 18 = A4; remove SOJ package option; remove 8ns option. *C 262949 See ECN RKF Added Automotive Specs to Data sheet *D 334398 See ECN SYT Added Lead-Free Product Information *E 493543 See ECN NXR Added note #1 on page #1 Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated Ordering Information Table Document #: 38-05133 Rev. *E Description of Change Page 9 of 9 [+] Feedback