RENESAS R8C-33A

PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
R8C/33A Group
REJ03B0228-0010
Rev.0.10
Mar 17, 2008
RENESAS MCU
1.
Overview
1.1
Features
The R8C/33A Group of single-chip MCUs incorporates the R8C/Tiny Series CPU core, employing sophisticated
instructions for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions
at high speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs also
use an anti-noise configuration to reduce emissions of electromagnetic noise and are designed to withstand EMI.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/33A Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
REJ03B0228-0010 Rev.0.10
Page 1 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/33A Group.
Table 1.1
Item
CPU
Specifications for R8C/33A Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RE
REJ03B0228-0010 Rev.0.10
Page 2 of 53
Specification
R8C/Tiny series core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)
100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)
500 ns (f(XIN) = 2 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/33A Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 27, selectable pull-up resistor
• High current drive ports: 27
4 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• Number of interrupt vectors: 69
• External Interrupt: 7 (INT × 3, Key input × 4)
• Priority levels: 7 levels
• 15 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 23
• Transfer modes: 2 (normal mode, repeat mode)
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 1.2
Item
Serial
Interface
1. Overview
Specifications for R8C/33A Group (2)
Function
UART0, UART1
UART2
Synchronous Serial
Communication Unit (SSU)
I2C bus
LIN Module
A/D Converter
D/A Converter
Comparator A
Comparator B
Flash Memory
Operating Frequency/Supply
Voltage
Current Consumption
Operating Ambient Temperature
Package
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O/UART, I2C mode (I2C-bus),
multiprocessor communication function
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
8-bit resolution × 2 circuits
• 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input available
2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function
f(XIN) = 20 MHz (VCC = 3.0 to 5.5 V)
f(XIN) = 10 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 2.2 to 5.5 V)
f(XIN) = 2 MHz (VCC = 1.8 to 5.5 V)
TBD (VCC = 5.0 V, f(XIN) = 20 MHz)
TBD (VCC = 3.0 V, f(XIN) = 10 MHz)
TBD (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
TBD (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version) (1)
32-pin LQFP
Package code: PLQP0032GB-A (previous code: 32P6U-A)
Note:
1. Specify the D version if D version functions are to be used.
REJ03B0228-0010 Rev.0.10
Page 3 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/33A Group, and Figure 1.1 shows a Part Number, Memory Size, and Package
of R8C/33A Group.
Table 1.3
Product List for R8C/33A Group
Part No.
R5F21331ANFP (D)
R5F21332ANFP (D)
R5F21334ANFP (D)
R5F21335ANFP (D)
R5F21336ANFP (D)
R5F21331ADFP (D)
R5F21332ADFP (D)
R5F21334ADFP (D)
R5F21335ADFP (D)
R5F21336ADFP (D)
ROM Capacity
Program ROM
Data flash
4 Kbytes
1 Kbyte × 4
8 Kbytes
1 Kbyte × 4
16 Kbytes
1 Kbyte × 4
24 Kbytes
1 Kbyte × 4
32 Kbytes
1 Kbyte × 4
4 Kbytes
1 Kbyte × 4
8 Kbytes
1 Kbyte × 4
16 Kbytes
1 Kbyte × 4
24 Kbytes
1 Kbyte × 4
32 Kbytes
1 Kbyte × 4
Current of Mar. 2008
RAM
Capacity
512 bytes
1 Kbyte
1.5 Kbytes
2 Kbytes
2.5 Kbytes
512 bytes
1 Kbyte
1.5 Kbytes
2 Kbytes
2.5 Kbytes
Package Type
Remarks
PLQP0032GB-A N version
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A D version
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
PLQP0032GB-A
(D): Under development
Part No.
R 5 F 21 33 6 A N FP
Package type:
FP: PLQP0032GB-A (0.8 mm pin-pitch, 7 mm square body)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
1: 4 KB
2: 8 KB
4: 16 KB
5: 24 KB
6: 32 KB
R8C/33A Group
R8C/Tiny Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/33A Group
REJ03B0228-0010 Rev.0.10
Page 4 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
8
8
3
5
Port P0
Port P1
Port P2
Port P3
3
1
Port P4
Peripheral functions
Timers
UART or
clock synchronous serial I/O
(8 bits × 3)
System clock generation
circuit
I2C bus or SSU
(8 bits × 1)
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RE (8 bits × 1)
LIN module
Low-speed on-chip oscillator
for watchdog timer
Watchdog timer
(15 bits)
Comparator B
Voltage detection circuit
A/D converter
(10 bits × 12 channels)
Comparator A
D/A converter
(8 bits × 2)
DTC
R8C/Tiny Series CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ROM (1)
USP
ISP
INTB
A0
A1
FB
Memory
RAM (2)
PC
FLG
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
REJ03B0228-0010 Rev.0.10
Page 5 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
1.4
1. Overview
Pin Assignment
P1_7/IVCMP1/INT1(/TRAIO)
P1_6/LVCOUT2/IVREF1(/CLK0)
P1_3/AN11/LVCOUT1/Kl3/TRBO(/TRCIOC)
P1_4(/TXD0/TRCCLK)
P1_5(/INT1/RXD0/TRAIO)
P1_2/AN10/LVREF/Kl2(/TRCIOB)
P1_0/AN8/LVCMP1/KI0(/TRCIOD)
P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)
Figure 1.3 shows Pin Assignment (Top View). Table 1.4 outlines the Pin Name Information by Pin Number.
24 23 22 21 20 19 18 17
P0_7/AN0/DA1(/TRCIOC)
25
16
P0_6/AN1/DA0(/TRCIOD)
P0_5/AN2(/TRCIOB)
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/CLK1/TRCIOB)
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
P0_0/AN7(/TRCIOA/TRCTRG)
26
15
27
14
R8C/33A Group
13
28
29
12
PLQP0032GB-A
(32P6U-A)
(top view)
30
31
11
10
9
MODE
RESET
P4_7/XOUT(/XCOUT)
4
5
6
7
8
VCC/AVCC
3
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)
2
VSS/AVSS
P4_6/XIN(/XCIN)
1
P4_2/VREF
32
P4_5/ADTRG/INT0(/RXD2/SCL2)
P3_1(/TRBO)
P2_0(/INT1/TRCIOB)
P2_1(/TRCIOC)
P2_2(/TRCIOD)
P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
P3_5/SCL/SSCK(/CLK2/TRCIOD)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
REJ03B0228-0010 Rev.0.10
Page 6 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 1.4
1. Overview
Pin Name Information by Pin Number
I/O Pin Functions for Peripheral Modules
Pin
Number
1
2
3
4
5
6
7
8
Control Pin
Port
Interrupt
Serial
Interface
Timer
SSU
I2 C
bus
P4_2
A/D Converter,
D/A Converter,
Comparator A,
Comparator B,
Voltage Detection Circuit
VREF
MODE
RESET
XOUT(/XCOUT)
VSS/AVSS
XIN(/XCIN)
VCC/AVCC
P4_7
P4_6
P3_7
TRAO
9
10
P3_5
P3_4
(TRCIOD)
(TRCIOC)
11
P3_3
12
13
14
P2_2
P2_1
P2_0
15
16
P3_1
P4_5
17
P1_7
18
19
P1_6
P1_5
20
21
P1_4
P1_3
22
P1_2
KI2
23
P1_1
KI1
24
P1_0
KI0
25
26
27
P0_7
P0_6
P0_5
28
P0_4
29
P0_3
30
P0_2
31
P0_1
32
P0_0
INT3
(TRCCLK)
(INT1)
(TRCIOD)
(TRCIOC)
(TRCIOB)
(RXD2/SCL2/ SSO SDA
TXD2/SDA2)
(CLK2)
SSCK SCL
(RXD2/SCL2/
SSI
TXD2/SDA2)
(CTS2/RTS2)
IVCMP3
(TRBO)
INT0
INT1
(TRAIO)
(INT1)
(TRAIO)
KI3
(TRCCLK)
TRBO
(/TRCIOC)
(TRCIOB)
(RXD2/SCL2)
ADTRG
IVCMP1
(CLK0)
(RXD0)
LVCOUT2/IVREF1
Mar 17, 2008
(TXD0)
AN11/LVCOUT1
AN10/LVREF
(TRCIOA/
TRCTRG)
(TRCIOD)
(TRCIOC)
(TRCIOD)
(TRCIOB)
TREO
(/TRCIOB)
(TRCIOB)
(TRCIOA/
TRCTRG)
(TRCIOA/
TRCTRG)
(TRCIOA/
TRCTRG)
Note:
1. Can be assigned to the pin in parentheses by a program.
REJ03B0228-0010 Rev.0.10
Page 7 of 53
SCS
IVREF3
AN9/LVCMP2
AN8/LVCMP1
AN0/DA1
AN1/DA0
AN2
AN3
(CLK1)
AN4
(RXD1)
AN5
(TXD1)
AN6
AN7
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
1.5
1. Overview
Pin Functions
Tables 1.5 and 1.6 list Pin Functions.
Table 1.5
Pin Functions (1)
Item
Pin Name
I/O Type
Description
Power supply input
VCC, VSS
−
Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
I/O (2)
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins (1). To use an external clock, input it
to the XOUT pin and leave the XIN pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0, INT1, INT3
I
INT interrupt input pins.
INT0 is timer RB, and RC input pin.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
I/O
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins (1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
Timer RA I/O pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
Timer RE
TREO
O
Divided clock output pin
Serial interface
CLK0, CLK1, CLK2
I/O
RXD0, RXD1, RXD2
I
TXD0, TXD1, TXD2
O
Serial data output pins
CTS2
I
Transmission control input pin
RTS2
O
Reception control output pin
SCL2
I/O
I2C mode clock I/O pin
SDA2
I/O
I2C mode data I/O pin
I2C
bus
SSU
Transfer clock I/O pins
Serial data input pins
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
I: Input
O: Output
I/O: Input and output
Notes:
1. Refer to the oscillator manufacturer for oscillation characteristics.
2. To use an externally generated clock, input it to XOUT.
REJ03B0228-0010 Rev.0.10
Page 8 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
1. Overview
Table 1.6
Pin Functions (2)
Item
Pin Name
I/O Type
Description
Reference voltage
input
VREF
I
Reference voltage input pin to A/D converter and D/A
converter
A/D converter
AN0 to AN11
I
Analog input pins to A/D converter
ADTRG
I
AD external trigger input pin
D/A converter
DA0, DA1
O
D/A converter output pins
Comparator A
LVCMP1, LVCMP2
I
Comparator A analog voltage input pins
LVREF
I
Comparator A reference voltage input pin
LVCOUT1, LVCOUT2
O
Comparator A output pins
IVCMP1, IVCMP3
I
Comparator B analog voltage input pins
Comparator B
IVREF1, IVREF3
I
Comparator B reference voltage input pins
Voltage detection
circuit
LVCMP2
I
Detection voltage input pin for voltage detection 2
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_2,
P3_1,
P3_3 to P3_5,
P3_7,
P4_5 to P4_7
Input port
P4_2
I: Input
O: Output
REJ03B0228-0010 Rev.0.10
Page 9 of 53
I/O
I
I/O: Input and output
Mar 17, 2008
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
All ports can be used as LED drive ports.
Input-only port
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
REJ03B0228-0010 Rev.0.10
Page 10 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
REJ03B0228-0010 Rev.0.10
Page 11 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
REJ03B0228-0010 Rev.0.10
Page 12 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
3.
3. Memory
Memory
3.1
R8C/33A Group
Figure 3.1 is a Memory Map of R8C/33A Group. The R8C/33A Group has a 1-Mbyte address space from addresses
00000h to FFFFFh. The internal ROM (program ROM) is allocated lower addresses, beginning with address
0FFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to 0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0FFD8h
0XXXXh
02C00h
02FFFh
03000h
Reserved area
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Size
Internal RAM
Address 0YYYYh
Address ZZZZZh
Size
Address 0XXXXh
R5F21331ANFP, R5F21331ADFP
R5F21332ANFP, R5F21332ADFP
4 Kbytes
0F000h
−
512 bytes
005FFh
8 Kbytes
0E000h
−
1 Kbyte
007FFh
R5F21334ANFP, R5F21334ADFP
R5F21335ANFP, R5F21335ADFP
16 Kbytes
24 Kbytes
0C000h
0A000h
−
−
1.5 Kbytes
2 Kbytes
009FFh
00BFFh
R5F21336ANFP, R5F21336ADFP
32 Kbytes
08000h
−
2.5 Kbytes
00DFFh
Figure 3.1
Memory Map of R8C/33A Group
REJ03B0228-0010 Rev.0.10
Page 13 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXX00XXb (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
CPSRF
FRA4
FRA5
FRA6
00h
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit/Comparator A Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (4)
1100X011b (5)
10001010b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Software reset, watchdog timer reset, or oscillation
stop detection reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
REJ03B0228-0010 Rev.0.10
Page 14 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Address
Register
003Ah
Voltage Monitor 2 Circuit Control Register
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
Flash Memory Ready Interrupt Control Register
0042h
0043h
0044h
0045h
0046h
0047h
Timer RC Interrupt Control Register
0048h
0049h
004Ah
Timer RE Interrupt Control Register
004Bh
UART2 Transmit Interrupt Control Register
004Ch
UART2 Receive Interrupt Control Register
004Dh
Key Input Interrupt Control Register
004Eh
A/D Conversion Interrupt Control Register
004Fh
SSU Interrupt Control Register / IIC bus Interrupt Control Register (2)
0050h
0051h
UART0 Transmit Interrupt Control Register
0052h
UART0 Receive Interrupt Control Register
0053h
UART1 Transmit Interrupt Control Register
0054h
UART1 Receive Interrupt Control Register
0055h
0056h
Timer RA Interrupt Control Register
0057h
0058h
Timer RB Interrupt Control Register
0059h
INT1 Interrupt Control Register
005Ah
INT3 Interrupt Control Register
005Bh
005Ch
005Dh
INT0 Interrupt Control Register
005Eh
UART2 Bus Collision Detection Interrupt Control Register
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
Voltage Monitor 1/Compare A1 Interrupt Control Register
0073h
Voltage Monitor 2/Compare A2 Interrupt Control Register
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0228-0010 Rev.0.10
Page 15 of 53
Mar 17, 2008
VW2C
Symbol
After Reset
10000010b
FMRDYIC
XXXXX000b
TRCIC
XXXXX000b
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC / IICIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
S0TIC
S0RIC
S1TIC
S1RIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
TRAIC
XXXXX000b
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.3
Address
0080h
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
0089h
008Ah
008Bh
008Ch
008Dh
008Eh
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
00A1h
00A2h
00A3h
00A4h
00A5h
00A6h
00A7h
00A8h
00A9h
00AAh
00ABh
00ACh
00ADh
00AEh
00AFh
00B0h
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
00BCh
00BDh
00BEh
00BFh
4. Special Function Registers (SFRs)
SFR Information (3) (1)
DTC Activation Control Register
Register
Symbol
DTCTL
00h
DTC Activation Enable Register 0
DTC Activation Enable Register 1
DTC Activation Enable Register 2
DTC Activation Enable Register 3
DTCEN0
DTCEN1
DTCEN2
DTCEN3
00h
00h
00h
00h
DTC Activation Enable Register 5
DTC Activation Enable Register 6
DTCEN5
DTCEN6
00h
00h
UART0 Transmit/Receive Mode Register
UART0 Bit Rate Register
UART0 Transmit Buffer Register
U0MR
U0BRG
U0TB
UART0 Transmit/Receive Control Register 0
UART0 Transmit/Receive Control Register 1
UART0 Receive Buffer Register
U0C0
U0C1
U0RB
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Register
UART2 Transmit Buffer Register
U2MR
U2BRG
U2TB
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
U2C0
U2C1
U2RB
UART2 Digital Filter Function Select Register
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
UART2 Special Mode Register 5
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 16 of 53
Mar 17, 2008
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Address
Register
00C0h
A/D Register 0
00C1h
00C2h
A/D Register 1
00C3h
00C4h
A/D Register 2
00C5h
00C6h
A/D Register 3
00C7h
00C8h
A/D Register 4
00C9h
00CAh
A/D Register 5
00CBh
00CCh
A/D Register 6
00CDh
00CEh
A/D Register 7
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Mode Register
00D5h
A/D Input Select Register
00D6h
A/D Control Register 0
00D7h
A/D Control Register 1
00D8h
D/A Register 0
00D9h
D/A Register 1
00DAh
00DBh
00DCh
D/A Control Register
00DDh
00DEh
00DFh
00E0h
Port P0 Register
00E1h
Port P1 Register
00E2h
Port P0 Direction Register
00E3h
Port P1 Direction Register
00E4h
Port P2 Register
00E5h
Port P3 Register
00E6h
Port P2 Direction Register
00E7h
Port P3 Direction Register
00E8h
Port P4 Register
00E9h
00EAh
Port P4 Direction Register
00EBh
00ECh
00EDh
00EEh
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 17 of 53
Mar 17, 2008
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
After Reset
XXXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
ADMOD
ADINSEL
ADCON0
ADCON1
DA0
DA1
00h
11000000b
00h
00h
00h
00h
DACON
00h
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
PD4
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.5
Address
0100h
0101h
0102h
0103h
0104h
0105h
0106h
0107h
0108h
0109h
010Ah
010Bh
010Ch
010Dh
010Eh
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
0119h
011Ah
011Bh
011Ch
011Dh
011Eh
011Fh
0120h
0121h
0122h
0123h
0124h
0125h
0126h
0127h
0128h
0129h
012Ah
012Bh
012Ch
012Dh
012Eh
012Fh
0130h
0131h
0132h
0133h
0134h
0135h
0136h
0137h
0138h
0139h
013Ah
013Bh
013Ch
013Dh
013Eh
013Fh
Note:
1.
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Timer RA Control Register
Timer RA I/O Control Register
Timer RA Mode Register
Timer RA Prescaler Register
Timer RA Register
LIN Control Register 2
LIN Control Register
LIN Status Register
Timer RB Control Register
Timer RB One-Shot Control Register
Timer RB I/O Control Register
Timer RB Mode Register
Timer RB Prescaler Register
Timer RB Secondary Register
Timer RB Primary Register
Register
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
Timer RE Second Data Register / Counter Data Register
Timer RE Minute Data Register / Compare Data Register
Timer RE Hour Data Register
Timer RE Day of Week Data Register
Timer RE Control Register 1
Timer RE Control Register 2
Timer RE Count Source Select Register
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
Timer RC Mode Register
Timer RC Control Register 1
Timer RC Interrupt Enable Register
Timer RC Status Register
Timer RC I/O Control Register 0
Timer RC I/O Control Register 1
Timer RC Counter
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
Timer RC General Register A
TRCGRA
Timer RC General Register B
TRCGRB
Timer RC General Register C
TRCGRC
Timer RC General Register D
TRCGRD
Timer RC Control Register 2
Timer RC Digital Filter Function Select Register
Timer RC Output Master Enable Register
Timer RC Trigger Control Register
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 18 of 53
Mar 17, 2008
After Reset
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
Register
0140h
0141h
0142h
0143h
0144h
0145h
0146h
0147h
0148h
0149h
014Ah
014Bh
014Ch
014Dh
014Eh
014Fh
0150h
0151h
0152h
0153h
0154h
0155h
0156h
0157h
0158h
0159h
015Ah
015Bh
015Ch
015Dh
015Eh
015Fh
0160h
UART1 Transmit/Receive Mode Register
0161h
UART1 Bit Rate Register
0162h
UART1 Transmit Buffer Register
0163h
0164h
UART1 Transmit/Receive Control Register 0
0165h
UART1 Transmit/Receive Control Register 1
0166h
UART1 Receive Buffer Register
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 19 of 53
Mar 17, 2008
Symbol
U1MR
U1BRG
U1TB
U1C0
U1C1
U1RB
After Reset
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
Register
0180h
Timer RA Pin Select Register
0181h
Timer RB/RC Pin Select Register
0182h
Timer RC Pin Select Register 0
0183h
Timer RC Pin Select Register 1
0184h
0185h
0186h
0187h
0188h
UART0 Pin Select Register
0189h
UART1 Pin Select Register
018Ah
UART2 Pin Select Register 0
018Bh
UART2 Pin Select Register 1
018Ch
SSU/IIC Pin Select Register
018Dh
018Eh
INT Interrupt Input Pin Select Register
018Fh
0190h
0191h
0192h
0193h
SS Bit Counter Register
0194h
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
0195h
SS Transmit Data Register H
0196h
SS Receive Data Register L / IIC bus Receive Data Register (2)
0197h
SS Receive Data Register H (2)
0198h
SS Control Register H / IIC bus Control Register 1 (2)
0199h
SS Control Register L / IIC bus Control Register 2 (2)
019Ah
SS Mode Register / IIC bus Mode Register (2)
019Bh
SS Enable Register / IIC bus Interrupt Enable Register (2)
019Ch
SS Status Register / IIC bus Status Register (2)
019Dh
SS Mode Register 2 / Slave Address Register (2)
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
Flash Memory Status Register
01B3h
01B4h
Flash Memory Control Register 0
01B5h
Flash Memory Control Register 1
01B6h
Flash Memory Control Register 2
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
REJ03B0228-0010 Rev.0.10
Page 20 of 53
Mar 17, 2008
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
00h
00h
00h
00h
After Reset
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
00h
00h
00h
00h
00h
INTSR
00h
SSBR
SSTDR / ICDRT
SSTDRH
SSRDR / ICDRR
SSRDRH
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00011000b
00h
00h / 0000X000b
00h
FST
10000X00b
FMR0
FMR1
FMR2
00h
00h
00h
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
Register
01C0h
Address Match Interrupt Register 0
01C1h
01C2h
01C3h
Address Match Interrupt Enable Register 0
01C4h
Address Match Interrupt Register 1
01C5h
01C6h
01C7h
Address Match Interrupt Enable Register 1
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
Pull-Up Control Register 0
01E1h
Pull-Up Control Register 1
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
Port P1 Drive Capacity Control Register
01F1h
Port P2 Drive Capacity Control Register
01F2h
Drive Capacity Control Register 0
01F3h
Drive Capacity Control Register 1
01F4h
01F5h
Input Threshold Control Register 0
01F6h
Input Threshold Control Register 1
01F7h
01F8h
Comparator B Control Register 0
01F9h
01FAh
External Input Enable Register 0
01FBh
01FCh
INT Input Filter Select Register 0
01FDh
01FEh
Key Input Enable Register 0
01FFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 21 of 53
Mar 17, 2008
Symbol
RMAD0
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
PUR0
PUR1
00h
00h
P1DRR
P2DRR
DRR0
DRR1
00h
00h
00h
00h
VLT0
VLT1
00h
00h
INTCMP
00h
INTEN
00h
INTF
00h
KIEN
00h
AIER0
RMAD1
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
Register
2C00h
DTC Transfer Vector Area
2C01h
DTC Transfer Vector Area
2C02h
DTC Transfer Vector Area
2C03h
DTC Transfer Vector Area
2C04h
DTC Transfer Vector Area
2C05h
DTC Transfer Vector Area
2C06h
DTC Transfer Vector Area
2C07h
DTC Transfer Vector Area
2C08h
DTC Transfer Vector Area
2C09h
DTC Transfer Vector Area
2C0Ah
DTC Transfer Vector Area
:
DTC Transfer Vector Area
:
DTC Transfer Vector Area
2C3Ah
DTC Transfer Vector Area
2C3Bh
DTC Transfer Vector Area
2C3Ch
DTC Transfer Vector Area
2C3Dh
DTC Transfer Vector Area
2C3Eh
DTC Transfer Vector Area
2C3Fh
DTC Transfer Vector Area
2C40h
DTC Control Data 0
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
DTC Control Data 1
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
DTC Control Data 2
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
DTC Control Data 3
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
DTC Control Data 4
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
DTC Control Data 5
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 22 of 53
Mar 17, 2008
Symbol
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
Address
Register
2C70h
DTC Control Data 6
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
DTC Control Data 7
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
DTC Control Data 8
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
DTC Control Data 9
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
DTC Control Data 10
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
DTC Control Data 11
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
DTC Control Data 12
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
DTC Control Data 13
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 23 of 53
Mar 17, 2008
Symbol
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
Register
2CB0h
DTC Control Data 14
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
DTC Control Data 15
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
DTC Control Data 16
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
DTC Control Data 17
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
DTC Control Data 18
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
DTC Control Data 19
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
DTC Control Data 20
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
DTC Control Data 21
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
REJ03B0228-0010 Rev.0.10
Page 24 of 53
Mar 17, 2008
Symbol
DTCD14
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 4.12
Address
2CF0h
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
2D01h
4. Special Function Registers (SFRs)
SFR Information (12) (1)
DTC Control Data 22
Register
Symbol
DTCD22
DTC Control Data 23
DTCD23
FFDBh
Option Function Select Register 2
:
FFFFh
Option Function Select Register
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. This register cannot be changed by a program. Use a flash programmer to write to it.
REJ03B0228-0010 Rev.0.10
Page 25 of 53
Mar 17, 2008
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
OFS2
(Note 2)
OFS
(Note 2)
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Condition
VCC/AVCC Supply voltage
VI
VO
Input voltage
Output voltage
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_2, P3_1, P3_3 to P3_5,
P3_7, P4_5 to P4_7,
MODE, RESET
Rated Value
Unit
−0.3 to 6.5
V
−0.3 to VCC + 0.3
V
XIN, XOUT
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XIN, XOUT
XIN-XOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
XCIN
XCIN-XCOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XCIN
XCIN-XCOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
−0.3 to VCC + 0.3
V
P0_0 to P0_7, P1_0 to P1_7,
P2_0 to P2_2, P3_1, P3_3 to P3_5,
P3_7, P4_5 to P4_7
XOUT
XIN-XOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XOUT
XIN-XOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
XCOUT
XCIN-XCOUT oscillation on
(oscillation buffer ON) (1)
−0.3 to 1.65
V
XCOUT
XCIN-XCOUT oscillation off
(oscillation buffer OFF) (1)
−0.3 to VCC + 0.3
V
Pd
Power dissipation
Topr
Operating ambient temperature
Topr = 25°C
Tstg
Storage temperature
TBD
mW
−20 to 85 (N version) /
−40 to 85 (D version)
°C
−65 to 150
°C
Note:
1. For the register settings for each operation, refer to 7. I/O Ports and 9. Clock Generation Circuit of Hardware Manual
(REJ09B0455).
REJ03B0228-0010 Rev.0.10
Page 26 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
VCC/AVCC Supply voltage
1.8
−
5.5
VSS/AVSS Supply voltage
−
0
−
V
CMOS Input level selection 4.0 V ≤ VCC ≤ 5.5 V
input
: 0.35 VCC
2.7 V ≤ VCC < 4.0 V
0.45 VCC
−
VCC
V
0.55 VCC
−
VCC
V
1.8 V ≤ VCC < 2.7 V
0.65 VCC
−
VCC
V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.5 VCC
2.7 V ≤ VCC < 4.0 V
0.6 VCC
−
VCC
V
0.7 VCC
−
VCC
V
1.8 V ≤ VCC < 2.7 V
0.8 VCC
−
VCC
V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.7 VCC
2.7 V ≤ VCC < 4.0 V
0.85 VCC
−
VCC
V
0.85 VCC
−
VCC
V
1.8 V ≤ VCC < 2.7 V
0.85 VCC
−
VCC
V
CMOS Input level selection 4.0 V ≤ VCC ≤ 5.5 V
input
: 0.35 VCC
2.7 V ≤ VCC < 4.0 V
0
−
0.2 VCC
V
0
−
0.2 VCC
V
1.8 V ≤ VCC < 2.7 V
0
−
0.2 VCC
V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.5 VCC
2.7 V ≤ VCC < 4.0 V
0
−
0.4 VCC
V
0
−
0.3 VCC
V
1.8 V ≤ VCC < 2.7 V
0
−
0.2 VCC
V
Input level selection 4.0 V ≤ VCC ≤ 5.5 V
: 0.7 VCC
2.7 V ≤ VCC < 4.0 V
0
−
0.55 VCC
V
0
−
0.45 VCC
V
1.8 V ≤ VCC < 2.7 V
0
−
0.35 VCC
V
VIH
VIL
Input “H” voltage Input level
switching
function
(I/O port)
Input “L” voltage Input level
switching
function
(I/O port)
V
IOH(sum)
Peak sum output Sum of all pins IOH(peak)
−
−
TBD
mA
IOH(sum)
Average sum
Sum of all pins IOH(avg)
−
−
TBD
mA
IOH(peak)
Peak output “H”
current
Drive capacity Low
−
−
−10
mA
Drive capacity High
−
−
−40
mA
IOH(avg)
Average output
“H” current
Drive capacity Low
−
−
−5
mA
−
−
−20
mA
IOL(sum)
Peak sum output Sum of all pins IOL(peak)
−
−
TBD
mA
IOL(sum)
Average sum
Sum of all pins IOL(avg)
−
−
TBD
mA
IOL(peak)
Peak output “L”
current
Drive capacity Low
−
−
10
mA
Drive capacity High
−
−
40
mA
IOL(avg)
Average output
“L” current
Drive capacity Low
−
−
5
mA
f(XIN)
XIN clock input oscillation frequency
Drive capacity High
−
20
mA
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
1.8 V ≤ VCC < 2.2 V
0
−
2
MHz
1.8 V ≤ VCC ≤ 5.5 V
−
32.768
50
kHz
When used as the count source for timer RC fOCO40M = 40MHz
2.7
−
5.5
V
When used as the count source for fOCO-F fOCO40M = 40MHz
1.8
−
5.5
V
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
f(XCIN)
XCIN clock input oscillation frequency
−
fOCO40M
operating
fOCO-F
−
3.0 V ≤ VCC ≤ 5.5 V
Drive capacity High
fOCO-F frequency
−
fOCO-S operating voltage
fOCO-S = 125kHz
1.8
−
5.5
V
−
System clock frequency
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
1.8 V ≤ VCC < 2.2 V
0
−
2
MHz
3.0 V ≤ VCC ≤ 5.5 V
0
−
20
MHz
2.7 V ≤ VCC < 3.0 V
0
−
10
MHz
2.2 V ≤ VCC < 2.7 V
0
−
5
MHz
1.8 V ≤ VCC < 2.2 V
0
−
2
MHz
f(BCLK)
CPU clock frequency
Notes:
1. VCC = 1.8 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
REJ03B0228-0010 Rev.0.10
Page 27 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
Figure 5.1
Ports P0 to P4 Timing Measurement Circuit
REJ03B0228-0010 Rev.0.10
Page 28 of 53
Mar 17, 2008
30pF
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.3
5. Electrical Characteristics
A/D Converter Characteristics (1)
Symbol
Parameter
−
Resolution
INL
Integral non-linearity error
Conditions
8-bit mode
−
Absolute accuracy
10-bit mode
8-bit mode
Typ.
Max.
Unit
−
−
10
Bit
Vref = AVCC = 5.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±3
LSB
Vref = AVCC = 3.3V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 3.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 2.2V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 5.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 3.3V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 3.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 2.2V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 5.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±3
LSB
Vref = AVCC = 3.3V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 3.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 2.2V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 5.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 3.3V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 3.0V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 2.2V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC
10-bit mode
Standard
Min.
−
Tolerance level impedance
−
3
−
kΩ
DNL
Differential non-linearity error
−
−
±1
LSB
−
Offset error
−
−
±3
LSB
−
Gain error
−
−
±3
LSB
RLADDER
Ladder resistance
Vref = AVCC
10
−
40
kΩ
tCONV
Conversion time
10-bit mode
Vref = AVCC = 5.0V,
φAD = 20 MHz
2.0
−
−
µs
8-bit mode
Vref = AVCC = 5.0V,
φAD = 20 MHz
2.0
−
−
µs
tSAMP
Sampling time
0.60
−
−
µs
Vref
Reference voltage
2.2
−
AVCC
V
VIA
Analog input voltage (3)
0
−
Vref
V
1.24
1.34
1.44
V
OCVREF On-chip reference voltage
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise
specified.
2. Set φAD frequency as follows:
When AVCC = 4.0 to 5.5 V, 2 MHz ≤ φAD ≤ 20 MHz
When AVCC = 3.2 to 4.0 V, 2 MHz ≤ φAD ≤ 16 MHz
When AVCC = 3.0 to 3.2 V, 2 MHz ≤ φAD ≤ 10 MHz
When AVCC = 2.2 to 3.0 V, 2 MHz ≤ φAD ≤ 5 MHz
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
REJ03B0228-0010 Rev.0.10
Page 29 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.4
5. Electrical Characteristics
D/A Converter Characteristics (1)
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
−
Resolution
−
−
8
Bit
−
Absolute accuracy
−
−
2.5
LSB
tsu
Setup time
−
−
3
µs
RO
Output resistor
−
6
−
kΩ
IVref
Reference power input current
−
−
1.5
mA
(NOTE 2)
Notes:
1. VCC/AVCC = Vref = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included. Also, even if the VCUT bit in the ADCON1 register is set to 0 (VREF
not connected), IVref flows into the D/A converters.
Table 5.5
Comparator A Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
LVREF
External reference voltage input range
1.4
−
VCC
V
LVCMP1,
LVCMP2
External comparison voltage input range
−0.3
−
VCC + 0.3
V
−
Offset
−
TBD
TBD
mV
−
Comparator output delay time (2)
−
TBD
TBD
µs
−
Comparator operating current
−
TBD
TBD
µA
VCC = 5.0 V
Note:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is not selected.
Table 5.6
Comparator B Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
0
−
VCC − 1.4
−0.3
−
VCC + 0.3
V
−
TBD
TBD
mV
V
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
−
Offset
td
Comparator output delay time (2)
VI = Vref ± 10 mV
−
TBD
TBD
µs
ICMP
Comparator operating current
VCC = 5.0 V
−
TBD
TBD
µA
Note:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is not selected.
REJ03B0228-0010 Rev.0.10
Page 30 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.7
5. Electrical Characteristics
Flash Memory (Program ROM) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
1,000 (3)
−
−
times
Byte program time
−
80
TBD
µs
−
Block erase time
−
0.3
TBD
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
5+CPU clock
× 3 cycles
ms
−
Interval from erase start/restart until
following suspend request (8)
0
−
−
µs
−
Time from suspend until erase restart
−
−
30+CPU clock
× 1 cycle
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
1.8
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time (7)
20
−
−
year
−
Program/erase endurance (2)
−
Ambient temperature = 55°C
Notes:
1. VCC = 2.7 to 5.5 V at Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
8. The erase sequence does not proceed unless the interval of 20 ms or more is allowed from when an erase operation
starts/restarts until the following suspend is requested.
REJ03B0228-0010 Rev.0.10
Page 31 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.8
5. Electrical Characteristics
Flash Memory (Data flash Block A to Block D) Electrical Characteristics (4)
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
10,000 (3)
−
−
times
Byte program time
(program/erase endurance ≤ 1,000 times)
−
160
TBD
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
300
−
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
1
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
1
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
5+CPU clock
× 3 cycles
ms
−
Interval from erase start/restart until
following suspend request (10)
0
−
−
µs
−
Time from suspend until erase restart
−
−
30+CPU clock
× 1 cycle
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
1.8
−
5.5
V
−
Program, erase temperature
−20 (8)
−
85
°C
−
Data hold time (9)
20
−
−
year
−
Program/erase endurance (2)
−
Ambient temperature = 55 °C
Notes:
1. VCC = 2.7 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 100 or 10,000), each block can be erased n times. For example, if 1,024
1-byte writes are performed to block A, a 1 Kbyte block, and then the block is erased, the programming/erasure endurance
still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. Standard of block A to block D when program and erase endurance exceeds 1,000 times. Byte program time to 1,000 times
is the same as that in program ROM.
5. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erase count of each block and limit the
number of erase operations to a certain number.
6. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
7. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
8. −40°C for D version.
9. The data hold time includes time that the power supply is off or the clock is not supplied.
10. The erase sequence does not proceed unless the interval of 3 ms or more is allowed from when an erase operation
starts/restarts until the following suspend is requested.
Suspend request
(FMR21 bit)
FST6 bit
Fixed time
Clock-dependent
time
td(SR-SUS)
FST6: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
REJ03B0228-0010 Rev.0.10
Page 32 of 53
Mar 17, 2008
Access restart
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.9
5. Electrical Characteristics
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Vdet0
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet0_0 (2)
At the falling of VCC
1.80
1.90
2.00
V
Voltage detection level Vdet0_1 (2)
At the falling of VCC
2.20
2.35
2.50
V
Voltage detection level Vdet0_2
(2)
At the falling of VCC
2.70
2.85
3.00
V
Voltage detection level Vdet0_3
(2)
At the falling of VCC
3.65
3.80
3.95
V
−
TBD
−
µA
−
−
TBD
µs
2.2
−
−
V
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts (3)
Vccmin
MCU operating voltage minimum value
VCA25 = 1, VCC = 5.0 V
Notes:
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
Table 5.10
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Vdet1
Parameter
Typ.
Max.
Unit
At the falling of VCC
2.05
2.20
2.35
V
(2)
At the falling of VCC
2.20
2.35
2.50
V
Voltage detection level Vdet1_2 (2)
At the falling of VCC
2.35
2.50
2.65
V
Voltage detection level Vdet1_3 (2)
At the falling of VCC
2.50
2.65
2.80
V
Voltage detection level Vdet1_4 (2)
At the falling of VCC
2.65
2.80
2.95
V
Voltage detection level Vdet1_5
(2)
At the falling of VCC
2.80
2.95
3.10
V
Voltage detection level Vdet1_6
(2)
At the falling of VCC
2.90
3.10
3.30
V
Voltage detection level Vdet1_7 (2)
At the falling of VCC
3.05
3.25
3.45
V
Voltage detection level Vdet1_8 (2)
At the falling of VCC
3.20
3.40
3.60
V
Voltage detection level Vdet1_9
(2)
At the falling of VCC
3.35
3.55
3.75
V
Voltage detection level Vdet1_A
(2)
At the falling of VCC
3.50
3.70
3.90
V
Voltage detection level Vdet1_B (2)
At the falling of VCC
3.65
3.85
4.05
V
Voltage detection level Vdet1_C (2)
At the falling of VCC
3.80
4.00
4.20
V
Voltage detection level Vdet1_D
(2)
At the falling of VCC
3.95
4.15
4.35
V
Voltage detection level Vdet1_E
(2)
At the falling of VCC
4.10
4.30
4.50
V
Voltage detection level Vdet1_F (2)
At the falling of VCC
4.25
4.45
4.65
V
−
40
−
µs
−
TBD
−
µA
−
−
TBD
µs
Voltage monitor 1 interrupt request generation time (3)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
Notes:
1.
2.
3.
4.
Standard
Min.
Voltage detection level Vdet1_0 (2)
Voltage detection level Vdet1_1
−
Condition
VCA26 = 1, VCC = 5.0 V
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
REJ03B0228-0010 Rev.0.10
Page 33 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.11
5. Electrical Characteristics
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Vdet2
Parameter
Min.
Typ.
Unit
Max.
Voltage detection level Vdet2_0 (2)
At the falling of VCC
3.80
4.00
4.20
V
Voltage detection level Vdet2_EXT (2)
At the falling of LVCMP2
1.24
1.34
1.44
V
−
40
−
µs
−
TBD
−
µA
−
−
TBD
µs
−
Voltage monitor 2 interrupt request generation time (3)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
Notes:
1.
2.
3.
4.
Standard
Condition
VCA27 = 1, VCC = 5.0 V
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.12
Power-on Reset Circuit, Voltage Monitor 0 Reset Electrical Characteristics(3)
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
Vpor1
Power-on reset valid voltage (4)
−
−
1.0
V
Vpor2
Power-on reset or voltage monitor 0 reset valid
voltage
0
−
Vdet0
V
trth
External power VCC rise gradient (2)
20
−
−
mV/msec
Notes:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This condition (external power VCC rise gradient) does not apply if VCC ≥ 1.0 V.
3. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVD0ON bit in the OFS register to 0, the
VW0C0 and VW0C6 bits in the VW0C register to 1 respectively, and the VCA25 bit in the VCA2 register to 1.
4. tw(por1) indicates the duration the external power VCC must be held below the effective voltage (Vpor1) to enable a power on
reset. When turning on the power for the first time, maintain tw(por1) for 1 ms or more.
Vdet0 (3)
Vdet0 (3)
1.8V
trth
trth
External
Power VCC
Vpor2
Vpor1
Sampling time (1, 2)
tw(por1)
Internal
reset signal
(“L” valid)
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. When using the voltage monitor 0 digital filter, ensure that the voltage is within the MCU operation voltage
range (1.8 V or above) during the sampling time.
2. The sampling clock can be selected. Refer to 6. Voltage Detection Circuit of Hardware Manual
(REJ09B0455) for details.
3. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit of Hardware Manual (REJ09B0455) for details.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
REJ03B0228-0010 Rev.0.10
Page 34 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.13
5. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
fOCO40M
Parameter
Condition
Standard
Unit
Min.
Typ.
Max.
TBD (3)
40
TBD (3)
MHz
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into
the FRA1 register and the FRA5 register
correction value into the FRA3 register (4)
TBD (3)
36.864
TBD (3)
MHz
High-speed on-chip oscillator frequency when
the FRA6 register correction value is written into
the FRA1 register and the FRA7 register
correction value into the FRA3 register
TBD (3)
32
TBD (3)
MHz
VCC = 2.7 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 2.7 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 2.2 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 2.2 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
TBD
−
TBD
%
High-speed on-chip oscillator frequency after
reset
High-speed on-chip oscillator frequency
temperature • supply voltage dependence (2)
VCC = 5.0 V, Topr = 25°C
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
TBD
TBD
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
TBD
−
µA
Notes:
1.
2.
3.
4.
VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
This indicates the precision error for the frequency set to fOCO40M.
These values are not guaranteed.
This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.14
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
60
125
250
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
10
100
kHz
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
1
−
µA
Note:
1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 5.15
Power Supply Circuit Timing Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
td(P-R)
Time for internal power supply stabilization during
power-on(2)
−
−
TBD
µs
td(R-S)
STOP exit time(3)
−
−
TBD
µs
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
3. Time until system clock supply starts after the interrupt is acknowledged to exit stop mode.
REJ03B0228-0010 Rev.0.10
Page 35 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.16
Symbol
5. Electrical Characteristics
Timing Requirements of Clock Synchronous Serial I/O with Chip Select (1)
Parameter
Conditions
Standard
Min.
Typ.
Unit
Max.
tSUCYC
SSCK clock cycle time
4
−
−
tCYC (2)
tHI
SSCK clock “H” width
0.4
−
0.6
tSUCYC
tLO
SSCK clock “L” width
0.4
−
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
−
−
1
tCYC (2)
Slave
−
−
1
µs
tFALL
SSCK clock falling
time
Master
−
−
1
tCYC (2)
−
−
1
µs
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC (2)
tLEAD
Slave
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
tSA
SSI slave access time
tOR
SSI slave out open time
−
−
1
tCYC (2)
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
REJ03B0228-0010 Rev.0.10
Page 36 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIH or VOH
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Master)
REJ03B0228-0010 Rev.0.10
Page 37 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIH or VOH
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Slave)
REJ03B0228-0010 Rev.0.10
Page 38 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIH or VOH
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Clock Synchronous Serial I/O with Chip Select (Clock Synchronous
Communication Mode)
REJ03B0228-0010 Rev.0.10
Page 39 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.17
5. Electrical Characteristics
Timing Requirements of I2C bus Interface (1)
Symbol
Parameter
Condition
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
tSCLL
SCL input “L” width
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
Standard
Typ.
(2)
−
12tCYC + 600
(2)
−
3tCYC + 300
Min.
Max.
−
Unit
−
ns
ns
5tCYC + 500 (2)
−
−
−
−
ns
−
300
−
SDA input bus-free time
5tCYC (2)
−
1tCYC (2)
−
ns
ns
tSTAH
Start condition input hold time
3tCYC (2)
−
−
ns
tSTAS
Retransmit start condition input setup time
3tCYC (2)
−
−
ns
tSTOP
Stop condition input setup time
3tCYC (2)
−
−
ns
tSDAS
Data input setup time
−
−
ns
tSDAH
Data input hold time
1tCYC + 20 (2)
0
−
−
ns
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
REJ03B0228-0010 Rev.0.10
Page 40 of 53
Mar 17, 2008
P(2)
tSDAS
tSDAH
ns
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.18
5. Electrical Characteristics
Electrical Characteristics (1) [VCC = 5 V]
Symbol
Parameter
VOH
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0, RXD1,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
RESET
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
Input “H” current
Input “L” current
Pull-up resistance
Feedback
XIN
resistance
Feedback
XCIN
resistance
RAM hold voltage
VI = 5 V
VI = 0 V
VI = 0 V
During stop mode
IOH = −20 mA
IOH = −5 mA
IOL = 20 mA
IOL = 5 mA
Standard
Min.
Typ.
VCC − 2.0
−
VCC − 2.0
−
−
−
−
−
0.1
0.5
Max.
VCC
VCC
2.0
2.0
−
Unit
V
V
V
V
V
−
V
−
5.0
µA
−
−5.0
30
−
50
1.0
167
−
µA
kΩ
MΩ
−
18
−
MΩ
1.8
−
−
V
0.1
1.0
−
−
Note:
1. VCC = 4.2 to 5.5 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
REJ03B0228-0010 Rev.0.10
Page 41 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.19
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [Vcc = 5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
High-speed
current
clock mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
Wait mode
Stop mode
REJ03B0228-0010 Rev.0.10
Page 42 of 53
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR27 = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Mar 17, 2008
Min.
−
Standard
Typ.
Max.
6.5
20
Unit
mA
−
5.3
16
mA
−
3.5
−
mA
−
2.5
−
mA
−
2.1
−
mA
−
1.5
−
mA
−
6.5
TBD
mA
−
2.5
−
mA
−
50
400
µA
−
60
400
µA
−
30
−
µA
−
15
TBD
µA
−
4
TBD
µA
−
3.5
−
µA
−
2.0
TBD
µA
−
5.0
−
µA
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C) [VCC = 5 V]
Table 5.20
XIN Input, XCIN Input
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
−
24
−
24
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 5 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.8
Table 5.21
XIN Input and XCIN Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
REJ03B0228-0010 Rev.0.10
Page 43 of 53
Mar 17, 2008
Unit
ns
ns
ns
VCC = 5 V
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.22
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
200
−
100
−
100
−
−
50
0
−
50
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.10
Table 5.23
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)
INT0 input “H” width, KIi input “H” width
Standard
Min.
Max.
−
250 (1)
INT0 input “L” width, KIi input “L” width
250 (2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.11
tW(INH)
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 5 V
REJ03B0228-0010 Rev.0.10
Page 44 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.24
5. Electrical Characteristics
Electrical Characteristics (3) [VCC = 3 V]
Symbol
Parameter
VOH
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
RESET
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance XIN
Feedback resistance XCIN
RAM hold voltage
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0,
RXD1, CLK0, CLK1,
CLK2, SSI, SCL,
SDA, SSO
VI = 3 V
VI = 0 V
VI = 0 V
During stop mode
IOH = −5 mA
IOH = −1 mA
IOL = 5 mA
IOL = 1 mA
Standard
Min.
Typ.
VCC − 0.5
−
VCC − 0.5
−
−
−
−
−
0.1
0.3
Max.
VCC
VCC
0.5
0.5
−
Unit
V
V
V
V
V
0.1
0.4
−
V
−
−
µA
−
66
−
−
1.8
−
160
3.0
18
−
4.0
−4.0
500
−
−
−
µA
kΩ
MΩ
MΩ
V
Note:
1. VCC =2.7 to 3.3 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
REJ03B0228-0010 Rev.0.10
Page 45 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.25
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [Vcc = 3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
REJ03B0228-0010 Rev.0.10
Page 46 of 53
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR27 = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral
clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Mar 17, 2008
Min.
−
Standard
Typ.
Max.
3.5
−
Unit
mA
−
1.5
−
mA
−
5.5
TBD
mA
−
1.5
−
mA
−
50
400
µA
−
60
400
µA
−
30
−
µA
−
15
TBD
µA
−
4
TBD
µA
−
3.5
−
µA
−
2.0
TBD
µA
−
5.0
−
µA
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C) [VCC = 3 V]
XIN Input, XCIN Input
Table 5.26
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
100
−
40
−
40
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 3 V
tWH(XIN)
XIN input
tWL(XIN)
XIN Input and XCIN Input Timing Diagram when VCC = 3 V
Figure 5.12
Table 5.27
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
300
−
120
−
120
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
REJ03B0228-0010 Rev.0.10
Page 47 of 53
Mar 17, 2008
Unit
ns
ns
ns
VCC = 3 V
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.28
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
300
−
150
−
150
−
−
80
0
−
70
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 3 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.14
Table 5.29
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)
INT0 input “H” width, KIi input “H” width
Standard
Min.
Max.
−
380 (1)
INT0 input “L” width, KIi input “L” width
380 (2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
−
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.15
tW(INH)
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 3 V
REJ03B0228-0010 Rev.0.10
Page 48 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.30
5. Electrical Characteristics
Electrical Characteristics (5) [VCC = 2.2 V]
Symbol
Parameter
VOH
Output “H” voltage
VOL
Output “L” voltage
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
RESET
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance XIN
Feedback resistance XCIN
RAM hold voltage
Condition
Drive capacity High
Drive capacity Low
Drive capacity High
Drive capacity Low
INT0, INT1, INT3,
KI0, KI1, KI2, KI3,
TRAIO, RXD0,
RXD1, CLK0, CLK1,
CLK2, SSI, SCL,
SDA, SSO
VI = 1.8 V
VI = 0 V
VI = 0 V
During stop mode
IOH = −2 mA
IOH = −1 mA
IOL = 2 mA
IOL = 1 mA
Standard
Min.
Typ.
VCC − 0.5
−
VCC − 0.5
−
−
−
−
−
0.05
0.3
Max.
VCC
VCC
0.5
0.5
−
Mar 17, 2008
V
V
V
V
V
0.05
0.15
−
V
−
−
µA
−
100
−
−
1.8
−
200
5
35
−
4.0
−4.0
600
−
−
−
Note:
1. VCC = 1.8 V at Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
REJ03B0228-0010 Rev.0.10
Page 49 of 53
Unit
µA
kΩ
MΩ
MΩ
V
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.31
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (6) [Vcc = 2.2 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 1.8 to 2.7 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
REJ03B0228-0010 Rev.0.10
Page 50 of 53
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 5 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
on-chip
Low-speed on-chip oscillator on = 125 kHz
oscillator
No division
mode
XIN clock off
High-speed on-chip oscillator on fOCO = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
Low-speed on- XIN clock off
chip oscillator High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
mode
Divide-by-8, FMR27 = 1, VCA20 = 1
Low-speed
XIN clock off
High-speed on-chip oscillator off
clock mode
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
FMR27 = 1, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 1
Wait mode
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral
clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop mode
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Mar 17, 2008
Min.
−
Standard
Typ.
Max.
2.2
−
Unit
mA
−
0.8
−
mA
−
4
−
mA
−
1.7
−
mA
−
50
300
µA
−
60
350
µA
−
30
−
µA
−
15
TBD
µA
−
4
TBD
µA
−
3.5
−
µA
−
2.0
TBD
µA
−
5.0
−
µA
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
5. Electrical Characteristics
Timing requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C) [VCC = 2.2 V]
XIN Input, XCIN Input
Table 5.32
Symbol
tc(XIN)
tWH(XIN)
tWL(XIN)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
200
−
90
−
90
−
14
−
7
−
7
−
Parameter
XIN input cycle time
XIN input “H” width
XIN input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 2.2 V
tWH(XIN)
XIN input
tWL(XIN)
Figure 5.16
XIN Input and XCIN Input Timing Diagram when VCC = 2.2 V
Table 5.33
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
500
−
200
−
200
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
REJ03B0228-0010 Rev.0.10
Page 51 of 53
Mar 17, 2008
Unit
ns
ns
ns
VCC = 2.2 V
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Table 5.34
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
Standard
Min.
Max.
800
−
400
−
400
−
−
200
0
−
150
−
90
−
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
Unit
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.18
Table 5.35
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0, 1, 3) Input, Key Input Interrupt KIi (i = 0 to 3)
INT0 input “H” width, KIi input “H” width
Standard
Min.
Max.
−
1000 (1)
INT0 input “L” width, KIi input “L” width
1000 (2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
INTi input
(i = 0, 1, 3)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.19
tW(INH)
Input Timing for External Interrupt INTi and Key Input Interrupt KIi when Vcc = 2.2 V
REJ03B0228-0010 Rev.0.10
Page 52 of 53
Mar 17, 2008
Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
R8C/33A Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Technology website.
JEITA Package Code
P-LQFP32-7x7-0.80
RENESAS Code
PLQP0032GB-A
Previous Code
32P6U-A
MASS[Typ.]
0.2g
HD
*1
D
24
17
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
16
25
bp
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
9
1
ZE
Terminal cross section
32
8
ZD
c
A
A1
F
A2
Index mark
L
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
L1
y
e
REJ03B0228-0010 Rev.0.10
Page 53 of 53
*3
Detail F
bp
x
Mar 17, 2008
e
x
y
ZD
ZE
L
L1
Min Nom Max
6.9 7.0 7.1
6.9 7.0 7.1
1.4
8.8 9.0 9.2
8.8 9.0 9.2
1.7
0.1 0.2
0
0.32 0.37 0.42
0.35
0.09 0.145 0.20
0.125
0°
8°
0.8
0.20
0.10
0.7
0.7
0.3 0.5 0.7
1.0
REVISION HISTORY
REVISION HISTORY
R8C/33A Group Datasheet
R8C/33A Group Datasheet
Description
Rev.
Date
0.01
Oct 26, 2007
−
First Edition issued
0.02
Feb 05, 2008
2
Table 1.1 Interrupts: Specification “• Number of interrupt vectors: 44” →
“• Number of interrupt vectors: 69”
3
Table 1.2 Serial Interface: Specification revised, Note1 deleted
6
Figure 1.3 revised
7
Table 1.4 revised
8
Table 1.5 XIN clock input, XIN clock output: revised
Note2 added
13
Figure 3.1 “Expanded area” deleted, Note1 revised
7
Table 1.4 I/O Pin Functions for Peripheral Modules: “Voltage Detection
Circuit” added
9
Table 1.6 Voltage Detection Circuit added
13
Figure 3.1 revised
15
Table 4.2 revised
16
Table 4.3 008Ch: deleted
20
Table 4.7 0186h, 018Fh: deleted
26
5. Electrical Characteristics added
0.10
Mar 17, 2008
Page
Summary
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