RENESAS R8C35M

Preliminary Datasheet
Specifications in this document are tentative and subject to change.
R8C/35M Group
RENESAS MCU
1.
R01DS0021EJ0020
Rev.0.20
Feb 15, 2011
Overview
1.1
Features
The R8C/35M Group of single-chip MCUs incorporates the R8C CPU core, employing sophisticated instructions
for a high level of efficiency. With 1 Mbyte of address space, and it is capable of executing instructions at high
speed. In addition, the CPU core boasts a multiplier for high-speed operation processing.
Power consumption is low, and the supported operating modes allow additional power control. These MCUs are
designed to maximize EMI/EMS performance.
Integration of many peripheral functions, including multifunction timer and serial interface, reduces the number of
system components.
The R8C/35M Group has data flash (1 KB × 4 blocks) with the background operation (BGO) function.
1.1.1
Applications
Electronic household appliances, office equipment, audio equipment, consumer equipment, etc.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 1 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
1.1.2
1. Overview
Specifications
Tables 1.1 and 1.2 outline the Specifications for R8C/35M Group.
Table 1.1
Item
CPU
Specifications for R8C/35M Group (1)
Function
Central processing
unit
Memory
ROM, RAM, Data
flash
Power Supply Voltage detection
Voltage
circuit
Detection
I/O Ports
Programmable I/O
ports
Clock
Clock generation
circuits
Interrupts
Watchdog Timer
DTC (Data Transfer Controller)
Timer
Timer RA
Timer RB
Timer RC
Timer RD
Timer RE
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Specification
R8C CPU core
• Number of fundamental instructions: 89
• Minimum instruction execution time:
50 ns (f(XIN) = 20 MHz, VCC = 2.7 to 5.5 V)
200 ns (f(XIN) = 5 MHz, VCC = 1.8 to 5.5 V)
• Multiplier: 16 bits × 16 bits → 32 bits
• Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits → 32 bits
• Operation mode: Single-chip mode (address space: 1 Mbyte)
Refer to Table 1.3 Product List for R8C/35M Group.
• Power-on reset
• Voltage detection 3 (detection level of voltage detection 0 and voltage
detection 1 selectable)
• Input-only: 1 pin
• CMOS I/O ports: 47, selectable pull-up resistor
• High current drive ports: 47
4 circuits: XIN clock oscillation circuit,
XCIN clock oscillation circuit (32 kHz),
High-speed on-chip oscillator (with frequency adjustment function),
Low-speed on-chip oscillator
• Oscillation stop detection: XIN clock oscillation stop detection function
• Frequency divider circuit: Dividing selectable 1, 2, 4, 8, and 16
• Low power consumption modes:
Standard operating mode (high-speed clock, low-speed clock, high-speed
on-chip oscillator, low-speed on-chip oscillator), wait mode, stop mode
Real-time clock (timer RE)
• Number of interrupt vectors: 69
• External Interrupt: 9 (INT × 5, Key input × 4)
• Priority levels: 7 levels
• 14 bits × 1 (with prescaler)
• Reset start selectable
• Low-speed on-chip oscillator for watchdog timer selectable
• 1 channel
• Activation sources: 33
• Transfer modes: 2 (normal mode, repeat mode)
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), pulse output mode (output level inverted every
period), event counter mode, pulse width measurement mode, pulse period
measurement mode
8 bits × 1 (with 8-bit prescaler)
Timer mode (period timer), programmable waveform generation mode (PWM
output), programmable one-shot generation mode, programmable wait oneshot generation mode
16 bits × 1 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 3 pins), PWM2 mode (PWM output pin)
16 bits × 2 (with 4 capture/compare registers)
Timer mode (input capture function, output compare function), PWM mode
(output 6 pins), reset synchronous PWM mode (output three-phase
waveforms (6 pins), sawtooth wave modulation), complementary PWM mode
(output three-phase waveforms (6 pins), triangular wave modulation), PWM3
mode (PWM output 2 pins with fixed period)
8 bits × 1
Real-time clock mode (count seconds, minutes, hours, days of week), output
compare mode
Page 2 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 1.2
Item
Serial
Interface
1. Overview
Specifications for R8C/35M Group (2)
Function
UART0, UART1
UART2
Synchronous Serial
Communication Unit (SSU)
I2C bus
LIN Module
A/D Converter
D/A Converter
Comparator A
Comparator B
Flash Memory
Operating Frequency/Supply
Voltage
Current consumption
Operating Ambient Temperature
Package
Specification
Clock synchronous serial I/O/UART × 2 channel
Clock synchronous serial I/O/UART, I2C mode (I2C-bus), multiprocessor
communication function
1 (shared with I2C-bus)
1 (shared with SSU)
Hardware LIN: 1 (timer RA, UART0)
10-bit resolution × 12 channels, includes sample and hold function, with sweep
mode
8-bit resolution × 2 circuits
• 2 circuits (shared with voltage monitor 1 and voltage monitor 2)
• External reference voltage input available
2 circuits
• Programming and erasure voltage: VCC = 2.7 to 5.5 V
• Programming and erasure endurance: 10,000 times (data flash)
1,000 times (program ROM)
• Program security: ROM code protect, ID code check
• Debug functions: On-chip debug, on-board flash rewrite function
• Background operation (BGO) function
f(XIN) = 20 MHz (VCC = 2.7 to 5.5 V)
f(XIN) = 5 MHz (VCC = 1.8 to 5.5 V)
Typ. 6.5 mA (VCC = 5.0 V, f(XIN) = 20 MHz)
Typ. 3.5 mA (VCC = 3.0 V, f(XIN) = 10 MHz)
Typ. 3.5 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz))
Typ. 2.0 µA (VCC = 3.0 V, stop mode)
-20 to 85°C (N version)
-40 to 85°C (D version) (1)
52-pin LQFP
Package code: PLQP0052JA-A (previous code: 52P6A-A)
Note:
1. Specify the D version if D version functions are to be used.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 3 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
1.2
1. Overview
Product List
Table 1.3 lists Product List for R8C/35M Group, and Figure 1.1 shows a Part Number, Memory Size, and Package
of R8C/35M Group.
Table 1.3
Product List for R8C/35M Group
Part No.
R5F21354MNFP (D)
R5F21355MNFP (D)
R5F21356MNFP (D)
R5F21357MNFP (P)
R5F21358MNFP (P)
R5F2135AMNFP (P)
R5F2135CMNFP (P)
R5F21354MDFP (D)
R5F21355MDFP (D)
R5F21356MDFP (D)
R5F21357MDFP (P)
R5F21358MDFP (P)
R5F2135AMDFP (P)
R5F2135CMDFP (P)
Current of Feb 2011
ROM Capacity
Program ROM
Data flash
16 Kbytes
1 Kbyte × 4
24 Kbytes
1 Kbyte × 4
32 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
16 Kbytes
1 Kbyte × 4
24 Kbytes
1 Kbyte × 4
32 Kbytes
1 Kbyte × 4
48 Kbytes
1 Kbyte × 4
64 Kbytes
1 Kbyte × 4
96 Kbytes
1 Kbyte × 4
128 Kbytes
1 Kbyte × 4
RAM
Capacity
1.5 Kbytes
2 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
1.5 Kbytes
2 Kbytes
2.5 Kbytes
4 Kbytes
6 Kbytes
8 Kbytes
10 Kbytes
Package Type
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
PLQP0052JA-A
Remarks
N version
D version
(D): Under development
(P): Under planning
Part No.
R 5 F 21 35 6 M N FP
Package type:
FP: PLQP0052JA-A (0.65 mm pin-pitch, 10 mm square body)
Classification
N: Operating ambient temperature -20°C to 85°C
D: Operating ambient temperature -40°C to 85°C
ROM capacity
4: 16 KB
5: 24 KB
6: 32 KB
7: 48 KB
8: 64 KB
A: 96 KB
C: 128 KB
R8C/35M Group
R8C/3x Series
Memory type
F: Flash memory
Renesas MCU
Renesas semiconductor
Figure 1.1
Part Number, Memory Size, and Package of R8C/35M Group
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 4 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
1.3
1. Overview
Block Diagram
Figure 1.2 shows a Block Diagram.
I/O ports
8
8
8
8
Port P0
Port P1
Port P2
Port P3
5
1
2
8
Port P4
Port P5
Port P6
Peripheral functions
Timers
UART or
clock synchronous serial I/O
(8 bits × 3)
Timer RA (8 bits × 1)
Timer RB (8 bits × 1)
Timer RC (16 bits × 1)
Timer RD (16 bits × 2)
Timer RE (8 bits × 1)
I2C bus or SSU
(8 bits × 1)
System clock generation
circuit
XIN-XOUT
High-speed on-chip oscillator
Low-speed on-chip oscillator
XCIN-XCOUT
LIN module
Watchdog timer
(14 bits)
Low-speed on-chip oscillator
for watchdog timer
Comparator A
Voltage detection circuit
A/D converter
(10 bits × 12 channels)
Comparator B
DTC
D/A converter
(8 bits × 2)
Memory
R8C CPU core
R0H
R1H
R0L
R1L
R2
R3
SB
ISP
INTB
A0
A1
FB
ROM (1)
USP
RAM (2)
PC
FLG
Multiplier
Notes:
1. ROM size varies with MCU type.
2. RAM size varies with MCU type.
Figure 1.2
Block Diagram
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 5 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
1.4
1. Overview
Pin Assignment
P4_5/ADTRG/INT0(/RXD2/SCL2)
P6_5/INT4(/CLK1/CLK2/TRCIOB)
P6_6/INT2(/TXD2/SDA2/TRCIOC)
P6_7(/INT3/TRCIOD)
P0_7/AN0/DA1(/TRCIOC)
P1_0/AN8/LVCMP1/KI0(/TRCIOD)
P1_1/AN9/LVCMP2/KI1(/TRCIOA/TRCTRG)
P1_2/AN10/LVREF/Kl2(/TRCIOB)
P1_3/AN11/LVCOUT1/Kl3/TRBO(/TRCIOC)
P1_4(/TXD0/TRCCLK)
P1_5(/INT1/RXD0/TRAIO)
P1_6/LVCOUT2/IVREF1(/CLK0)
P1_7/IVCMP1/INT1(/TRAIO)
Figure 1.3 shows the Pin Assignment (Top View). Tables 1.4 and 1.5 outline the Pin Name Information by Pin
Number.
39 38 37 36 35 34 33 32 31 30 29 28 27
P0_6/AN1/DA0(/TRCIOD)
P0_5/AN2(/TRCIOB)
P0_4/AN3/TREO(/TRCIOB)
P0_3/AN4(/CLK1/TRCIOB)
P0_2/AN5(/RXD1/TRCIOA/TRCTRG)
P0_1/AN6(/TXD1/TRCIOA/TRCTRG)
P0_0/AN7(/TRCIOA/TRCTRG)
P6_4(/RXD1)
P6_3(/TXD1)
P6_2(/CLK1)
P6_1
P6_0(/TREO)
P5_7
40
26
41
25
42
24
43
23
44
22
21
45
R8C/35M Group
46
20
19
47
18
48
PLQP0052JA-A(52P6A-A)
(top view)
49
50
17
16
51
15
52
14
2
3
4
5
6
7
8
9
10 11 12 13
P5_6(/TRAO)
P3_2(/INT1/INT2/TRAIO)
P3_0(/TRAO)
P4_2/VREF
MODE
P4_3(/XCIN)
P4_4(/XCOUT)
RESET
P4_7/XOUT
VSS/AVSS
P4_6/XIN
VCC/AVCC
P3_7/SDA/SSO/TRAO(/RXD2/SCL2/TXD2/SDA2)
1
P3_1(/TRBO)
P3_6(/INT1)
P2_0(/INT1/TRCIOB/TRDIOA0/TRDCLK)
P2_1(/TRCIOC/TRDIOC0)
P2_2(/TRCIOD/TRDIOB0)
P2_3(/TRDIOD0)
P2_4(/TRDIOA1)
P2_5(/TRDIOB1)
P2_6(/TRDIOC1)
P2_7(/TRDIOD1)
P3_3/IVCMP3/INT3/SCS(/CTS2/RTS2/TRCCLK)
P3_4/IVREF3/SSI(/RXD2/SCL2/TXD2/SDA2/TRCIOC)
P3_5/SCL/SSCK(/CLK2/TRCIOD)
Notes:
1. Can be assigned to the pin in parentheses by a program.
2. Confirm the pin 1 position on the package by referring to the package dimensions.
Figure 1.3
Pin Assignment (Top View)
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 6 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 1.4
1. Overview
Pin Name Information by Pin Number (1)
I/O Pin Functions for Peripheral Modules
Pin
Number
Control Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
Port
Interrupt
P5_6
P3_2 (INT1/INT2)
P3_0
P4_2
MODE
(XCIN)
(XCOUT)
RESET
XOUT
VSS/AVSS
XIN
VCC/AVCC
Serial
Interface
Timer
SSU
I2C
bus
A/D Converter,
D/A Converter,
Comparator A,
Comparator B
(TRAO)
(TRAIO)
(TRAO)
VREF
P4_3
P4_4
P4_7
P4_6
P3_7
TRAO
14
15
P3_5
P3_4
(TRCIOD)
(TRCIOC)
16
P3_3
17
18
19
20
21
22
P2_7
P2_6
P2_5
P2_4
P2_3
P2_2
23
P2_1
24
P2_0
(INT1)
25
P3_6
(INT1)
26
27
P3_1
P6_7
(INT3)
(TRBO)
(TRCIOD)
28
P6_6
INT2
(TRCIOC)
(TXD2/SDA2)
29
P6_5
INT4
(TRCIOB)
(CLK1/CLK2)
30
P4_5
INT0
31
P1_7
32
33
P1_6
P1_5
34
35
P1_4
P1_3
INT3
(TRCCLK)
(RXD2/SCL2/ SSO SDA
TXD2/SDA2)
(CLK2)
SSCK SCL
(RXD2/SCL2/ SSI
TXD2/SDA2)
(CTS2/RTS2)
SCS
IVREF3
IVCMP3
(TRDIOD1)
(TRDIOC1)
(TRDIOB1)
(TRDIOA1)
(TRDIOD0)
(TRCIOD/
TRDIOB0)
(TRCIOC/
TRDIOC0)
(TRCIOB/
TRDIOA0/
TRDCLK)
INT1
(TRAIO)
(INT1)
(TRAIO)
KI3
(TRCCLK)
TRBO
(/TRCIOC)
(RXD2/SCL2)
ADTRG
IVCMP1
(CLK0)
(RXD0)
LVCOUT2/IVREF1
(TXD0)
AN11/LVCOUT1
Note:
1. Can be assigned to the pin in parentheses by a program.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 7 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 1.5
1. Overview
Pin Name Information by Pin Number (2)
I/O Pin Functions for Peripheral Modules
Pin
Number
Control Pin
Port
Interrupt
Timer
Serial
Interface
SSU
I2C
bus
A/D Converter,
D/A Converter,
Comparator A,
Comparator B
AN10/LVREF
36
P1_2
KI2
(TRCIOB)
37
P1_1
KI1
AN9/LVCMP2
38
P1_0
KI0
(TRCIOA/
TRCTRG)
(TRCIOD)
39
40
41
P0_7
P0_6
P0_5
AN0/DA1
AN1/DA0
AN2
42
P0_4
43
P0_3
44
P0_2
45
P0_1
46
P0_0
(TRCIOC)
(TRCIOD)
(TRCIOB)
TREO
(/TRCIOB)
(TRCIOB)
(TRCIOA/
TRCTRG)
(TRCIOA/
TRCTRG)
(TRCIOA/
TRCTRG)
47
48
49
50
51
52
P6_4
P6_3
P6_2
P6_1
P6_0
P5_7
AN8/LVCMP1
AN3
(CLK1)
AN4
(RXD1)
AN5
(TXD1)
AN6
AN7
(RXD1)
(TXD1)
(CLK1)
(TREO)
Note:
1. Can be assigned to the pin in parentheses by a program.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 8 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
1.5
1. Overview
Pin Functions
Tables 1.6 and 1.7 list Pin Functions.
Table 1.6
Pin Functions (1)
I/O Type
Description
Power supply input
Item
VCC, VSS
Pin Name
−
Apply 1.8 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.
Analog power
supply input
AVCC, AVSS
−
Power supply for the A/D converter.
Connect a capacitor between AVCC and AVSS.
Reset input
RESET
I
Input “L” on this pin resets the MCU.
MODE
MODE
I
Connect this pin to VCC via a resistor.
XIN clock input
XIN
I
XIN clock output
XOUT
I/O
These pins are provided for XIN clock generation circuit I/O.
Connect a ceramic resonator or a crystal oscillator between
the XIN and XOUT pins (1). To use an external clock, input it
to the XOUT pin and leave the XIN pin open.
XCIN clock input
XCIN
I
XCIN clock output
XCOUT
O
INT interrupt input
INT0 to INT4
I
INT interrupt input pins.
INT0 is timer RB, RC and RD input pin.
Key input interrupt
KI0 to KI3
I
Key input interrupt input pins
Timer RA
TRAIO
I/O
These pins are provided for XCIN clock generation circuit I/O.
Connect a crystal oscillator between the XCIN and XCOUT
pins (1). To use an external clock, input it to the XCIN pin and
leave the XCOUT pin open.
Timer RA I/O pin
TRAO
O
Timer RA output pin
Timer RB
TRBO
O
Timer RB output pin
Timer RC
TRCCLK
I
External clock input pin
TRCTRG
I
External trigger input pin
TRCIOA, TRCIOB,
TRCIOC, TRCIOD
I/O
Timer RC I/O pins
Timer RD
TRDIOA0, TRDIOA1,
TRDIOB0, TRDIOB1,
TRDIOC0, TRDIOC1,
TRDIOD0, TRDIOD1
I/O
Timer RD I/O pins
TRDCLK
I
External clock input pin
Timer RE
TREO
O
Divided clock output pin
Serial interface
CLK0, CLK1, CLK2
I/O
RXD0, RXD1, RXD2
I
Serial data input pins
TXD0, TXD1, TXD2
O
Serial data output pins
CTS2
I
Transmission control input pin
RTS2
O
Reception control output pin
SCL2
I/O
I2C mode clock I/O pin
SDA2
I/O
I2C mode data I/O pin
I2C bus
SSU
Transfer clock I/O pins
SCL
I/O
Clock I/O pin
SDA
I/O
Data I/O pin
SSI
I/O
Data I/O pin
SCS
I/O
Chip-select signal I/O pin
SSCK
I/O
Clock I/O pin
SSO
I/O
Data I/O pin
I: Input
O: Output
I/O: Input and output
Note:
1. Refer to the oscillator manufacturer for oscillation characteristics.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 9 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
1. Overview
Table 1.7
Pin Functions (2)
I/O Type
Description
Reference voltage
input
Item
VREF
Pin Name
I
Reference voltage input pin to A/D converter and D/A
converter
A/D converter
AN0 to AN11
I
Analog input pins to A/D converter
ADTRG
I
A/D external trigger input pin
D/A converter
DA0, DA1
O
D/A converter output pins
Comparator A
LVCMP1, LVCMP2
I
Comparator A analog voltage input pins
LVREF
I
Comparator A reference voltage input pin
LVCOUT1, LVCOUT2
O
Comparator A output pins
IVCMP1, IVCMP3
I
Comparator B analog voltage input pins
IVREF1, IVREF3
I
Comparator B reference voltage input pins
Comparator B
I/O port
P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_3 to P4_7,
P5_6, P5_7,
P6_0 to P6_7
Input port
P4_2
I: Input
O: Output
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
I/O
I
CMOS I/O ports. Each port has an I/O select direction
register, allowing each pin in the port to be directed for input
or output individually.
Any port set to input can be set to use a pull-up resistor or not
by a program.
All ports can be used as LED drive ports.
Input-only port
I/O: Input and output
Page 10 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
2.
2. Central Processing Unit (CPU)
Central Processing Unit (CPU)
Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a
register bank. There are two sets of register bank.
b31
b15
R2
R3
b8b7
b0
R0H (high-order of R0) R0L (low-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
Data registers (1)
R2
R3
A0
A1
FB
b19
b15
Address registers (1)
Frame base register (1)
b0
Interrupt table register
INTBL
INTBH
The 4 high order bits of INTB are INTBH and
the 16 low order bits of INTB are INTBL.
b19
b0
Program counter
PC
b15
b0
USP
User stack pointer
ISP
Interrupt stack pointer
SB
Static base register
b15
b0
FLG
b15
b8
IPL
b7
Flag register
b0
U I O B S Z D C
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit
Note:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1
CPU Registers
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 11 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
2.1
2. Central Processing Unit (CPU)
Data Registers (R0, R1, R2, and R3)
R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split
into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are
analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is
analogous to R2R0.
2.2
Address Registers (A0 and A1)
A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also
used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32bit address register (A1A0).
2.3
Frame Base Register (FB)
FB is a 16-bit register for FB relative addressing.
2.4
Interrupt Table Register (INTB)
INTB is a 20-bit register that indicates the starting address of an interrupt vector table.
2.5
Program Counter (PC)
PC is 20 bits wide and indicates the address of the next instruction to be executed.
2.6
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
The stack pointers (SP), USP and ISP, are each 16 bits wide. The U flag of FLG is used to switch between
USP and ISP.
2.7
Static Base Register (SB)
SB is a 16-bit register for SB relative addressing.
2.8
Flag Register (FLG)
FLG is an 11-bit register indicating the CPU state.
2.8.1
Carry Flag (C)
The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.
2.8.2
Debug Flag (D)
The D flag is for debugging only. Set it to 0.
2.8.3
Zero Flag (Z)
The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.
2.8.4
Sign Flag (S)
The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.
2.8.5
Register Bank Select Flag (B)
Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.
2.8.6
Overflow Flag (O)
The O flag is set to 1 when an operation results in an overflow; otherwise to 0.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 12 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
2.8.7
2. Central Processing Unit (CPU)
Interrupt Enable Flag (I)
The I flag enables maskable interrupts.
Interrupts are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0
when an interrupt request is acknowledged.
2.8.8
Stack Pointer Select Flag (U)
ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.
The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software
interrupt numbers 0 to 31 is executed.
2.8.9
Processor Interrupt Priority Level (IPL)
IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has higher priority than IPL, the interrupt is enabled.
2.8.10
Reserved Bit
If necessary, set to 0. When read, the content is undefined.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 13 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
3.
3. Memory
Memory
3.1
R8C/35M Group
Figure 3.1 is a Memory Map of R8C/35M Group. The R8C/35M Group has a 1-Mbyte address space from
addresses 00000h to FFFFFh. For example, a 32-Kbyte internal ROM area is allocated addresses 08000h to
0FFFFh.
The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. The starting address of each interrupt
routine is stored here.
The internal ROM (data flash) is allocated addresses 03000h to 03FFFh.
The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2.5-Kbyte internal
RAM area is allocated addresses 00400h to 00DFFh. The internal RAM is used not only for data storage but also as
a stack area when a subroutine is called or when an interrupt request is acknowledged.
Special function registers (SFRs) are allocated addresses 00000h to 002FFh and 02C00h to 02FFFh. Peripheral
function control registers are allocated here. All unallocated spaces within the SFRs are reserved and cannot be
accessed by users.
00000h
002FFh
SFR
(Refer to 4. Special
Function Registers
(SFRs))
00400h
Internal RAM
0FFD8h
0XXXXh
02C00h
02FFFh
03000h
Reserved area
0FFDCh
SFR
(Refer to 4. Special Function
Registers (SFRs))
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Internal ROM
(data flash) (1)
03FFFh
0YYYYh
Watchdog timer, oscillation stop detection, voltage monitor
Address break
(Reserved)
Reset
Internal ROM
(program ROM)
0FFFFh
0FFFFh
Internal ROM
(program ROM)
ZZZZZh
FFFFFh
Notes:
1. Data flash indicates block A (1 Kbyte), block B (1 Kbyte), block C (1 Kbyte), and block D (1 Kbyte).
2. The blank areas are reserved and cannot be accessed by users.
Internal ROM
Part Number
Internal RAM
Size
Address 0YYYYh
Address ZZZZZh
Size
R5F21354MNFP, R5F21354MDFP
16 Kbytes
0C000h
−
1.5 Kbytes
009FFh
R5F21355MNFP, R5F21355MDFP
24 Kbytes
0A000h
−
2 Kbytes
00BFFh
R5F21356MNFP, R5F21356MDFP
32 Kbytes
08000h
−
2.5 Kbytes
00DFFh
R5F21357MNFP, R5F21357MDFP
48 Kbytes
04000h
−
4 Kbytes
013FFh
R5F21358MNFP, R5F21358MDFP
64 Kbytes
04000h
13FFFh
6 Kbytes
01BFFh
R5F2135AMNFP, R5F2135AMDFP
96 Kbytes
04000h
1BFFFh
8 Kbytes
023FFh
R5F2135CMNFP, R5F2135CMDFP
128 Kbytes
04000h
23FFFh
10 Kbytes
02BFFh
Figure 3.1
Address 0XXXXh
Memory Map of R8C/35M Group
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 14 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
4.
4. Special Function Registers (SFRs)
Special Function Registers (SFRs)
An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.12 list the special
function registers and Table 4.13 lists the ID Code Areas and Option Function Select Area.
Table 4.1
Address
0000h
0001h
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h
000Ah
000Bh
000Ch
000Dh
000Eh
000Fh
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
0019h
001Ah
001Bh
001Ch
001Dh
001Eh
001Fh
0020h
0021h
0022h
0023h
0024h
0025h
0026h
0027h
0028h
0029h
002Ah
002Bh
002Ch
002Dh
002Eh
002Fh
0030h
0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
SFR Information (1) (1)
Register
Symbol
After Reset
Processor Mode Register 0
Processor Mode Register 1
System Clock Control Register 0
System Clock Control Register 1
Module Standby Control Register
System Clock Control Register 3
Protect Register
Reset Source Determination Register
Oscillation Stop Detection Register
Watchdog Timer Reset Register
Watchdog Timer Start Register
Watchdog Timer Control Register
PM0
PM1
CM0
CM1
MSTCR
CM3
PRCR
RSTFR
OCD
WDTR
WDTS
WDTC
00h
00h
00101000b
00100000b
00h
00h
00h
0XXXXXXXb (2)
00000100b
XXh
XXh
00111111b
High-Speed On-Chip Oscillator Control Register 7
FRA7
When shipping
Count Source Protection Mode Register
CSPR
00h
10000000b (3)
High-Speed On-Chip Oscillator Control Register 0
High-Speed On-Chip Oscillator Control Register 1
High-Speed On-Chip Oscillator Control Register 2
On-Chip Reference Voltage Control Register
FRA0
FRA1
FRA2
OCVREFCR
00h
When shipping
00h
00h
Clock Prescaler Reset Flag
High-Speed On-Chip Oscillator Control Register 4
High-Speed On-Chip Oscillator Control Register 5
High-Speed On-Chip Oscillator Control Register 6
CPSRF
FRA4
FRA5
FRA6
00h
When Shipping
When Shipping
When Shipping
High-Speed On-Chip Oscillator Control Register 3
Voltage Monitor Circuit/Comparator A Control Register
Voltage Monitor Circuit Edge Select Register
FRA3
CMPA
VCAC
When shipping
00h
00h
Voltage Detect Register 1
Voltage Detect Register 2
VCA1
VCA2
00001000b
00h (4)
00100000b (5)
Voltage Detection 1 Level Select Register
VD1LS
00000111b
Voltage Monitor 0 Circuit Control Register
VW0C
1100X010b (4)
1100X011b (5)
10001010b
0039h
Voltage Monitor 1 Circuit Control Register
VW1C
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. The CWR bit in the RSTFR register is set to 0 after power-on and voltage monitor 0 reset. Hardware reset, software reset, or watchdog timer
reset does not affect this bit.
3. The CSPROINI bit in the OFS register is set to 0.
4. The LVDAS bit in the OFS register is set to 1.
5. The LVDAS bit in the OFS register is set to 0.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 15 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.2
4. Special Function Registers (SFRs)
SFR Information (2) (1)
Address
Register
003Ah
Voltage Monitor 2 Circuit Control Register
003Bh
003Ch
003Dh
003Eh
003Fh
0040h
0041h
Flash Memory Ready Interrupt Control Register
0042h
0043h
0044h
0045h
0046h
INT4 Interrupt Control Register
0047h
Timer RC Interrupt Control Register
0048h
Timer RD0 Interrupt Control Register
0049h
Timer RD1 Interrupt Control Register
004Ah
Timer RE Interrupt Control Register
004Bh
UART2 Transmit Interrupt Control Register
004Ch
UART2 Receive Interrupt Control Register
004Dh
Key Input Interrupt Control Register
004Eh
A/D Conversion Interrupt Control Register
004Fh
SSU Interrupt Control Register / IIC bus Interrupt Control Register (2)
0050h
0051h
UART0 Transmit Interrupt Control Register
0052h
UART0 Receive Interrupt Control Register
0053h
UART1 Transmit Interrupt Control Register
0054h
UART1 Receive Interrupt Control Register
0055h
INT2 Interrupt Control Register
0056h
Timer RA Interrupt Control Register
0057h
0058h
Timer RB Interrupt Control Register
0059h
INT1 Interrupt Control Register
005Ah
INT3 Interrupt Control Register
005Bh
005Ch
005Dh
INT0 Interrupt Control Register
005Eh
UART2 Bus Collision Detection Interrupt Control Register
005Fh
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
Voltage Monitor 1/Comparator A1 Interrupt Control Register
0073h
Voltage Monitor 2/Comparator A2 Interrupt Control Register
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
VW2C
Symbol
After Reset
10000010b
FMRDYIC
XXXXX000b
INT4IC
TRCIC
TRD0IC
TRD1IC
TREIC
S2TIC
S2RIC
KUPIC
ADIC
SSUIC / IICIC
XX00X000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
S0TIC
S0RIC
S1TIC
S1RIC
INT2IC
TRAIC
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XX00X000b
XXXXX000b
TRBIC
INT1IC
INT3IC
XXXXX000b
XX00X000b
XX00X000b
INT0IC
U2BCNIC
XX00X000b
XXXXX000b
VCMP1IC
VCMP2IC
XXXXX000b
XXXXX000b
Page 16 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.3
4. Special Function Registers (SFRs)
SFR Information (3) (1)
Address
Register
0080h
DTC Activation Control Register
0081h
0082h
0083h
0084h
0085h
0086h
0087h
0088h
DTC Activation Enable Register 0
0089h
DTC Activation Enable Register 1
008Ah
DTC Activation Enable Register 2
008Bh
DTC Activation Enable Register 3
008Ch
DTC Activation Enable Register 4
008Dh
DTC Activation Enable Register 5
008Eh
DTC Activation Enable Register 6
008Fh
0090h
0091h
0092h
0093h
0094h
0095h
0096h
0097h
0098h
0099h
009Ah
009Bh
009Ch
009Dh
009Eh
009Fh
00A0h
UART0 Transmit/Receive Mode Register
00A1h
UART0 Bit Rate Register
00A2h
UART0 Transmit Buffer Register
00A3h
00A4h
UART0 Transmit/Receive Control Register 0
00A5h
UART0 Transmit/Receive Control Register 1
00A6h
UART0 Receive Buffer Register
00A7h
00A8h
UART2 Transmit/Receive Mode Register
00A9h
UART2 Bit Rate Register
00AAh
UART2 Transmit Buffer Register
00ABh
00ACh
UART2 Transmit/Receive Control Register 0
00ADh
UART2 Transmit/Receive Control Register 1
00AEh
UART2 Receive Buffer Register
00AFh
00B0h
UART2 Digital Filter Function Select Register
00B1h
00B2h
00B3h
00B4h
00B5h
00B6h
00B7h
00B8h
00B9h
00BAh
00BBh
UART2 Special Mode Register 5
00BCh
UART2 Special Mode Register 4
00BDh
UART2 Special Mode Register 3
00BEh
UART2 Special Mode Register 2
00BFh
UART2 Special Mode Register
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
DTCTL
00h
DTCEN0
DTCEN1
DTCEN2
DTCEN3
DTCEN4
DTCEN5
DTCEN6
00h
00h
00h
00h
00h
00h
00h
U0MR
U0BRG
U0TB
URXDF
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
00h
U2SMR5
U2SMR4
U2SMR3
U2SMR2
U2SMR
00h
00h
000X0X0Xb
X0000000b
X0000000b
U0C0
U0C1
U0RB
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
After Reset
Page 17 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.4
4. Special Function Registers (SFRs)
SFR Information (4) (1)
Address
Register
00C0h
A/D Register 0
00C1h
00C2h
A/D Register 1
00C3h
00C4h
A/D Register 2
00C5h
00C6h
A/D Register 3
00C7h
00C8h
A/D Register 4
00C9h
00CAh
A/D Register 5
00CBh
00CCh
A/D Register 6
00CDh
00CEh
A/D Register 7
00CFh
00D0h
00D1h
00D2h
00D3h
00D4h
A/D Mode Register
00D5h
A/D Input Select Register
00D6h
A/D Control Register 0
00D7h
A/D Control Register 1
00D8h
D/A0 Register
00D9h
D/A1 Register
00DAh
00DBh
00DCh
D/A Control Register
00DDh
00DEh
00DFh
00E0h
Port P0 Register
00E1h
Port P1 Register
00E2h
Port P0 Direction Register
00E3h
Port P1 Direction Register
00E4h
Port P2 Register
00E5h
Port P3 Register
00E6h
Port P2 Direction Register
00E7h
Port P3 Direction Register
00E8h
Port P4 Register
00E9h
Port P5 Register
00EAh
Port P4 Direction Register
00EBh
Port P5 Direction Register
00ECh
Port P6 Register
00EDh
00EEh
Port P6 Direction Register
00EFh
00F0h
00F1h
00F2h
00F3h
00F4h
00F5h
00F6h
00F7h
00F8h
00F9h
00FAh
00FBh
00FCh
00FDh
00FEh
00FFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
After Reset
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
XXh
000000XXb
ADMOD
ADINSEL
ADCON0
ADCON1
DA0
DA1
00h
11000000b
00h
00h
00h
00h
DACON
00h
P0
P1
PD0
PD1
P2
P3
PD2
PD3
P4
P5
PD4
PD5
P6
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
XXh
00h
00h
XXh
PD6
00h
Page 18 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.5
4. Special Function Registers (SFRs)
SFR Information (5) (1)
Address
Register
0100h
Timer RA Control Register
0101h
Timer RA I/O Control Register
0102h
Timer RA Mode Register
0103h
Timer RA Prescaler Register
0104h
Timer RA Register
0105h
LIN Control Register 2
0106h
LIN Control Register
0107h
LIN Status Register
0108h
Timer RB Control Register
0109h
Timer RB One-Shot Control Register
010Ah
Timer RB I/O Control Register
010Bh
Timer RB Mode Register
010Ch
Timer RB Prescaler Register
010Dh
Timer RB Secondary Register
010Eh
Timer RB Primary Register
010Fh
0110h
0111h
0112h
0113h
0114h
0115h
0116h
0117h
0118h
Timer RE Second Data Register / Counter Data Register
0119h
Timer RE Minute Data Register / Compare Data Register
011Ah
Timer RE Hour Data Register
011Bh
Timer RE Day of Week Data Register
011Ch
Timer RE Control Register 1
011Dh
Timer RE Control Register 2
011Eh
Timer RE Count Source Select Register
011Fh
0120h
Timer RC Mode Register
0121h
Timer RC Control Register 1
0122h
Timer RC Interrupt Enable Register
0123h
Timer RC Status Register
0124h
Timer RC I/O Control Register 0
0125h
Timer RC I/O Control Register 1
0126h
Timer RC Counter
0127h
0128h
Timer RC General Register A
0129h
012Ah
Timer RC General Register B
012Bh
012Ch
Timer RC General Register C
012Dh
012Eh
Timer RC General Register D
012Fh
0130h
Timer RC Control Register 2
0131h
Timer RC Digital Filter Function Select Register
0132h
Timer RC Output Master Enable Register
0133h
Timer RC Trigger Control Register
0134h
0135h
Timer RD Control Expansion Register
0136h
Timer RD Trigger Control Register
0137h
Timer RD Start Register
0138h
Timer RD Mode Register
0139h
Timer RD PWM Mode Register
013Ah
Timer RD Function Control Register
013Bh
Timer RD Output Master Enable Register 1
013Ch
Timer RD Output Master Enable Register 2
013Dh
Timer RD Output Control Register
013Eh
Timer RD Digital Filter Function Select Register 0
013Fh
Timer RD Digital Filter Function Select Register 1
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
TRACR
TRAIOC
TRAMR
TRAPRE
TRA
LINCR2
LINCR
LINST
TRBCR
TRBOCR
TRBIOC
TRBMR
TRBPRE
TRBSC
TRBPR
00h
00h
00h
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
FFh
FFh
FFh
TRESEC
TREMIN
TREHR
TREWK
TRECR1
TRECR2
TRECSR
00h
00h
00h
00h
00h
00h
00001000b
TRCMR
TRCCR1
TRCIER
TRCSR
TRCIOR0
TRCIOR1
TRC
TRCCR2
TRCDF
TRCOER
TRCADCR
01001000b
00h
01110000b
01110000b
10001000b
10001000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00011000b
00h
01111111b
00h
TRDECR
TRDADCR
TRDSTR
TRDMR
TRDPMR
TRDFCR
TRDOER1
TRDOER2
TRDOCR
TRDDF0
TRDDF1
00h
00h
11111100b
00001110b
10001000b
10000000b
FFh
01111111b
00h
00h
00h
TRCGRA
TRCGRB
TRCGRC
TRCGRD
After Reset
Page 19 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.6
4. Special Function Registers (SFRs)
SFR Information (6) (1)
Address
Register
0140h
Timer RD Control Register 0
0141h
Timer RD I/O Control Register A0
0142h
Timer RD I/O Control Register C0
0143h
Timer RD Status Register 0
0144h
Timer RD Interrupt Enable Register 0
0145h
Timer RD PWM Mode Output Level Control Register 0
0146h
Timer RD Counter 0
0147h
0148h
Timer RD General Register A0
0149h
014Ah
Timer RD General Register B0
014Bh
014Ch
Timer RD General Register C0
014Dh
014Eh
Timer RD General Register D0
014Fh
0150h
Timer RD Control Register 1
0151h
Timer RD I/O Control Register A1
0152h
Timer RD I/O Control Register C1
0153h
Timer RD Status Register 1
0154h
Timer RD Interrupt Enable Register 1
0155h
Timer RD PWM Mode Output Level Control Register 1
0156h
Timer RD Counter 1
0157h
0158h
Timer RD General Register A1
0159h
015Ah
Timer RD General Register B1
015Bh
015Ch
Timer RD General Register C1
015Dh
015Eh
Timer RD General Register D1
015Fh
0160h
UART1 Transmit/Receive Mode Register
0161h
UART1 Bit Rate Register
0162h
UART1 Transmit Buffer Register
0163h
0164h
UART1 Transmit/Receive Control Register 0
0165h
UART1 Transmit/Receive Control Register 1
0166h
UART1 Receive Buffer Register
0167h
0168h
0169h
016Ah
016Bh
016Ch
016Dh
016Eh
016Fh
0170h
0171h
0172h
0173h
0174h
0175h
0176h
0177h
0178h
0179h
017Ah
017Bh
017Ch
017Dh
017Eh
017Fh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
TRDCR0
TRDIORA0
TRDIORC0
TRDSR0
TRDIER0
TRDPOCR0
TRD0
TRDGRA0
TRDGRB0
TRDGRC0
TRDGRD0
TRDCR1
TRDIORA1
TRDIORC1
TRDSR1
TRDIER1
TRDPOCR1
TRD1
TRDGRA1
TRDGRB1
TRDGRC1
TRDGRD1
U1MR
U1BRG
U1TB
U1C0
U1C1
U1RB
After Reset
00h
10001000b
10001000b
11100000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
10001000b
10001000b
11000000b
11100000b
11111000b
00h
00h
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
Page 20 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.7
4. Special Function Registers (SFRs)
SFR Information (7) (1)
Address
Register
0180h
Timer RA Pin Select Register
0181h
Timer RB/RC Pin Select Register
0182h
Timer RC Pin Select Register 0
0183h
Timer RC Pin Select Register 1
0184h
Timer RD Pin Select Register 0
0185h
Timer RD Pin Select Register 1
0186h
Timer Pin Select Register
0187h
0188h
UART0 Pin Select Register
0189h
UART1 Pin Select Register
018Ah
UART2 Pin Select Register 0
018Bh
UART2 Pin Select Register 1
018Ch
SSU/IIC Pin Select Register
018Dh
018Eh
INT Interrupt Input Pin Select Register
018Fh
I/O Function Pin Select Register
0190h
0191h
0192h
0193h
SS Bit Counter Register
0194h
SS Transmit Data Register L / IIC bus Transmit Data Register (2)
0195h
SS Transmit Data Register H (2)
0196h
SS Receive Data Register L / IIC bus Receive Data Register (2)
0197h
SS Receive Data Register H (2)
0198h
SS Control Register H / IIC bus Control Register 1 (2)
0199h
SS Control Register L / IIC bus Control Register 2 (2)
019Ah
SS Mode Register / IIC bus Mode Register (2)
019Bh
SS Enable Register / IIC bus Interrupt Enable Register (2)
019Ch
SS Status Register / IIC bus Status Register (2)
019Dh
SS Mode Register 2 / Slave Address Register (2)
019Eh
019Fh
01A0h
01A1h
01A2h
01A3h
01A4h
01A5h
01A6h
01A7h
01A8h
01A9h
01AAh
01ABh
01ACh
01ADh
01AEh
01AFh
01B0h
01B1h
01B2h
Flash Memory Status Register
01B3h
01B4h
Flash Memory Control Register 0
01B5h
Flash Memory Control Register 1
01B6h
Flash Memory Control Register 2
01B7h
01B8h
01B9h
01BAh
01BBh
01BCh
01BDh
01BEh
01BFh
X: Undefined
Notes:
1. The blank areas are reserved and cannot be accessed by users.
2. Selectable by the IICSEL bit in the SSUIICSR register.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
TRASR
TRBRCSR
TRCPSR0
TRCPSR1
TRDPSR0
TRDPSR1
TIMSR
00h
00h
00h
00h
00h
00h
00h
After Reset
U0SR
U1SR
U2SR0
U2SR1
SSUIICSR
00h
00h
00h
00h
00h
INTSR
PINSR
00h
00h
SSBR
SSTDR / ICDRT
SSTDRH
SSRDR / ICDRR
SSRDRH
SSCRH / ICCR1
SSCRL / ICCR2
SSMR / ICMR
SSER / ICIER
SSSR / ICSR
SSMR2 / SAR
11111000b
FFh
FFh
FFh
FFh
00h
01111101b
00010000b / 00011000b
00h
00h / 0000X000b
00h
FST
10000X00b
FMR0
FMR1
FMR2
00h
00h
00h
Page 21 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.8
4. Special Function Registers (SFRs)
SFR Information (8) (1)
Address
Register
01C0h
Address Match Interrupt Register 0
01C1h
01C2h
01C3h
Address Match Interrupt Enable Register 0
01C4h
Address Match Interrupt Register 1
01C5h
01C6h
01C7h
Address Match Interrupt Enable Register 1
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
Pull-Up Control Register 0
01E1h
Pull-Up Control Register 1
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
Port P1 Drive Capacity Control Register
01F1h
Port P2 Drive Capacity Control Register
01F2h
Drive Capacity Control Register 0
01F3h
Drive Capacity Control Register 1
01F4h
01F5h
Input Threshold Control Register 0
01F6h
Input Threshold Control Register 1
01F7h
01F8h
Comparator B Control Register 0
01F9h
01FAh
External Input Enable Register 0
01FBh
External Input Enable Register 1
01FCh
INT Input Filter Select Register 0
01FDh
INT Input Filter Select Register 1
01FEh
Key Input Enable Register 0
01FFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
RMAD0
AIER1
After Reset
XXh
XXh
0000XXXXb
00h
XXh
XXh
0000XXXXb
00h
PUR0
PUR1
00h
00h
P1DRR
P2DRR
DRR0
DRR1
00h
00h
00h
00h
VLT0
VLT1
00h
00h
INTCMP
00h
INTEN
INTEN1
INTF
INTF1
KIEN
00h
00h
00h
00h
00h
AIER0
RMAD1
Page 22 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.9
4. Special Function Registers (SFRs)
SFR Information (9) (1)
Address
Register
2C00h
DTC Transfer Vector Area
2C01h
DTC Transfer Vector Area
2C02h
DTC Transfer Vector Area
2C03h
DTC Transfer Vector Area
2C04h
DTC Transfer Vector Area
2C05h
DTC Transfer Vector Area
2C06h
DTC Transfer Vector Area
2C07h
DTC Transfer Vector Area
2C08h
DTC Transfer Vector Area
2C09h
DTC Transfer Vector Area
2C0Ah
DTC Transfer Vector Area
:
DTC Transfer Vector Area
:
DTC Transfer Vector Area
2C3Ah
DTC Transfer Vector Area
2C3Bh
DTC Transfer Vector Area
2C3Ch
DTC Transfer Vector Area
2C3Dh
DTC Transfer Vector Area
2C3Eh
DTC Transfer Vector Area
2C3Fh
DTC Transfer Vector Area
2C40h
DTC Control Data 0
2C41h
2C42h
2C43h
2C44h
2C45h
2C46h
2C47h
2C48h
DTC Control Data 1
2C49h
2C4Ah
2C4Bh
2C4Ch
2C4Dh
2C4Eh
2C4Fh
2C50h
DTC Control Data 2
2C51h
2C52h
2C53h
2C54h
2C55h
2C56h
2C57h
2C58h
DTC Control Data 3
2C59h
2C5Ah
2C5Bh
2C5Ch
2C5Dh
2C5Eh
2C5Fh
2C60h
DTC Control Data 4
2C61h
2C62h
2C63h
2C64h
2C65h
2C66h
2C67h
2C68h
DTC Control Data 5
2C69h
2C6Ah
2C6Bh
2C6Ch
2C6Dh
2C6Eh
2C6Fh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
DTCD0
DTCD1
DTCD2
DTCD3
DTCD4
DTCD5
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 23 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.10
4. Special Function Registers (SFRs)
SFR Information (10) (1)
Address
Register
2C70h
DTC Control Data 6
2C71h
2C72h
2C73h
2C74h
2C75h
2C76h
2C77h
2C78h
DTC Control Data 7
2C79h
2C7Ah
2C7Bh
2C7Ch
2C7Dh
2C7Eh
2C7Fh
2C80h
DTC Control Data 8
2C81h
2C82h
2C83h
2C84h
2C85h
2C86h
2C87h
2C88h
DTC Control Data 9
2C89h
2C8Ah
2C8Bh
2C8Ch
2C8Dh
2C8Eh
2C8Fh
2C90h
DTC Control Data 10
2C91h
2C92h
2C93h
2C94h
2C95h
2C96h
2C97h
2C98h
DTC Control Data 11
2C99h
2C9Ah
2C9Bh
2C9Ch
2C9Dh
2C9Eh
2C9Fh
2CA0h
DTC Control Data 12
2CA1h
2CA2h
2CA3h
2CA4h
2CA5h
2CA6h
2CA7h
2CA8h
DTC Control Data 13
2CA9h
2CAAh
2CABh
2CACh
2CADh
2CAEh
2CAFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
DTCD6
DTCD7
DTCD8
DTCD9
DTCD10
DTCD11
DTCD12
DTCD13
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 24 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 4.11
4. Special Function Registers (SFRs)
SFR Information (11) (1)
Address
Register
2CB0h
DTC Control Data 14
2CB1h
2CB2h
2CB3h
2CB4h
2CB5h
2CB6h
2CB7h
2CB8h
DTC Control Data 15
2CB9h
2CBAh
2CBBh
2CBCh
2CBDh
2CBEh
2CBFh
2CC0h
DTC Control Data 16
2CC1h
2CC2h
2CC3h
2CC4h
2CC5h
2CC6h
2CC7h
2CC8h
DTC Control Data 17
2CC9h
2CCAh
2CCBh
2CCCh
2CCDh
2CCEh
2CCFh
2CD0h
DTC Control Data 18
2CD1h
2CD2h
2CD3h
2CD4h
2CD5h
2CD6h
2CD7h
2CD8h
DTC Control Data 19
2CD9h
2CDAh
2CDBh
2CDCh
2CDDh
2CDEh
2CDFh
2CE0h
DTC Control Data 20
2CE1h
2CE2h
2CE3h
2CE4h
2CE5h
2CE6h
2CE7h
2CE8h
DTC Control Data 21
2CE9h
2CEAh
2CEBh
2CECh
2CEDh
2CEEh
2CEFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Symbol
DTCD14
DTCD15
DTCD16
DTCD17
DTCD18
DTCD19
DTCD20
DTCD21
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
Page 25 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
4. Special Function Registers (SFRs)
SFR Information (12) (1)
Table 4.12
Address
Register
2CF0h
DTC Control Data 22
2CF1h
2CF2h
2CF3h
2CF4h
2CF5h
2CF6h
2CF7h
2CF8h
DTC Control Data 23
2CF9h
2CFAh
2CFBh
2CFCh
2CFDh
2CFEh
2CFFh
2D00h
:
2FFFh
X: Undefined
Note:
1. The blank areas are reserved and cannot be accessed by users.
Table 4.13
ID Code Areas and Option Function Select Area
Address
:
FFDBh
:
FFDFh
:
FFE3h
:
FFEBh
:
FFEFh
:
FFF3h
:
FFF7h
:
FFFBh
:
FFFFh
Area Name
Notes:
1.
2.
Option Function Select Register 2
Symbol
DTCD22
DTCD23
Symbol
OFS2
After Reset
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
XXh
After Reset
(Note 1)
ID1
(Note 2)
ID2
(Note 2)
ID3
(Note 2)
ID4
(Note 2)
ID5
(Note 2)
ID6
(Note 2)
ID7
(Note 2)
Option Function Select Register
OFS
(Note 1)
The option function select area is allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the option function select area. If the block including the option function select area is erased, the option function select
area is set to FFh.
When blank products are shipped, the option function select area is set to FFh. It is set to the written value after written by the user.
When factory-programming products are shipped, the value of the option function select area is the value programmed by the user.
The ID code areas are allocated in the flash memory, not in the SFRs. Set appropriate values as ROM data by a program.
Do not write additions to the ID code areas. If the block including the ID code areas is erased, the ID code areas are set to FFh.
When blank products are shipped, the ID code areas are set to FFh. They are set to the written value after written by the user.
When factory-programming products are shipped, the value of the ID code areas is the value programmed by the user.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 26 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5.
5. Electrical Characteristics
Electrical Characteristics
Table 5.1
Absolute Maximum Ratings
Symbol
Parameter
Rated Value
Unit
−0.3 to 6.5
V
Input voltage
−0.3 to VCC + 0.3
V
VO
Output voltage
−0.3 to VCC + 0.3
V
Pd
Power dissipation
500
mW
Topr
Operating ambient temperature
−20 to 85 (N version) /
−40 to 85 (D version)
°C
Tstg
Storage temperature
−65 to 150
°C
VCC/AVCC
Supply voltage
VI
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Condition
−40°C ≤ Topr ≤ 85°C
Page 27 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.2
5. Electrical Characteristics
Recommended Operating Conditions
Symbol
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
VCC/AVCC Supply voltage
1.8
−
5.5
VSS/AVSS Supply voltage
−
0
−
V
0.8 VCC
−
VCC
V
VIH
Input “H” voltage
Other than CMOS input
CMOS Input level Input level selection
input
switching : 0.35 VCC
function
(I/O port)
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
4.0 V ≤ VCC ≤ 5.5 V
0.5 VCC
−
VCC
V
2.7 V ≤ VCC < 4.0 V 0.55 VCC
−
VCC
V
1.8 V ≤ VCC < 2.7 V 0.65 VCC
−
VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0.65 VCC
−
VCC
V
2.7 V ≤ VCC < 4.0 V
0.7 VCC
−
VCC
V
1.8 V ≤ VCC < 2.7 V
0.8 VCC
−
VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0.85 VCC
−
VCC
V
2.7 V ≤ VCC < 4.0 V 0.85 VCC
−
VCC
V
1.8 V ≤ VCC < 2.7 V 0.85 VCC
−
VCC
V
1.2
−
VCC
V
0
−
0.2 VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0
−
0.2 VCC
V
2.7 V ≤ VCC < 4.0 V
0
−
0.2 VCC
V
1.8 V ≤ VCC < 2.7 V
0
−
0.2 VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0
−
0.4 VCC
V
2.7 V ≤ VCC < 4.0 V
0
−
0.3 VCC
V
1.8 V ≤ VCC < 2.7 V
0
−
0.2 VCC
V
4.0 V ≤ VCC ≤ 5.5 V
0
−
0.55 VCC
V
2.7 V ≤ VCC < 4.0 V
0
−
0.45 VCC
V
1.8 V ≤ VCC < 2.7 V
0
−
0.35 VCC
V
0
−
0.4
V
External clock input (XOUT)
VIL
Input “L” voltage
Other than CMOS input
CMOS Input level Input level selection
input
switching : 0.35 VCC
function
(I/O port)
Input level selection
: 0.5 VCC
Input level selection
: 0.7 VCC
V
External clock input (XOUT)
IOH(sum)
Peak sum output “H” current Sum of all pins IOH(peak)
−
−
−160
mA
IOH(sum)
Average sum output “H” current Sum of all pins IOH(avg)
−
−
−80
mA
IOH(peak)
Peak output “H” current
Drive capacity Low
−
−
−10
mA
Drive capacity High
−
−
−40
mA
Drive capacity Low
−
−
−5
mA
mA
IOH(avg)
Average output “H” current
IOL(sum)
Peak sum output “L” current
IOL(sum)
IOL(peak)
Drive capacity High
−
−
−20
Sum of all pins IOL(peak)
−
−
160
mA
Average sum output “L” current Sum of all pins IOL(avg)
−
−
80
mA
Peak output “L” current
Drive capacity Low
−
−
10
mA
Drive capacity High
−
−
40
mA
Drive capacity Low
−
−
5
mA
IOL(avg)
Average output “L” current
f(XIN)
XIN clock input oscillation frequency
f(XCIN)
XCIN clock input oscillation frequency
Drive capacity High
fOCO40M When used as the count source for timer RC or timer RD (3)
fOCO-F
−
f(BCLK)
fOCO-F frequency
System clock frequency
CPU clock frequency
2.7 V ≤ VCC ≤ 5.5 V
−
−
20
mA
−
−
20
MHz
MHz
1.8 V ≤ VCC < 2.7 V
−
−
5
1.8 V ≤ VCC ≤ 5.5 V
TBD
32.768
50
kHz
2.7 V ≤ VCC ≤ 5.5 V
32
−
40
MHz
2.7 V ≤ VCC ≤ 5.5 V
−
−
20
MHz
1.8 V ≤ VCC < 2.7 V
−
−
5
MHz
2.7 V ≤ VCC ≤ 5.5 V
−
−
20
MHz
1.8 V ≤ VCC < 2.7 V
−
−
5
MHz
2.7 V ≤ VCC ≤ 5.5 V
−
−
20
MHz
1.8 V ≤ VCC < 2.7 V
−
−
5
MHz
Notes:
1. VCC = 1.8 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. The average output current indicates the average value of current measured during 100 ms.
3. fOCO40M can be used as the count source for timer RC or timer RD in the range of VCC = 2.7 V to 5.5V.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 28 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
P0
P1
P2
P3
P4
P5
P6
Figure 5.1
30pF
Ports P0 to P6 Timing Measurement Circuit
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 29 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.3
5. Electrical Characteristics
A/D Converter Characteristics
Symbol
Parameter
−
Resolution
−
Absolute accuracy
A/D conversion clock
−
Tolerance level impedance
tCONV
Conversion time
Min.
Max.
Unit
−
−
10
Bit
AN0 to AN7 input,
AN8 to AN11 input
−
−
±3
LSB
Vref = AVCC = 3.3 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 3.0 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 2.2 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±5
LSB
Vref = AVCC = 5.0 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 3.3 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 3.0 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
Vref = AVCC = 2.2 V
AN0 to AN7 input,
AN8 to AN11 input
−
−
±2
LSB
4.0 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
−
20
MHz
3.2 V ≤ Vref = AVCC ≤ 5.5 V
(2)
2
−
16
MHz
2.7 V ≤ Vref = AVCC ≤ 5.5 V
(2)
2
−
10
MHz
2.2 V ≤ Vref = AVCC ≤ 5.5 V (2)
2
−
5
MHz
−
3
−
kΩ
10-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
−
−
µs
8-bit mode
Vref = AVCC = 5.0 V, φAD = 20 MHz
2.2
−
−
µs
0.8
−
−
µs
−
45
−
µA
2.2
−
AVCC
V
0
−
Vref
V
1.19
1.34
1.49
V
tSAMP
Sampling time
φAD = 20 MHz
IVref
Vref current
VCC = 5 V, XIN = f1 = φAD = 20 MHz
Vref
Reference voltage
VIA
Analog input voltage (3)
OCVREF On-chip reference voltage
Typ.
Vref = AVCC = 5.0 V
Vref = AVCC
10-bit mode
8-bit mode
φAD
Standard
Conditions
2 MHz ≤ φAD ≤ 4 MHz
Notes:
1. VCC/AVCC = Vref = 2.2 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise
specified.
2. The A/D conversion result will be undefined in wait mode, stop mode, when the flash memory stops, and in low-currentconsumption mode. Do not perform A/D conversion in these states or transition to these states during A/D conversion.
3. When the analog input voltage is over the reference voltage, the A/D conversion result will be 3FFh in 10-bit mode and FFh in
8-bit mode.
R01DS0021EJ0020 Rev.0.20
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Page 30 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.4
5. Electrical Characteristics
D/A Converter Characteristics
Symbol
Parameter
Standard
Condition
Min.
Typ.
Max.
Unit
−
Resolution
−
−
8
Bit
−
Absolute accuracy
−
−
2.5
LSB
tsu
Setup time
−
−
3
µs
RO
Output resistor
−
6
−
kΩ
IVref
Reference power input current
−
−
1.5
mA
(Note 2)
Notes:
1. VCC/AVCC = Vref = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This applies when one D/A converter is used and the value of the DAi register (i = 0 or 1) for the unused D/A converter is 00h.
The resistor ladder of the A/D converter is not included.
Table 5.5
Comparator A Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Unit
Max.
LVREF
External reference voltage input range
1.4
−
VCC
V
LVCMP1,
LVCMP2
External comparison voltage input
range
−0.3
−
VCC + 0.3
V
−
Offset
−
Comparator output delay time (2)
−
Comparator operating current
−
50
200
mV
At falling, VI = Vref − 100 mV
−
3
−
µs
At falling, VI = Vref − 1 V or below
−
1.5
−
µs
At rising, VI = Vref + 100 mV
−
2
−
µs
At rising, VI = Vref + 1 V or above
−
0.5
−
µs
VCC = 5.0 V
−
0.5
−
µA
Notes:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is disabled.
Table 5.6
Comparator B Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
0
−
VCC − 1.4
−0.3
−
VCC + 0.3
V
−
5
100
mV
V
Vref
IVREF1, IVREF3 input reference voltage
VI
IVCMP1, IVCMP3 input voltage
−
Offset
td
Comparator output delay time (2)
VI = Vref ± 100 mV
−
0.1
−
µs
ICMP
Comparator operating current
VCC = 5.0 V
−
17.5
−
µA
Notes:
1. VCC = 2.7 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. When the digital filter is disabled.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 31 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.7
5. Electrical Characteristics
Flash Memory (Program ROM) Electrical Characteristics
Symbol
Parameter
Conditions
Standard
Min.
Typ.
Max.
Unit
−
Program/erase endurance (2)
1,000 (3)
−
−
times
−
Byte program time
−
80
500
µs
−
Block erase time
−
0.3
−
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
5+CPU clock
× 3 cycles
ms
−
Interval from erase start/restart until
following suspend request
0
−
−
µs
−
Time from suspend until erase restart
−
−
30+CPU clock
× 1 cycle
µs
td(CMDRST-
Time from when command is forcibly
terminated until reading is enabled
−
−
30+CPU clock
× 1 cycle
µs
READY)
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
1.8
−
5.5
V
−
Program, erase temperature
0
−
60
°C
−
Data hold time (7)
20
−
−
year
Ambient temperature = 55°C
Notes:
1. VCC = 2.7 to 5.5 V and Topr = 0 to 60°C, unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 1,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. It is also advisable to retain data on the erasure endurance of each block and limit
the number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. The data hold time includes time that the power supply is off or the clock is not supplied.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 32 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.8
5. Electrical Characteristics
Flash Memory (Data flash Block A to Block D) Electrical Characteristics
Symbol
Parameter
Standard
Conditions
Min.
Typ.
Max.
Unit
−
Program/erase endurance (2)
10,000 (3)
−
−
times
−
Byte program time
(program/erase endurance ≤ 1,000 times)
−
160
1,500
µs
−
Byte program time
(program/erase endurance > 1,000 times)
−
300
1,500
µs
−
Block erase time
(program/erase endurance ≤ 1,000 times)
−
0.2
1
s
−
Block erase time
(program/erase endurance > 1,000 times)
−
0.3
1
s
td(SR-SUS)
Time delay from suspend request until
suspend
−
−
5+CPU clock
× 3 cycles
ms
−
Interval from erase start/restart until
following suspend request
0
−
−
µs
−
Time from suspend until erase restart
−
−
30+CPU clock
× 1 cycle
µs
td(CMDRSTREADY)
Time from when command is forcibly
terminated until reading is enabled
−
−
30+CPU clock
× 1 cycle
µs
−
Program, erase voltage
2.7
−
5.5
V
−
Read voltage
1.8
−
5.5
V
−
Program, erase temperature
−20 (7)
−
85
°C
−
Data hold time (8)
20
−
−
year
Ambient temperature = 55 °C
Notes:
1. VCC = 2.7 to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. Definition of programming/erasure endurance
The programming and erasure endurance is defined on a per-block basis.
If the programming and erasure endurance is n (n = 10,000), each block can be erased n times. For example, if 1,024 1-byte
writes are performed to different addresses in block A, a 1 Kbyte block, and then the block is erased, the
programming/erasure endurance still stands at one.
However, the same address must not be programmed more than once per erase operation (overwriting prohibited).
3. Endurance to guarantee all electrical characteristics after program and erase. (1 to Min. value can be guaranteed).
4. In a system that executes multiple programming operations, the actual erasure count can be reduced by writing to sequential
addresses in turn so that as much of the block as possible is used up before performing an erase operation. For example,
when programming groups of 16 bytes, the effective number of rewrites can be minimized by programming up to 128 groups
before erasing them all in one operation. In addition, averaging the erasure endurance between blocks A to D can further
reduce the actual erasure endurance. It is also advisable to retain data on the erasure endurance of each block and limit the
number of erase operations to a certain number.
5. If an error occurs during block erase, attempt to execute the clear status register command, then execute the block erase
command at least three times until the erase error does not occur.
6. Customers desiring program/erase failure rate information should contact their Renesas technical support representative.
7. −40°C for D version.
8. The data hold time includes time that the power supply is off or the clock is not supplied.
Suspend request
(FMR21 bit)
FST7 bit
FST6 bit
Fixed time
Clock-dependent
time
Access restart
td(SR-SUS)
FST6, FST7: Bit in FST register
FMR21: Bit in FMR2 register
Figure 5.2
Time delay until Suspend
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 33 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.9
5. Electrical Characteristics
Voltage Detection 0 Circuit Electrical Characteristics
Symbol
Vdet0
Parameter
Standard
Unit
Min.
Typ.
Max.
Voltage detection level Vdet0_0 (2)
1.80
1.90
2.05
V
(2)
2.15
2.35
2.50
V
Voltage detection level Vdet0_2 (2)
2.70
2.85
3.05
V
Voltage detection level Vdet0_3 (2)
3.55
3.80
4.05
V
At the falling of VCC from 5 V
to (Vdet0_0 − 0.1) V
−
6
150
µs
VCA25 = 1, VCC = 5.0 V
−
1.5
−
µA
−
−
100
µs
Voltage detection level Vdet0_1
−
Condition
Voltage detection 0 circuit response time
(4)
−
Voltage detection circuit self power consumption
td(E-A)
Waiting time until voltage detection circuit
operation starts (3)
Notes:
1. The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
2. Select the voltage detection level with bits VDSEL0 and VDSEL1 in the OFS register.
3. Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA25 bit in the VCA2
register to 0.
4. Time until the voltage monitor 0 reset is generated after the voltage passes Vdet0.
Table 5.10
Voltage Detection 1 Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
Voltage detection level Vdet1_0 (2)
At the falling of VCC
2.00
2.20
2.40
V
Voltage detection level Vdet1_1 (2)
At the falling of VCC
2.15
2.35
2.55
V
Voltage detection level Vdet1_2
(2)
At the falling of VCC
2.30
2.50
2.70
V
Voltage detection level Vdet1_3
(2)
At the falling of VCC
2.45
2.65
2.85
V
Voltage detection level Vdet1_4 (2)
At the falling of VCC
2.60
2.80
3.00
V
Voltage detection level Vdet1_5 (2)
At the falling of VCC
2.75
2.95
3.15
V
Voltage detection level Vdet1_6 (2)
At the falling of VCC
2.85
3.10
3.40
V
Voltage detection level Vdet1_7
(2)
At the falling of VCC
3.00
3.25
3.55
V
Voltage detection level Vdet1_8
(2)
At the falling of VCC
3.15
3.40
3.70
V
Voltage detection level Vdet1_9 (2)
At the falling of VCC
3.30
3.55
3.85
V
Voltage detection level Vdet1_A (2)
At the falling of VCC
3.45
3.70
4.00
V
Voltage detection level Vdet1_B
(2)
At the falling of VCC
3.60
3.85
4.15
V
Voltage detection level Vdet1_C
(2)
At the falling of VCC
3.75
4.00
4.30
V
Voltage detection level Vdet1_D (2)
At the falling of VCC
3.90
4.15
4.45
V
Voltage detection level Vdet1_E (2)
At the falling of VCC
4.05
4.30
4.60
V
(2)
At the falling of VCC
4.20
4.45
4.75
V
Vdet1_0 to Vdet1_5
selected
−
0.07
−
V
Vdet1_6 to Vdet1_F
selected
−
0.10
−
V
Voltage detection 1 circuit response time (3)
At the falling of VCC from
5 V to (Vdet1_0 − 0.1) V
−
60
150
µs
−
Voltage detection circuit self power consumption
VCA26 = 1, VCC = 5.0 V
−
1.7
−
µA
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
−
−
100
µs
Vdet1
Voltage detection level Vdet1_F
−
−
Notes:
1.
2.
3.
4.
Hysteresis width at the rising of Vcc in voltage
detection 1 circuit
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
Select the voltage detection level with bits VD1S0 to VD1S3 in the VD1LS register.
Time until the voltage monitor 1 interrupt request is generated after the voltage passes Vdet1.
Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA26 bit in the VCA2
register to 0.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 34 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.11
5. Electrical Characteristics
Voltage Detection 2 Circuit Electrical Characteristics
Symbol
Vdet2
Parameter
Voltage detection level Vdet2_0 (2)
Voltage detection level Vdet2_EXT
Standard
Condition
(2)
Typ.
At the falling of VCC
3.70
4.00
4.30
V
At the falling of LVCMP2
TBD
1.34
TBD
V
−
0.10
−
V
−
20
150
µs
−
1.7
−
µA
−
−
100
µs
−
Hysteresis width at the rising of Vcc in voltage detection
2 circuit
−
Voltage detection 2 circuit response time (3)
At the falling of Vcc from
5 V to (Vdet2_0 − 0.1) V
−
Voltage detection circuit self power consumption
VCA27 = 1, VCC = 5.0 V
td(E-A)
Waiting time until voltage detection circuit operation
starts (4)
Notes:
1.
2.
3.
4.
Unit
Min.
Max.
The measurement condition is VCC = 1.8 V to 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version).
The voltage detection level varies with detection targets. Select the level with the VCA24 bit in the VCA2 register.
Time until the voltage monitor 2 interrupt request is generated after the voltage passes Vdet2.
Necessary time until the voltage detection circuit operates after setting to 1 again after setting the VCA27 bit in the VCA2
register to 0.
Table 5.12
Power-on Reset Circuit (2)
Symbol
Parameter
Condition
External power VCC rise gradient
trth
Standard
Min.
Typ.
Max.
0
−
50,000
(1)
Unit
mV/ms
Notes:
1. The measurement condition is Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. To use the power-on reset function, enable voltage monitor 0 reset by setting the LVDAS bit in the OFS register to 0.
Vdet0 (1)
Vdet0 (1)
trth
trth
External
Power VCC
0.5 V
tw(por) (2)
Voltage detection 0
circuit response time
Internal
reset signal
1
× 32
fOCO-S
1
× 32
fOCO-S
Notes:
1. Vdet0 indicates the voltage detection level of the voltage detection 0 circuit. Refer to 6. Voltage Detection
Circuit for details.
2. tw(por) indicates the duration the external power VCC must be held below the valid voltage (0.5 V) to enable
a power-on reset. When turning on the power after it falls with voltage monitor 0 reset disabled, maintain
tw(por) for 1 ms or more.
Figure 5.3
Power-on Reset Circuit Electrical Characteristics
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 35 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.13
5. Electrical Characteristics
High-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
−
Parameter
High-speed on-chip oscillator frequency after
reset
High-speed on-chip oscillator frequency when
the FRA4 register correction value is written into
the FRA1 register and the FRA5 register
correction value into the FRA3 register (2)
High-speed on-chip oscillator frequency when
the FRA6 register correction value is written into
the FRA1 register and the FRA7 register
correction value into the FRA3 register
Standard
Condition
Unit
Min.
Typ.
Max.
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
39.4
40
40.6
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
39.4
40
40.6
MHz
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
36.311
36.864
37.417
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
36.311
36.864
37.417
MHz
VCC = 1.8 V to 5.5 V
−20°C ≤ Topr ≤ 85°C
31.52
32
32.48
MHz
VCC = 1.8 V to 5.5 V
−40°C ≤ Topr ≤ 85°C
31.52
32
32.48
MHz
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
100
450
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
500
−
µA
Notes:
1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. This enables the setting errors of bit rates such as 9600 bps and 38400 bps to be 0% when the serial interface is used in
UART mode.
Table 5.14
Low-speed On-Chip Oscillator Circuit Electrical Characteristics
Symbol
Parameter
Condition
Standard
Min.
Typ.
Max.
Unit
fOCO-S
Low-speed on-chip oscillator frequency
60
125
250
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
30
100
kHz
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
2
−
µA
fOCO-WDT
Low-speed on-chip oscillator frequency for the
watchdog timer
60
125
250
kHz
−
Oscillation stability time
VCC = 5.0 V, Topr = 25°C
−
30
100
µs
−
Self power consumption at oscillation
VCC = 5.0 V, Topr = 25°C
−
2
−
µA
Note:
1. VCC = 1.8 to 5.5 V, Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
Table 5.15
Power Supply Circuit Timing Characteristics
Symbol
td(P-R)
Parameter
Condition
Time for internal power supply stabilization during
power-on (2)
Standard
Min.
Typ.
Max.
−
−
2,000
Unit
µs
Notes:
1. The measurement condition is VCC = 1.8 to 5.5 V and Topr = 25°C.
2. Waiting time until the internal power supply generation circuit stabilizes during power-on.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 36 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.16
Symbol
5. Electrical Characteristics
Timing Requirements of Synchronous Serial Communication Unit (SSU) (1)
Parameter
Conditions
Standard
Unit
Min.
Typ.
Max.
4
−
−
tCYC (2)
tSUCYC
tSUCYC
SSCK clock cycle time
tHI
SSCK clock “H” width
0.4
−
0.6
tLO
SSCK clock “L” width
0.4
−
0.6
tSUCYC
tRISE
SSCK clock rising
time
Master
−
−
1
tCYC (2)
Slave
−
−
1
µs
tFALL
SSCK clock falling
time
Master
−
−
1
tCYC (2)
−
−
1
µs
tSU
SSO, SSI data input setup time
100
−
−
ns
tH
SSO, SSI data input hold time
1
−
−
tCYC (2)
tLEAD
SCS setup time
Slave
1tCYC + 50
−
−
ns
tLAG
SCS hold time
Slave
1tCYC + 50
−
−
ns
tOD
SSO, SSI data output delay time
−
−
1
tCYC (2)
tSA
SSI slave access time
tOR
SSI slave out open time
Slave
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
2.7 V ≤ VCC ≤ 5.5 V
−
−
1.5tCYC + 100
ns
1.8 V ≤ VCC < 2.7 V
−
−
1.5tCYC + 200
ns
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 37 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Master, CPHS = 1
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
4-Wire Bus Communication Mode, Master, CPHS = 0
VIH or VOH
SCS (output)
VIL or VOL
tHI
tFALL
tRISE
SSCK (output)
(CPOS = 1)
tLO
tHI
SSCK (output)
(CPOS = 0)
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
tH
CPHS, CPOS: Bits in SSMR register
Figure 5.4
I/O Timing of Synchronous Serial Communication Unit (SSU) (Master)
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
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Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
4-Wire Bus Communication Mode, Slave, CPHS = 1
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
4-Wire Bus Communication Mode, Slave, CPHS = 0
VIH or VOH
SCS (input)
VIL or VOL
tLEAD
tHI
tFALL
tRISE
tLAG
SSCK (input)
(CPOS = 1)
tLO
tHI
SSCK (input)
(CPOS = 0)
tLO
tSUCYC
SSO (input)
tSU
tH
SSI (output)
tSA
tOD
tOR
CPHS, CPOS: Bits in SSMR register
Figure 5.5
I/O Timing of Synchronous Serial Communication Unit (SSU) (Slave)
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 39 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
tHI
VIH or VOH
SSCK
VIL or VOL
tLO
tSUCYC
SSO (output)
tOD
SSI (input)
tSU
Figure 5.6
tH
I/O Timing of Synchronous Serial Communication Unit (SSU) (Clock Synchronous
Communication Mode)
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 40 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.17
5. Electrical Characteristics
Timing Requirements of I2C bus Interface (1)
Symbol
Parameter
Condition
Standard
Typ.
−
12tCYC + 600 (2)
−
3tCYC + 300 (2)
Min.
tSCL
SCL input cycle time
tSCLH
SCL input “H” width
tSCLL
SCL input “L” width
tsf
tSP
SCL, SDA input fall time
SCL, SDA input spike pulse rejection time
tBUF
SDA input bus-free time
5tCYC (2)
tSTAH
Start condition input hold time
3tCYC (2)
tSTAS
Retransmit start condition input setup time
tSTOP
Stop condition input setup time
tSDAS
Data input setup time
tSDAH
Data input hold time
Max.
−
Unit
ns
−
ns
−
ns
−
300
−
ns
ns
−
1tCYC (2)
−
−
−
ns
3tCYC (2)
−
−
ns
3tCYC (2)
−
−
ns
1tCYC + 40 (2)
10
−
−
ns
−
−
ns
5tCYC + 500
−
−
−
(2)
ns
Notes:
1. VCC = 1.8 to 5.5 V, VSS = 0 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.
2. 1tCYC = 1/f1(s)
VIH
SDA
VIL
tBUF
tSTAH
tSCLH
tSTAS
tSP
tSTOP
SCL
P(2)
S(1)
tsf
Sr(3)
tSCLL
tsr
tSCL
P(2)
tSDAS
tSDAH
Notes:
1. Start condition
2. Stop condition
3. Retransmit start condition
Figure 5.7
I/O Timing of I2C bus Interface
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 41 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.18
5. Electrical Characteristics
Electrical Characteristics (1) [4.2 V ≤ Vcc ≤ 5.5 V]
Symbol
Parameter
VOH
Output “H”
voltage
VOL
Output “L”
voltage
VT+-VT-
Hysteresis
Other than XOUT
XOUT
Other than XOUT
XOUT
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
INT0, INT1, INT2,
INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRDIOA0,
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1,
TRDIOB1, TRDIOC1,
TRDIOD1, TRCTRG,
TRCCLK, ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
RESET
Input “H” current
Input “L” current
Pull-up resistance
Feedback XIN
resistance
Feedback XCIN
resistance
RAM hold voltage
Standard
Min.
Typ.
Drive capacity High VCC = 5 V IOH = −20 mA VCC − 2.0
−
VCC − 2.0
−
Drive capacity Low VCC = 5 V IOH = −5 mA
IOH = −200 µA
1.0
−
VCC = 5 V
Drive capacity High VCC = 5 V IOL = 20 mA
−
−
−
−
Drive capacity Low VCC = 5 V IOL = 5 mA
IOL = 200 µA
−
−
VCC = 5 V
VCC = 5.0 V
0.1
1.2
Condition
VCC = 5.0 V
VI = 5 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
VI = 0 V, VCC = 5.0 V
During stop mode
Max.
VCC
VCC
VCC
2.0
2.0
0.5
−
Unit
V
V
V
V
V
V
V
−
V
−
5.0
µA
−
−5.0
25
−
50
0.3
100
−
µA
kΩ
MΩ
−
8
−
MΩ
1.8
−
−
V
0.1
1.2
−
−
Note:
1. 4.2 V ≤ VCC ≤ 5.5 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 20 MHz, unless otherwise specified.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 42 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.19
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (2) [3.3 V ≤ Vcc ≤ 5.5 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply
High-speed
current
clock mode
(VCC = 3.3 to 5.5 V)
Single-chip mode,
output pins are
open, other pins
are VSS
High-speed
on-chip
oscillator mode
Low-speed
on-chip
oscillator mode
Low-speed
clock mode
Wait mode
Stop mode
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 20 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 16 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16, MSTIIC = MSTTRD = MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division, Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1, Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1, Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ.
Max.
6.5
15
Unit
mA
−
5.3
12.5
mA
−
3.6
−
mA
−
3.0
−
mA
−
2.2
−
mA
−
1.5
−
mA
−
7.0
15
mA
−
3.0
−
mA
−
1
−
mA
−
90
400
µA
−
85
400
µA
−
47
−
µA
−
15
100
µA
−
4
90
µA
−
3.5
−
µA
−
2.0
5.0
µA
−
5.0 (1)
−
µA
TBD
(2)
Notes:
1. Value when the program ROM capacity of the product is 16 Kbytes to 32 Kbytes.
2. Value when the program ROM capacity of the product is 48 Kbytes to 128 Kbytes.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 43 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 5 V, VSS = 0 V at Topr = 25°C)
Table 5.20
External Clock Input (XOUT, XCIN)
Symbol
tc(XOUT)
tWH(XOUT)
tWL(XOUT)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
−
24
−
24
−
14
TBD
7
TBD
7
TBD
Parameter
XOUT input cycle time
XOUT input “H” width
XOUT input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XOUT), tC(XCIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 5 V
tWH(XOUT),
tWH(XCIN)
External Clock Input
tWL(XOUT), tWL(XCIN)
Figure 5.8
Table 5.21
External Clock Input Timing Diagram when VCC = 5 V
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
100
−
40
−
40
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 5 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.9
TRAIO Input Timing Diagram when VCC = 5 V
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 44 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.22
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
td(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
TXDi output delay time
RXDi input setup time
RXDi input hold time
When external clock is selected
When internal clock is selected
Standard
Min.
Max.
200
−
100
−
100
−
−
90
0
−
10
−
90
−
−
10
90
−
90
−
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 5 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.10
Table 5.23
Serial Interface Timing Diagram when VCC = 5 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
INTi input “H” width, KIi input “H” width
Standard
Min.
Max.
−
250 (1)
INTi input “L” width, KIi input “L” width
250 (2)
Symbol
tW(INH)
tW(INL)
Parameter
−
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 5 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.11
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when Vcc
=5V
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 45 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.24
5. Electrical Characteristics
Electrical Characteristics (3) [2.7 V ≤ Vcc < 4.2 V]
Symbol
Parameter
VOH
Output “H” voltage
Other than XOUT
VOL
Output “L” voltage
XOUT
Other than XOUT
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
RfXCIN
VRAM
RESET
Input “H” current
Input “L” current
Pull-up resistance
Feedback resistance XIN
Feedback resistance XCIN
RAM hold voltage
XOUT
INT0, INT1, INT2,
INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRDIOA0,
TRDIOB0,
TRDIOC0,
TRDIOD0,
TRDIOA1,
TRDIOB1,
TRDIOC1,
TRDIOD1,
TRCTRG, TRCCLK,
ADTRG,
RXD0, RXD1,
RXD2, CLK0,
CLK1, CLK2, SSI,
SCL, SDA, SSO
Condition
Drive capacity High IOH = −5 mA
Drive capacity Low IOH = −1 mA
IOH = −200 µA
Drive capacity High IOL = 5 mA
Drive capacity Low IOL = 1 mA
IOL = 200 µA
VCC = 3.0 V
VCC = 3.0 V
VI = 3 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
VI = 0 V, VCC = 3.0 V
During stop mode
Standard
Min.
Typ.
VCC − 0.5
−
VCC − 0.5
−
1.0
−
−
−
−
−
−
−
0.1
0.4
Max.
VCC
VCC
VCC
0.5
0.5
0.5
−
Unit
V
V
V
V
V
V
V
0.1
0.5
−
V
−
−
µA
−
42
−
−
1.8
−
84
0.3
8
−
4.0
−4.0
168
−
−
−
µA
kΩ
MΩ
MΩ
V
Note:
1. 2.7 V ≤ VCC < 4.2 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 10 MHz, unless otherwise specified.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 46 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.25
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (4) [2.7 V ≤ Vcc < 3.3 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed
(VCC = 2.7 to 3.3 V)
clock mode
Single-chip mode,
output pins are open,
other pins are VSS
High-speed
on-chip
oscillator
mode
Low-speed
on-chip
oscillator
mode
Low-speed
clock mode
Wait mode
Stop mode
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
No division
XIN = 10 MHz (square wave)
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 20 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
No division
XIN clock off
High-speed on-chip oscillator on fOCO-F = 10 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16
MSTIIC = MSTTRD = MSTTRC = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division, Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0, VCA20 = 1
XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ. Max.
3.5
10
Unit
mA
−
1.5
7.5
mA
−
7.0
15
mA
−
3.0
−
mA
−
4.0
−
mA
−
1.5
−
mA
−
1
−
mA
−
90
390
µA
−
80
400
µA
−
40
−
µA
−
15
90
µA
−
4
80
µA
−
3.5
−
µA
−
2.0
5.0
µA
−
5.0 (1)
−
µA
TBD
(2)
Notes:
1. Value when the program ROM capacity of the product is 16 Kbytes to 32 Kbytes.
2. Value when the program ROM capacity of the product is 48 Kbytes to 128 Kbytes.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 47 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 3 V, VSS = 0 V at Topr = 25°C)
Table 5.26
External Clock Input (XOUT, XCIN)
Symbol
tc(XOUT)
tWH(XOUT)
tWL(XOUT)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
50
−
24
−
24
−
14
TBD
7
TBD
7
TBD
Parameter
XOUT input cycle time
XOUT input “H” width
XOUT input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XOUT), tC(XCIN)
tWH(XOUT),
tWH(XCIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 3 V
External Clock Input
tWL(XOUT), tWL(XCIN)
Figure 5.12
External Clock Input Timing Diagram when VCC = 3 V
Table 5.27
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
300
−
120
−
120
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 3 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.13
TRAIO Input Timing Diagram when VCC = 3 V
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 48 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.28
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
td(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi Input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
TXDi output delay time
RXDi input setup time
RXDi input hold time
When external clock is selected
When internal clock is selected
Standard
Min.
Max.
300
−
150
−
150
−
−
120
0
−
30
−
90
−
−
30
120
−
90
−
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 3 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.14
Table 5.29
Serial Interface Timing Diagram when VCC = 3 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
INTi input “H” width, KIi input “H” width
Standard
Min.
Max.
−
380 (1)
INTi input “L” width, KIi input “L” width
380 (2)
Symbol
tW(INH)
tW(INL)
Parameter
Unit
ns
−
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 3 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.15
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when Vcc
=3V
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 49 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.30
5. Electrical Characteristics
Electrical Characteristics (5) [1.8 V ≤ Vcc < 2.7 V]
Symbol
Parameter
VOH
Output “H” voltage
Other than XOUT
VOL
Output “L” voltage
XOUT
Other than XOUT
VT+-VT-
Hysteresis
IIH
IIL
RPULLUP
RfXIN
Input “H” current
Input “L” current
Pull-up resistance
Feedback
resistance
Feedback
resistance
RAM hold voltage
XOUT
INT0, INT1, INT2,
INT3, INT4,
KI0, KI1, KI2, KI3,
TRAIO, TRCIOA,
TRCIOB, TRCIOC,
TRCIOD, TRDIOA0,
TRDIOB0, TRDIOC0,
TRDIOD0, TRDIOA1,
TRDIOB1, TRDIOC1,
TRDIOD1, TRCTRG,
TRCCLK,
ADTRG,
RXD0, RXD1, RXD2,
CLK0, CLK1, CLK2,
SSI, SCL, SDA, SSO
VRAM
Max.
VCC
VCC
VCC
0.5
0.5
0.5
−
Unit
V
V
V
V
V
V
V
0.05
0.20
−
V
−
−
µA
XIN
−
70
−
−
140
0.3
4.0
−4.0
300
−
µA
kΩ
MΩ
XCIN
−
8
−
MΩ
1.8
−
−
V
RESET
RfXCIN
Standard
Min.
Typ.
Drive capacity High IOH = −2 mA
VCC − 0.5
−
VCC − 0.5
−
Drive capacity Low IOH = −1 mA
1.0
−
IOH = −200 µA
Drive capacity High IOL = 2 mA
−
−
−
−
Drive capacity Low IOL = 1 mA
−
−
IOL = 200 µA
0.05
0.2
VCC = 2.2 V
Condition
VCC = 2.2 V
VI = 2.2 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
VI = 0 V, VCC = 2.2 V
During stop mode
Note:
1. 1.8 V ≤ VCC < 2.7 V and Topr = −20 to 85°C (N version) / −40 to 85°C (D version), f(XIN) = 5 MHz, unless otherwise specified.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 50 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.31
Symbol
ICC
5. Electrical Characteristics
Electrical Characteristics (6) [1.8 V ≤ Vcc < 2.7 V]
(Topr = −20 to 85°C (N version) / −40 to 85°C (D version), unless otherwise specified.)
Parameter
Condition
Power supply current High-speed XIN = 5 MHz (square wave)
(VCC = 1.8 to 2.7 V)
clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Single-chip mode,
No division
output pins are open,
XIN = 5 MHz (square wave)
other pins are VSS
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
High-speed XIN clock off
High-speed on-chip oscillator on fOCO-F = 5 MHz
on-chip
Low-speed on-chip oscillator on = 125 kHz
oscillator
No division
mode
XIN clock off
High-speed on-chip oscillator on fOCO-F = 5 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-8
XIN clock off
High-speed on-chip oscillator on fOCO-F = 4 MHz
Low-speed on-chip oscillator on = 125 kHz
Divide-by-16
MSTIIC = MSTTRD = MSTTRC = 1
Low-speed XIN clock off
High-speed on-chip oscillator off
on-chip
Low-speed on-chip oscillator on = 125 kHz
oscillator
Divide-by-8, FMR27 = 1, VCA20 = 0
mode
Low-speed XIN clock off
clock mode High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division, FMR27 = 1, VCA20 = 0
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz
No division, Program operation on RAM
Flash memory off, FMSTP = 1, VCA20 = 0
Wait mode XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock operation
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator on = 125 kHz
While a WAIT instruction is executed
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
XIN clock off
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
XCIN clock oscillator on = 32 kHz (peripheral clock off)
While a WAIT instruction is executed
VCA27 = VCA26 = VCA25 = 0
VCA20 = 1
Stop mode XIN clock off, Topr = 25°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
XIN clock off, Topr = 85°C
High-speed on-chip oscillator off
Low-speed on-chip oscillator off
CM10 = 1
Peripheral clock off
VCA27 = VCA26 = VCA25 = 0
Min.
−
Standard
Typ. Max.
2.2
−
Unit
mA
−
0.8
−
mA
−
2.5
10
mA
−
1.7
−
mA
−
1
−
mA
−
90
300
µA
−
80
350
µA
−
40
−
µA
−
15
90
µA
−
4
80
µA
−
3.5
−
µA
−
2.0
5
µA
−
5.0 (1)
−
µA
TBD
(2)
Notes:
1. Value when the program ROM capacity of the product is 16 Kbytes to 32 Kbytes.
2. Value when the program ROM capacity of the product is 48 Kbytes to 128 Kbytes.
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 51 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
5. Electrical Characteristics
Timing Requirements
(Unless Otherwise Specified: VCC = 2.2 V, VSS = 0 V at Topr = 25°C)
Table 5.32
External Clock Input (XOUT, XCIN)
Symbol
tc(XOUT)
tWH(XOUT)
tWL(XOUT)
tc(XCIN)
tWH(XCIN)
tWL(XCIN)
Standard
Min.
Max.
200
−
90
−
90
−
14
TBD
7
TBD
7
TBD
Parameter
XOUT input cycle time
XOUT input “H” width
XOUT input “L” width
XCIN input cycle time
XCIN input “H” width
XCIN input “L” width
tC(XOUT), tC(XCIN)
tWH(XOUT),
tWH(XCIN)
Unit
ns
ns
ns
µs
µs
µs
VCC = 2.2 V
External Clock Input
tWL(XOUT), tWL(XCIN)
Figure 5.16
External Clock Input Timing Diagram when VCC = 2.2 V
Table 5.33
TRAIO Input
Symbol
tc(TRAIO)
tWH(TRAIO)
tWL(TRAIO)
Standard
Min.
Max.
500
−
200
−
200
−
Parameter
TRAIO input cycle time
TRAIO input “H” width
TRAIO input “L” width
tC(TRAIO)
Unit
ns
ns
ns
VCC = 2.2 V
tWH(TRAIO)
TRAIO input
tWL(TRAIO)
Figure 5.17
TRAIO Input Timing Diagram when VCC = 2.2 V
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 52 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Table 5.34
5. Electrical Characteristics
Serial Interface
Symbol
tc(CK)
tW(CKH)
tW(CKL)
td(C-Q)
th(C-Q)
tsu(D-C)
th(C-D)
td(C-Q)
tsu(D-C)
th(C-D)
Parameter
CLKi input cycle time
CLKi input “H” width
CLKi input “L” width
TXDi output delay time
TXDi hold time
RXDi input setup time
RXDi input hold time
TXDi output delay time
RXDi input setup time
RXDi input hold time
When external clock is selected
When internal clock is selected
Standard
Min.
Max.
800
−
400
−
400
−
−
200
0
−
150
−
90
−
−
200
150
−
90
−
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
i = 0 to 2
VCC = 2.2 V
tC(CK)
tW(CKH)
CLKi
tW(CKL)
th(C-Q)
TXDi
td(C-Q)
tsu(D-C)
th(C-D)
RXDi
i = 0 to 2
Figure 5.18
Table 5.35
Serial Interface Timing Diagram when VCC = 2.2 V
External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)
Symbol
tW(INH)
tW(INL)
Standard
Min.
Max.
−
1000 (1)
Parameter
INTi input “H” width, KIi input “H” width
1000
INTi input “L” width, KIi input “L” width
(2)
−
Unit
ns
ns
Notes:
1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock
frequency × 3) or the minimum value of standard, whichever is greater.
VCC = 2.2 V
INTi input
(i = 0 to 4)
tW(INL)
KIi input
(i = 0 to 3)
Figure 5.19
tW(INH)
Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi when Vcc
= 2.2 V
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
Page 53 of 54
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
R8C/35M Group
Package Dimensions
Package Dimensions
Diagrams showing the latest package dimensions and mounting information are available in the “Packages” section of
the Renesas Electronics website.
JEITA Package Code
P-LQFP52-10x10-0.65
RENESAS Code
PLQP0052JA-A
Previous Code
52P6A-A
MASS[Typ.]
0.3g
HD
*1
D
39
27
40
NOTE)
1. DIMENSIONS "*1" AND "*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION "*3" DOES NOT
INCLUDE TRIM OFFSET.
26
bp
c1
c
E
*2
HE
b1
Reference Dimension in Millimeters
Symbol
14
1
Terminal cross section
ZE
52
13
ZD
Index mark
A
A2
c
F
A1
S
e
y S
*3
L
bp
Min
9.9
9.9
Nom
10.0
10.0
1.4
11.8 12.0
11.8 12.0
0.05
0.27
0.09
0°
L1
x
Detail F
R01DS0021EJ0020 Rev.0.20
Feb 15, 2011
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
e
x
y
ZD
ZE
L
L1
0.35
Max
10.1
10.1
12.2
12.2
1.7
0.1 0.15
0.32 0.37
0.30
0.145 0.20
0.125
8°
0.65
0.13
0.10
1.1
1.1
0.5 0.65
1.0
Page 54 of 54
REVISION HISTORY
Rev.
0.10
0.20
Date
Sep 28, 2010
Feb 15, 2011
R8C/35M Group Datasheet
Description
Summary
Page
−
35
36
42
50
First Edition issued
Table 5.11 revised, Note 2 added
Table 5.13 and Table 5.14 revised
Table 5.18 revised
Table 5.30 revised
All trademarks and registered trademarks are the property of their respective owners.
C-1
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes
on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under
General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each
other, the description in the body of the manual takes precedence.
1. Handling of Unused Pins
Handle unused pins in accord with the directions given under Handling of Unused Pins in the
manual.
 The input pins of CMOS products are generally in the high-impedance state. In operation
with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the
vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur
due to the false recognition of the pin state as an input signal become possible. Unused
pins should be handled as described under Handling of Unused Pins in the manual.
2. Processing at Power-on
The state of the product is undefined at the moment when power is supplied.
 The states of internal circuits in the LSI are indeterminate and the states of register
settings and pins are undefined at the moment when power is supplied.
In a finished product where the reset signal is applied to the external reset pin, the states
of pins are not guaranteed from the moment when power is supplied until the reset
process is completed.
In a similar way, the states of pins in a product that is reset by an on-chip power-on reset
function are not guaranteed from the moment when power is supplied until the power
reaches the level at which resetting has been specified.
3. Prohibition of Access to Reserved Addresses
Access to reserved addresses is prohibited.
 The reserved addresses are provided for the possible future expansion of functions. Do
not access these addresses; the correct operation of LSI is not guaranteed if they are
accessed.
4. Clock Signals
After applying a reset, only release the reset line after the operating clock signal has become
stable. When switching the clock signal during program execution, wait until the target clock
signal has stabilized.
 When the clock signal is generated with an external resonator (or from an external
oscillator) during a reset, ensure that the reset line is only released after full stabilization of
the clock signal. Moreover, when switching to a clock signal produced with an external
resonator (or by an external oscillator) while program execution is in progress, wait until
the target clock signal is stable.
5. Differences between Products
Before changing from one product to another, i.e. to one with a different part number, confirm
that the change will not lead to problems.
 The characteristics of MPU/MCU in the same group but having different part numbers may
differ because of the differences in internal memory capacity and layout pattern. When
changing to products of different part numbers, implement a system-evaluation test for
each of the products.
Notice
1.
All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas
Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to
be disclosed by Renesas Electronics such as that disclosed through our website.
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You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part.
4.
Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for
the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the
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When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and
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malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the
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(Note 1)
"Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majority-owned subsidiaries.
(Note 2)
"Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics.
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