RFP50N05L Data Sheet 50A, 50V, 0.022 Ohm, Logic Level, N-Channel Power MOSFETs These are logic-level N-channel power MOSFETs manufactured using the MegaFET process. This process, which uses feature sizes approaching those of LSI integrated circuits gives optimum utilization of silicon, resulting in outstanding performance. They were designed for use with logic-level (5V) driving sources in applications such as programmable controllers, automotive switching, switching regulators, switching converters, motor relay drivers and emitter switches for bipolar transistors. This performance is accomplished through a special gate oxide design which provides full rated conductance at gate bias in the 3V - 5V range, thereby facilitating true on-off power control directly from integrated circuit supply voltages. Ordering Information RFP50N05L PACKAGE TO-220AB Features • 50A, 50V • rDS(ON) = 0.022Ω • UIS SOA Rating Curve (Single Pulse) • Design Optimized for 5V Gate Drive • Can be Driven Directly from CMOS, NMOS, TTL Circuits • Compatible with Automotive Drive Requirements • SOA is Power Dissipation Limited • Nanosecond Switching Speeds • Linear Transfer Characteristics • High Input Impedance • Majority Carrier Device Formerly developmental type TA09872. PART NUMBER August 2004 BRAND F50N05L • Related Literature - TB334 “Guidelines for Soldering Surface Mount Components to PC Boards” Symbol D NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-263AB variant in the tape and reel, i.e., RFP50N05L9A. G S Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) ©2004 Fairchild Semiconductor Corporation RFP50N05L Rev. C RFP50N05L Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified RFP50N05L UNITS Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS 50 V Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . VDGR 50 V Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM 50 130 A A Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±10 V Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Above TC = 25oC, Derate Linearly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 0.88 W W/oC Single Pulse Avalanche Energy Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to UIS SOA Curve - Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 150 oC Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300 260 oC oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 10) 50 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 9) 1 - 2 V VDS = Rated BVDSS, VGS = 0 - - 25 µA VDS = 0.8 x Rated BVDSS, VGS = 0, TC = 150oC - - 250 µA VGS = ±10V, VDS = 0V - - ±100 nA ID = 50A, VGS = 5V (Figure 7) - - 0.022 Ω ID = 50A, VGS = 4V - - 0.027 Ω VGS = 5V, RGS = 2.5Ω, RL = 1Ω (Figures 12, 15, 16) - - 100 ns - 15 - ns tr - 50 - ns tD(OFF) - 50 - ns tf - 15 - ns t(OFF) - - 100 ns - - 140 nC - - 80 nC - - 6 nC Zero Gate Voltage Drain Current IDSS Gate to Source Leakage Current IGSS Drain to Source On Resistance (Note 2) rDS(ON) Turn-On Time t(ON) Turn-On Delay Time tD(ON) Rise Time Turn-Off Delay Time Fall Time Turn-Off Time Total Gate Charge QG(TOT) VGS = 0 to 10V Gate Charge at 5V QG(5) VGS = 0 to 5V Threshold Gate Charge QG(th) VGS = 0 to 1V VDD = 40V, ID = 50A RL = 0.8Ω (Figures 17, 18) Thermal Resistance Junction to Case RθJC - - 1.14 oC/W Thermal Resistance Junction to Ambient RθJA - - 80 oC/W Source to Drain Diode Specifications PARAMETER Source to Drain Diode Voltage (Note 2) Diode Reverse Recovery Time SYMBOL VSD trr TEST CONDITIONS MIN TYP MAX UNITS ISD = 50A - - 1.5 V ISD = 50A, dISD/dt = 100A/µs - - 1.25 ns NOTES: 2. Pulsed: pulse duration = 300µs maximum, duty cycle = 2%. 3. Repititive rating: pulse width limited by maximum junction temperature. ©2004 Fairchild Semiconductor Corporation RFP50N05L Rev. C RFP50N05L Typical Performance Curves POWER DISSIPATION MULTIPLIER 1.2 50 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 25 50 75 100 125 30 20 10 0 25 0 0 40 150 50 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE 1000 TC = 25oC TJ = MAX RATED ID MAX CONTINUOUS DC OPERATION 10 OPERATION IN THIS AREA LIMITED BY rDS(ON) 1 0.1 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) ID(ON), DRAIN TO SOURCE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 100 VGS = 4V 60 VGS = 3V 40 20 VGS = 2V 0 0 1.5 3.0 4.5 6.0 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. SATURATION CHARACTERISTICS ©2004 Fairchild Semiconductor Corporation IDM 100 STARTING TJ = 25oC STARTING TJ = 150oC 0.1 1 10 FIGURE 4. UNCLAMPED INDUCTIVE SWITCHING SAFE OPERATING AREA PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. TC - 25oC VGS = 5V 80 150 tAV, TIME IN AVALANCHE (ms) 140 VGS = 10V 125 IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R = 0 TAV = (L/R) IN [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 10 0.01 100 FIGURE 3. FORWARD BIAS SAFE OPERATING AREA 120 100 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE IAS, AVALANCHE CURRENT (A) IDS, DRAIN TO SOURCE CURRENT (A) 100 75 TC, CASE TEMPERATURE (oC) 7.5 140 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. TC - 25oC 120 150oC 100 VDS = 15V 80 -55oC 25oC 60 40 20 0 0 1.5 3.0 4.5 6.0 7.5 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 6. TRANSFER CHARACTERISTICS RFP50N05L Rev. C RFP50N05L Typical Performance Curves (Continued) 2.0 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. VGS = 5V ID = 50A 2.5 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.0 1.5 1.0 0.5 PULSE DURATION = 80µs DUTY CYCLE = 0.5% MAX. ID = 50A, VGS = 5V 1.5 1.2 0.8 0.4 0 0 -50 0 50 100 150 4 5 TJ, JUNCTION TEMPERATURE (oC) FIGURE 7. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2.0 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250µA NORMALIZED GATE THRESHOLD VOLTAGE 1.8 1.2 0.8 0.4 0 50 100 TJ, JUNCTION TEMPERATURE (oC) ID = 250µA 1.8 1.2 0.8 0.4 0 -50 150 0 50 C, CAPACITANCE (pF) DRAIN TO SOURCE VOLTAGE (V) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS ≈ CDS + CGD 4000 CISS 3000 2000 COSS 1000 CRSS RL = 0Ω IG(REF) = 1.25mA 10 15 20 150 25 10 37.5 VDD = BVDSS 25 0.75BVDSS VDD = BVDSS 0.75BVDSS 5 GATE TO SOURCE VOLTAGE 0.50BVDSS 12.5 0.50BVDSS 0.25BVDSS 0.25BVDSS DRAIN TO SOURCE VOLTAGE 0 0 0 5 100 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 6000 5000 50 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE 0 7 FIGURE 8. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE 2.0 0 -50 6 VGS, GATE TO SOURCE VOLTAGE (V) GATE TO SOURCE VOLTAGE (V) NORMALIZED DRAIN TO SOURCE ON RESISTANCE 3.0 20 IG(REF) IG(ACT) TIME-MICROSECONDS 80 IG(REF) IG(ACT) VDS, DRAIN TO SOURCE (V) NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE ©2004 Fairchild Semiconductor Corporation FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR CONSTANT GATE CURRENT RFP50N05L Rev. C RFP50N05L Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS IAS + RG VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01Ω tAV FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 14. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) VDS td(OFF) tr VDS tf 90% 90% RL VGS + - DUT 10% 0 VDD 10% 90% RGS VGS VGS 0 FIGURE 15. SWITCHING TIME TEST CIRCUIT 50% 50% PULSE WIDTH 10% FIGURE 16. RESISTIVE SWITCHING WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS = 10V VGS Qg(5) + VDD DUT IG(REF) VGS = 5V VGS - VGS = 1V 0 Qg(TH) IG(REF) 0 FIGURE 17. GATE CHARGE TEST CIRCUIT ©2004 Fairchild Semiconductor Corporation FIGURE 18. GATE CHARGE WAVEFORMS RFP50N05L Rev. C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FAST ActiveArray™ FASTr™ Bottomless™ FPS™ CoolFET™ FRFET™ CROSSVOLT™ GlobalOptoisolator™ DOME™ GTO™ EcoSPARK™ HiSeC™ E2CMOS™ I2C™ EnSigna™ i-Lo™ FACT™ ImpliedDisconnect™ FACT Quiet Series™ ISOPLANAR™ LittleFET™ MICROCOUPLER™ MicroFET™ MicroPak™ MICROWIRE™ MSX™ MSXPro™ OCX™ OCXPro™ OPTOLOGIC Across the board. Around the world.™ OPTOPLANAR™ PACMAN™ The Power Franchise POP™ Programmable Active Droop™ Power247™ PowerSaver™ PowerTrench QFET QS™ QT Optoelectronics™ Quiet Series™ RapidConfigure™ RapidConnect™ µSerDes™ SILENT SWITCHER SMART START™ SPM™ Stealth™ SuperFET™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic TINYOPTO™ TruTranslation™ UHC™ UltraFET VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I11