RFP25N06, RF1S25N06, RF1S25N06SM
Data Sheet
January 2002
25A, 60V, 0.047 Ohm, N-Channel Power
MOSFETs
Features
• 25A, 60V
These N-Channel power MOSFETs are manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA09771.
Ordering Information
PART NUMBER
PACKAGE
• rDS(ON) = 0.047Ω
• Temperature Compensating PSPICE® Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 175oC Operating Temperature
• Related Literature
- TB334, “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
BRAND
D
RFP25N06
TO-220AB
RFP25N06
RF1S25N06
TO-262AA
F1S25N06
RF1S25N06SM
TO-263AB
F1S25N06
G
NOTE: When ordering use the entire part number. Add the suffix, 9A,
to obtain the TO-263AB variant in tape and reel, e.g. RF1S25N06SM9A.
S
Packaging
JEDEC TO- 220AB
DRAIN
(FLANGE)
JEDEC TO-263AB
SOURCE
DRAIN
GATE
GATE
DRAIN
(FLANGE)
SOURCE
JEDEC TO-262AA
DRAIN
(FLANGE)
©2002 Fairchild Semiconductor Corporation
SOURCE
DRAIN
GATE
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
RFP25N06, RF1S25N06, RF1S25N06SMS
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Single Pulse Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Junction Temperature Range . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFP25N06,
RF1S25N06, RF1S25N06SM
60
60
±20
25
(Figure 5)
(Figure 6)
72
0.48
-55 to 175
UNITS
V
V
V
A
W
W/oC
oC
oC
oC
300
260
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V (Figure 11)
60
-
-
V
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 10)
2
-
4
V
-
-
1
µA
-
-
50
µA
VGS = ±20V
-
-
±100
nA
ID = 25A, VGS = 10V (Figure 9)
-
-
0.047
Ω
VDD = 30V, ID = 12.5A
RL = 2.4Ω, VGS = 10V
RGS = 10Ω
(Figure 13)
-
-
60
ns
-
14
-
ns
-
30
-
ns
td(OFF)
-
45
-
ns
tf
-
22
-
ns
tOFF
-
-
100
ns
-
-
80
nC
-
-
45
nC
-
-
3
nC
-
975
-
pF
-
330
-
pF
-
95
-
pF
Zero Gate Voltage Drain Current
IDSS
TC = 25oC
TC = 150oC
VDS = 60V
VGS = 0V
Gate to Source Leakage Current
Drain to Source On Resistance
IGSS
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0 to 20V
Gate Charge at 10V
Qg(10)
VGS = 0 to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0 to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to Ambient
RθJA
VDD = 48V, ID = 25A,
RL = 1.92Ω
Ig(REF) = 0.75mA
(Figure 13)
VDS = 25V, VGS = 0V
f = 1MHz
(Figure 12)
-
-
2.083
oC/W
-
-
62
oC/W
MIN
TYP
MAX
UNITS
ISD = 25A
-
-
1.5
V
ISD = 25A, dISD/dt = 100A/µs
-
-
125
ns
(Figure 3)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
©2002 Fairchild Semiconductor Corporation
SYMBOL
VSD
trr
TEST CONDITIONS
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
RFP25N06, RF1S25N06, RF1S25N06SM
Unless Otherwise Specified
1.2
30
1.0
25
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
20
15
10
0.2
5
0
0
50
125
75
100
TC , CASE TEMPERATURE (oC)
25
0
25
175
150
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
50
75
100
125
TC, CASE TEMPERATURE (oC)
150
175
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
0.5
0.2
0.1
0.1
PDM
0.05
t1
t2
0.02
0.01
SINGLE PULSE
0.01
10-5
10-4
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
10-2
10-1
10-3
t1 , RECTANGULAR PULSE DURATION (s)
100
101
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
200
IDM, PEAK CURRENT (A)
ID, DRAIN CURRENT (A)
100
VGS = 20V
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
VGS = 10V
100
100µs
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
10ms
100ms
DC
1
10
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
©2002 Fairchild Semiconductor Corporation
100
175 – T C
I = I 25 ------------------------
150
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10 -5
10
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
TC = 25oC
100
101
FIGURE 5. PEAK CURRENT CAPABILITY
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
RFP25N06, RF1S25N06, RF1S25N06SM
Typical Performance Curves
Unless Otherwise Specified (Continued)
100
VGS = 20V
VGS = 10V
VGS = 8V
60
STARTING TJ = 25oC
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
70
10
STARTING TJ = 150oC
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS-VDD) +1]
1
0.01
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
50
40
VGS = 7V
30
VGS = 6V
20
10
1
0.1
tAV, TIME IN AVALANCHE (µs)
0
10
VGS = 4.5V
VGS = 5V
2
4
6
VDS, DRAIN TO SOURCE VOLTAGE (V)
0
8
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
FIGURE 7. SATURATION CHARACTERISTICS
2.5
70
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
60
ID, DRAIN CURRENT (A)
25oC
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
-55oC
VDD = 15V
50
175oC
40
30
20
10
0
0
2
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
2.0
1.5
1.0
0.5
0
-80
10
FIGURE 8. TRANSFER CHARACTERISTICS
1.0
0.5
200
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2002 Fairchild Semiconductor Corporation
200
ID = 250µA
BREAKDOWN VOLTAGE
NORMALIZED DRAIN TO SOURCE
NORMALIZED GATE
THRESHOLD VOLTAGE
1.5
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
0
40
80
120
160
TJ, JUNCTION TEMPERATURE (oC)
2.0
VGS = VDS
ID = 250µA
-40
-40
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
2.0
0
-80
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 25A
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
RFP25N06, RF1S25N06, RF1S25N06SM
Unless Otherwise Specified (Continued)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
CISS
1200
VDS , DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
10
60
1600
800
COSS
400
CRSS
VDD = BVDSS
VDD = BVDSS
45
7.5
5.0
30
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
15
0
0
I g ( REF )
0
0
5
10
15
20
VDS, DRAIN TO SOURCE VOLTAGE (V)
2.5
RL = 2.4Ω
Ig(REF) = 0.75mA
VGS = 10V
VGS , GATE TO SOURCE VOLTAGE (V)
Typical Performance Curves
20 -------------------I g ( ACT )
25
t, TIME (µs)
I g ( REF )
80 -------------------I g ( ACT )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
+
DUT
RGS
VGS
-
VDD
90%
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
10%
10%
0
10%
50%
50%
PULSE WIDTH
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
RFP25N06, RF1S25N06, RF1S25N06SM
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
Ig(REF)
VGS = 10V
VGS
-
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
FIGURE 19. GATE CHARGE WAVEFORM
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
RFP25N06, RF1S25N06, RF1S25N06SM
PSPICE Electrical Model
.SUBCKT
RFP25N06 2 1 3 ;
rev 8/19/94
CA 12 8 1.83e-9
CB 15 14 1.98e-9
CIN 6 8 9.7e-10
DPLCAP
RSCL1
+ 51
5
ESCL
51
50
ESG
+
IT 8 17 1
GATE
9
1
LGATE
20
EVTO
+ 18
6
8
VTO
-
+
21
6
S1A
S1B
S2A
S2B
MOS2
+
DBODY
-
MOS1
RIN
CIN
8
S1A
12
11
17
EBREAK
18
16
8
RGATE
DBREAK
RDRAIN
MOS1 16 6 8 8 MOSMOD M = 0.99
MOS2 16 21 8 8 MOSMOD M = 0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 50 16 RDSMOD 1.1e-3
RGATE 9 20 2.88
RIN 6 8 1e9
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RDSMOD 20.3e-3
RVTO 18 19 RVTOMOD 1
DRAIN
2
LDRAIN
RSCL2
EBREAK 11 7 17 18 65.9
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
LDRAIN 2 5 1e-9
LGATE 1 9 4.92e-9
LSOURCE 3 7 4.5e-9
5
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBKMOD
DPLCAP 10 5 DPLCAPMOD
RSOURCE
7
LSOURCE
3
SOURCE
S2A
14
13
13
8
S1B
RBREAK
15
17
18
S2B
13
CA
RVTO
CB
+
EGS
-
6
8
+
EDS
-
14
IT
19
VBAT
+
5
8
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.764
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)*1e6/108,6))}
.MODEL DBDMOD D (IS = 2.32e-13 RS = 5.72e-3 TRS1 = 2.56e-3 TRS2 = -5.13e-6 CJO = 1.18e-9 TT = 5.62e-8)
.MODEL DBKMOD D (RS = 2.00e-1 TRS1 = 3.33e-4 TRS2 = 2.68e-6)
.MODEL DPLCAPMOD D (CJO = 6.55e-10 IS = 1e-30 N = 10)
.MODEL MOSMOD NMOS (VTO = 3.89 KP = 15.03 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL RBKMOD RES (TC1 = 1.04e-3 TC2 = -1.04e-6)
.MODEL RDSMOD RES (TC1 = 5.85e-3 TC2 = 1.77e-5)
.MODEL RSCLMOD RES (TC1 = 2.0e-3 TC2 = 1.5e-6)
.MODEL RVTOMOD RES (TC1 = -5.35e-3 TC2 = -3.77e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -5.04 VOFF= -3.04)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.04 VOFF= -5.04)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -3.02 VOFF= 1.98)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 1.98 VOFF= -3.02)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-circuit for the Power MOSFET Featuring Global
Temperature Options; written by William J. Hepp and C. Frank Wheatley.
©2002 Fairchild Semiconductor Corporation
RFP25N06, RF1S25N06, RF1S25N06SM Rev. C
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™
Bottomless™
CoolFET™
CROSSVOLT™
DenseTrench™
DOME™
EcoSPARK™
E2CMOSTM
EnSignaTM
FACT™
FACT Quiet Series™
FAST
FASTr™
FRFET™
GlobalOptoisolator™
GTO™
HiSeC™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
OPTOLOGIC™
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench
QFET™
QS™
QT Optoelectronics™
Quiet Series™
SILENT SWITCHER
SMART START™
STAR*POWER™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET
VCX™
STAR*POWER is used under license
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into
support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose
be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance
support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. H4