RFD16N06LESM
Data Sheet
September 2002
16A, 60V, 0.047 Ohm, Logic Level,
N-Channel Power MOSFETs
Features
• 16A, 60V
These are N-Channel power MOSFETs manufactured using
a modern process. This process, which uses feature sizes
approaching those of LSI integrated circuits gives optimum
utilization of silicon, resulting in outstanding performance.
They were designed for use in applications such as
switching regulators, switching converters, motor drivers,
relay drivers and emitter switches for bipolar transistors. This
performance is accomplished through a special gate oxide
design which provides full rated conductance at gate bias in
the 3V to 5V range, thereby facilitating true on-off power
control directly from logic level (5V) integrated circuits.
Formerly developmental type TA49027.
• rDS(ON) = 0.047Ω
• Temperature Compensating PSPICE® Model
• Can be Driven Directly from CMOS, NMOS, TTL
Circuits
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Ordering Information
PART NUMBER
RFD16N06LESM*
D
PACKAGE
TO-252AA
BRAND
16N06LE
NOTE: When ordering, use the entire part number. Add suffix 9A to
obtain the TO-252AA variant in the tape and reel, i.e.,
RFD16N06LESM9A.
G
S
*RFD16N06LESM is only availabe in tape and reel.
Packaging
JEDEC TO-252AA
DRAIN (FLANGE)
GATE
SOURCE
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
RFD16N06LESM
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
RFD16N06LESM
60
60
+10, -8
16
Refer to Peak Current Curve
Refer to UIS Curve
90
0.606
-55 to 175
UNITS
V
V
V
A
300
260
oC
oC
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V, Figure 11
60
-
-
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA, Figure 10
1
-
3
V
VDS = 55V, VGS = 0V
-
-
1
µA
VDS = 50V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = +10, -8V
-
-
10
µA
ID = 16A, VGS = 5V
-
-
0.047
Ω
VDD = 30V, ID = 16A, RL = 1.88Ω,
VGS = 5V, RGS = 5Ω
Figures 16, 17
-
-
100
ns
-
11
-
ns
tr
-
60
-
ns
td(OFF)
-
48
-
ns
tf
-
35
-
ns
tOFF
-
-
115
ns
-
51
62
nC
-
29
35
nC
Zero Gate Voltage Drain Current
IDSS
Gate to Source Leakage Current
IGSS
Drain to Source On Resistance (Note 2)
rDS(ON)
Turn-On Time
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
-
1.8
2.6
nC
VDS = 25V, VGS = 0V,
f = 1MHz
Figure 12
-
1350
-
pF
-
300
-
pF
Threshold Gate Charge
VDD = 48V,
ID = 16A, RL = 3Ω
Figures 18, 19
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
-
90
-
pF
Thermal Resistance Junction to Case
RθJC
-
-
1.65
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
80
oC/W
MIN
TYP
MAX
UNITS
ISD = 16A
-
-
1.5
V
ISD = 16A, dISD/dt = 100A/µs
-
-
125
ns
TO-251AA, TO-252AA
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage (Note 2)
Diode Reverse Recovery Time
SYMBOL
VSD
trr
TEST CONDITIONS
NOTES:
2. Pulse Test: Pulse Width ≤300µs, Duty Cycle ≤2%.
3. Repetitive Rating: Pulse Width limited by max junction temperature.
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
RFD16N06LESM
Typical Performance Curves
Unless Otherwise Specified
20
POWER DISSIPATION MULTIPLIER
1.2
ID , DRAIN CURRENT (A)
1.0
0.8
0.6
0.4
15
10
5
0.2
0
25
0
0
25
125
50
75
100
TC , CASE TEMPERATURE (oC)
175
150
1ms
10ms
VDSS MAX = 60V
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
IDM , PEAK CURRENT CAPABILITY (A)
ID, DRAIN CURRENT (A)
10
1
150
175
VGS = 10V
I = I25
(
175 - TC
150
)
100
VGS = 5V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
10-6
100
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
TC = 25oC
FIGURE 3. FORWARD BIAS SAFE OPERATING AREA
10-4
10-2
10-3
t, PULSE WIDTH (s)
10-5
10-1
100
101
FIGURE 4. PEAK CURRENT CAPABILITY
100
100
VGS = 10V
TC =25oC
STARTING TJ = 25oC
STARTING TJ = 150oC
ID , DRAIN CURRENT (A)
IAS , AVALANCHE CURRENT (A)
125
500
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
100
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
TC = 25oC
TJ = MAX RATED
100
75
TC , CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
200
50
10
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
VGS = 5V
80
VGS = 4.5V
60
VGS = 4V
40
VGS = 3V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
0
1
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
FIGURE 5. UNCLAMPED INDUCTIVE SWITCHING
©2002 Fairchild Semiconductor Corporation
10
0
1.5
3.0
4.5
6.0
7.5
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 6. SATURATION CHARACTERISTICS
RFD16N06LESM Rev. B1
RFD16N06LESM
Typical Performance Curves
2.5
VDD = 15V
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
80
175oC
25oC
-55oC
60
40
20
0
0
1.5
3.0
4.5
6.0
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = 5V, ID = 16A
1.5
1.0
0.5
0
-80
7.5
-40
FIGURE 7. TRANSFER CHARACTERISTICS
2.0
VGS = VDS, ID = 250µA
1.5
1.0
0.5
0
-80
-40
160
120
0
40
80
TJ , JUNCTION TEMPERATURE (oC)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
COSS
CRSS
0
0
5
10
15
20
160
200
ID = 250µA
1.0
0.5
0
-80
-40
0
40
80
120
160
200
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VDS , DRAIN TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
CISS
500
120
TJ , JUNCTION TEMPERATURE (oC)
2000
1000
80
1.5
200
FIGURE 9. NORMALIZED GATE THRESHOLD VOLTAGE vs
TEMPERATURE
1500
40
FIGURE 8. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
2.0
0
TJ , JUNCTION TEMPERATURE (oC)
VGS , GATE TO SOURCE VOLTAGE (V)
25
VDS , DRAIN TO SOURCE VOLTAGE (V)
5.00
60
VDD = BVDSS
VDD = BVDSS
3.75
45
2.50
30
15
0.75 BVDSS 0.75 BVDSS
0.50 BVDSS 0.50 BVDSS
0.25 BVDSS 0.25 BVDSS
1.25
RL = 3.75Ω
IG(REF) = 0.65mA
VGS = 5V
VGS , GATE TO SOURCE VOLTAGE (V)
ID(ON) , ON STATE DRAIN CURRENT (A)
100
Unless Otherwise Specified (Continued)
0
0
I G ( REF )
20 ---------------------I G ( ACT )
t, TIME (µs)
I G ( REF )
80 ---------------------I G ( ACT )
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
©2002 Fairchild Semiconductor Corporation
FIGURE 12. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
RFD16N06LESM Rev. B1
RFD16N06LESM
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
RG
VDS
IAS
+
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 13. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 14. UNCLAMPED ENERGY WAVEFORMS
tON
VDS
tOFF
td(ON)
RL
VGS
td(OFF)
tr
VDS
tf
90%
90%
+
-
DUT
VDD
10%
10%
RGS
90%
VGS
VGS
10%
FIGURE 15. SWITCHING TIME TEST CIRCUIT
VDS
50%
50%
PULSE WIDTH
FIGURE 16. RESISTIVE SWITCHING WAVEFORMS
VDD
RL
Qg(TOT)
VDS
Qg(10) OR Qg(5)
VGS
+
VDD
VGS
DUT
Ig(REF)
VGS = 2V
0
VGS = 1V FOR
L2 DEVICES
Qg(TH)
VGS = 20V
VGS = 10V FOR
L2 DEVICES
VGS = 10V
VGS = 5V FOR
L2 DEVICES
Ig(REF)
0
FIGURE 17. GATE CHARGE TEST CIRCUIT
©2002 Fairchild Semiconductor Corporation
FIGURE 18. GATE CHARGE WAVEFORMS
RFD16N06LESM Rev. B1
RFD16N06LESM
PSPICE Electrical Model
SUBCKT RFD16N06LESM 2 1 3 ;
rev 8/2/93
CA 12 8 1.46e-9
CB 15 14 1.46e-9
CIN 6 8 1.0e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
IT 8 17 1
EVTEMP
RGATE + 18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 7.0e-3
RGATE 9 20 3.6
RLDRAIN 2 5 10
RLGATE 1 9 55
RLSOURCE 3 7 44
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.45e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
ESG
LDRAIN 2 5 1e-9
LGATE 1 9 5.5e-9
LSOURCE 3 7 4.4e-9
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 66.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*100),3.5))}
.MODEL DBODYMOD D (IS = 6.3e-13 RS = 6.8e-3 TRS1 = 1e-3 TRS2 = 1e-6 XTI = 4.3 CJO = 1.28e-9 TT = 5.1e-8 M = 0.5)
.MODEL DBREAKMOD D (RS = 2.9e-1 TRS1 = 1e-4 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 9.5e-10 IS = 1e-30 N = 10 M = 0.82)
.MODEL MMEDMOD NMOS (VTO = 2.10 KP = 6 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6)
.MODEL MSTROMOD NMOS (VTO = 2.45 KP = 60.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.79 KP = 0.13 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 36 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.2e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 1.3e-2 TC2 = 3.1e-5)
.MODEL RSLCMOD RES (TC1 = 5.5e-3 TC2 = 7e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.8e-3 TC2 = -5.8e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 8e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.8 VOFF= -2.8)
VON = -2.8 VOFF= -4.8)
VON = -0.6 VOFF= 0.5)
VON = 0.5 VOFF= -0.6)
.ENDS
For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2002 Fairchild Semiconductor Corporation
RFD16N06LESM Rev. B1
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not
intended to be an exhaustive list of all such trademarks.
FACT™
ACEx™
FACT Quiet Series™
ActiveArray™
FAST®
Bottomless™
FASTr™
CoolFET™
CROSSVOLT™ FRFET™
GlobalOptoisolator™
DOME™
GTO™
EcoSPARK™
HiSeC™
E2CMOS™
EnSigna™
I2C™
Across the board. Around the world.™
The Power Franchise™
Programmable Active Droop™
ImpliedDisconnect™
ISOPLANAR™
LittleFET™
MicroFET™
MicroPak™
MICROWIRE™
MSX™
MSXPro™
OCX™
OCXPro™
OPTOLOGIC®
OPTOPLANAR™
PACMAN™
POP™
Power247™
PowerTrench®
QFET™
QS™
QT Optoelectronics™
Quiet Series™
RapidConfigure™
RapidConnect™
SILENT SWITCHER®
SMART START™
SPM™
Stealth™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SyncFET™
TinyLogic™
TruTranslation™
UHC™
UltraFET®
VCX™
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY
LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;
NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR
CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body,
or (b) support or sustain life, or (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In
Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I1