CY62157DV18 MoBL2 8M (512K x 16) Static RAM Features • • • • • • • • • power consumption by more than 99% when deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW or both BHE and BLE are HIGH. The input/output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable 2 (CE2) LOW, outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or during a write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and WE LOW). Very high speed: 55 ns and 70 ns Voltage range: 1.65V to 1.95V Pin compatible with CY62157CV18 Ultra-low active power — Typical active current: 1 mA @ f = 1 MHz — Typical active current: 10 mA @ f = fMAX Ultra-low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered in a 48-ball FBGA Writing to the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A18). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A18). Functional Description[1] The CY62157DV18 is a high-performance CMOS static RAM organized as 512K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can be put into standby mode reducing Reading from the device is accomplished by taking Chip Enable 1 (CE1) LOW and Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. Logic Block Diagram 512K x 16 RAM ARRAY 2048 x 256 x 16 SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS I/O0–I/O7 I/O8–I/O15 BHE WE A13 A14 A15 A16 A17 A18 A11 A12 COLUMN DECODER CE 2 CE 1 OE BLE Power - down Circuit CE 2 BHE BLE CE 1 Note: 1. For best practice recommendations, please refer to the Cypress application note System Design Guidelines on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05126 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised March 17, 2003 CY62157DV18 MoBL2 Pin Configuration[2, 3] FBGA T op View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE 2 A I/O8 B HE A3 A4 CE 1 I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 I/O3 Vccq D VCC I/O12 DNU A16 I/O4 Vss q E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 NC A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H Notes: 2. NC pins are not connected to the die. 3. DNU pins are to be connected to VSS or left open. Document #: 38-05126 Rev. *B Page 2 of 10 CY62157DV18 MoBL2 Maximum Ratings DC Input Voltage[4] ................................ –0.2V to VCC + 0.2V (Above which the useful life may be impaired. For user guidelines, not tested.) Output Current into Outputs (LOW)............................. 20 mA Storage Temperature ................................. –65°C to +150°C Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Ambient Temperature with Power Applied............................................. –55°C to +125°C Latch-up Current .................................................... > 200 mA Supply Voltage to Ground Potential ......................... –0.2V to VCCMAX + 0.2V Operating Range DC Voltage Applied to Outputs in High-Z State[4] ....................................–0.2V to VCC + 0.2V Range Ambient Temperature (TA) VCC Industrial –40°C to +85°C 1.65V to 1.95V Product Portfolio Power Dissipation Operating, Icc (mA) VCC Range(V) Max. Speed (ns) Typ.[5] 1.8 1.95 55 1.8 1.95 55 Min. Typ.[5] CY62157DV18L 1.65 CY62157DV18LL 1.65 Product f = 1 MHz f = fMAX Standby, ISB2 (µA) Max. Typ.[5] Max. Typ.[5] Max. 1 5 10 20 2 20 8 15 2 20 1 5 10 20 2 5 8 15 2 5 70 70 DC Electrical Characteristics (Over the Operating Range) CY62157DV18-55 Parameter Description Test Conditions Min. Typ.[5] Max. CY62157DV18-70 Typ.[5] Min. Max. Unit VOH Output HIGH Voltage IOH = −0.1 mA VCC = 1.65V VOL Output LOW Voltage IOL = 0.1 mA VCC = 1.65V 0.2 V VIH Input HIGH Voltage 1.4 VCC + 0.2 1.4 VCC + 0.2 V VIL Input LOW Voltage –0.2 0.4 –0.2 0.4 V IIX Input Leakage Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current –1 +1 –1 +1 µA ICC VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz mA ISB1 ISB2 GND < VO < VCC, Output Disabled Vcc = 1.95V, IOUT = 0 mA, CMOS level 1.4 1.4 V 0.2 10 20 8 15 1 5 1 5 Automatic CE CE1 > VCC − 0.2V, CE2 < L Power-down Current – 0.2V, VIN > VCC − 0.2V, VIN LL < 0.2V, f = fMAX (Address CMOS Inputs and Data Only), f = 0 (OE, WE, BHE and BLE) 2 20 2 20 2 5 2 5 Automatic CE CE1 > VCC − 0.2V, CE2 < L Power-down Current – 0.2V, VIN > VCC − 0.2V or LL VIN < 0.2V, f = 0, VCC = CMOS Inputs 1.95V 2 20 2 20 2 5 2 5 µA µA Capacitance[6] Parameter Description CIN Input Capacitance Test Conditions TA = 25°C, f = 1 MHz VCC = VCC(typ) Max. Unit 6 pF COUT Output Capacitance 8 Notes: 4. VIL(min.) = –2.0V for pulse durations less than 20 ns. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. 6. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05126 Rev. *B pF Page 3 of 10 CY62157DV18 MoBL2 Thermal Resistance Parameter Description θJA Thermal Resistance (Junction to Ambient)[6] θJC Thermal Resistance (Junction to Case)[6] Test Conditions BGA Unit Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board 55 C/W 16 C/W AC Test Loads and Waveforms R1 ALL INPUT PULSES VCC VCC Typ OUTPUT 10% 90% 10% 90% GND R2 CL = 30 pF Rise Time: 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: Fall Time: 1 V/ns THÉVENIN EQUIVALENT OUTPUT RTH V Parameters 1.8V UNIT R1 13500 Ω R2 10800 Ω R TH 6000 Ω VT H 0.80 V Data Retention Characteristics Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current Min. Typ.[5] 1.0 tCDR[6] Chip Deselect to Data Retention Time tR[7] Operation Recovery Time VCC = 1.0V, CE1 > VCC – 0.2V, CE2 L < 0.2V, VIN > VCC − 0.2V or VIN < LL 0.2V 1 Max. Unit 1.95 V 10 µA 3 0 ns tRC ns Data Retention Waveform[8] VCC VCC(min.) tCDR DATA RETENTION MODE VDR > 1.0V VCC(min.) tR CE1 or BHE . BLE or CE2 Notes: 7. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 100 µs or stable at VCC(min.) > 100 µs. . 8. BHE BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05126 Rev. *B Page 4 of 10 CY62157DV18 MoBL2 Switching Characteristics (Over the Operating Range)[9] Parameter Description CY62157DV18-55 CY62157DV18-70 Min. Min. Max. Max. Unit Read Cycle tRC Read Cycle Time 55 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW or CE2 HIGH to Data Valid 55 70 ns tDOE OE LOW to Data Valid 25 35 ns tLZOE OE LOW to Low Z[10] tHZOE OE HIGH to High Z[10, 12] 55 10 CE1 LOW or CE2 HIGH to Low Z tHZCE CE1 HIGH or CE2 LOW to High Z[10, 12] tPU CE1 LOW or CE2 HIGH to Power-up tPD CE1 HIGH or CE2 LOW to Power-down tDBE BLE/BHE LOW to Data Valid tLZBE[11] BLE/BHE LOW to Low Z[10] BLE/BHE HIGH to High-Z 70 10 ns ns 25 ns 70 ns 70 ns ns 0 ns 55 55 5 [10, 12] 25 10 20 0 ns ns 5 20 [10] ns 10 5 tLZCE tHZBE 70 5 ns 20 25 ns Write Cycle[13] tWC Write Cycle Time 55 70 ns tSCE CE1 LOW or CE2 HIGH to Write End 45 60 ns tAW Address Set-up to Write End 45 60 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-up to Write Start 0 0 ns tPWE WE Pulse Width 45 50 ns tBW BLE/BHE LOW to Write End 45 60 ns tSD Data Set-up to Write End 25 30 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High Z[10, 12] tLZWE WE HIGH to Low Z[10] 0 ns 20 10 25 10 ns ns Switching Waveforms Read Cycle No. 1 (Address Transition Controlled)[14, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Notes: 9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL. 10. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than t. 11. If both byte enables are toggled together, this value is 10 ns. 12. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 13. The internal Write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE and/or BLE = VIL. 14. Device is continuously selected. OE, CE1 = VIL, BHE and/or BLE = VIL, CE2 = VIH. 15. WE is HIGH for Read cycle. Document #: 38-05126 Rev. *B Page 5 of 10 CY62157DV18 MoBL2 Switching Waveforms (continued) Read Cycle No. 2 (OE Controlled)[15, 16] ADDRESS t RC CE 1 t PD t HZCE CE2 tACE BHE /BLE t DBE t HZBE t LZBE OE t HZOE t DOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID t LZCE tPU VCC SUPPLY CURRENT 50% 50% I CC I SB Write Cycle No. 1 (WE Controlled) [13, 17, 18, 19] t WC ADDRESS tSCE CE1 CE2 tAW t HA t SA t PWE WE tBW BHE /BLE OE tSD DATA I/O t HD DATAIN VALID DON’T CARE t HZOE Notes: 16. Address valid prior to or coincident with CE1, BHE, BLE transition LOW and CE2 transition HIGH. 17. Data I/O is high-impedance if OE = VIH. 18. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 19. During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Document #: 38-05126 Rev. *B Page 6 of 10 CY62157DV18 MoBL2 Switching Waveforms (continued) Write Cycle No. 2 (CE1 or CE2 Controlled) [13, 17, 18, 19] t WC ADDRESS t SCE CE 1 CE 2 t SA t AW t HA t PWE WE t BW BHE /BLE OE t SD DATA I/O t HD DATA IN VALID DON’T CARE t HZOE Write Cycle No. 3 (WE Controlled, OE LOW)[18, 19] tWC ADDRESS tSCE CE1 CE2 tAW tSA tHA tPWE WE tSD DATA I/O DATAIN VALID DON’T CARE tHZWE Document #: 38-05126 Rev. *B tHD tLZWE Page 7 of 10 CY62157DV18 MoBL2 Switching Waveforms (continued) Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)[19] t WC ADDRESS CE 1 CE 2 t SCE t AW t HA t BW BHE /BLE t SA t PWE WE t SD DATA I/O t HD DATAIN VALID DON’T CARE Truth Table CE 1 CE 2 WE OE BHE BLE Input / Outputs Mode Power H X X X X X High Z Deselect/Power-down Standby(I SB ) X L X X X X High Z Deselect/Power-down Standby(I SB ) X X X X H H High Z Deselect/Power-down Standby(I SB ) L H H L L L Data Out(I/O0– I/O15) Read Active(I CC) L H H L H L Data Out(I/O0– I/O7); High Z (I/O8– I/O15) Read Active(I CC) L H H L L H High Z (I/O0– I/O7); Data Out(I/O8– I/O15) Read Active(I CC) L H H H L H High Z Output Disabled Active(I CC) L H H H H L High Z Output Disabled Active(I CC) L H H H L L High Z Output Disabled Active(I CC) L H L X L L Data In (I/O0– I/O15) Write Active(I CC) L H L X H L Data In (I/O0– I/O7); High Z (I/O8– I/O15) Write Active(I CC) L H L X L H High Z (I/O0– I/O7); Data In (I/O8– I/O15) Write Active(I CC) Ordering Information Speed (ns) Ordering Code Package Name 55 CY62157DV18L-55BVI CY62157DV18LL-55BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 70 CY62157DV18L-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) CY62157DV18LL-70BVI BV48A 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Document #: 38-05126 Rev. *B BV48A Package Type 48-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial Industrial Page 8 of 10 CY62157DV18 MoBL2 Package Diagrams 48-Lead VFBGA (6 x 8 x 1 mm) BV48A 51-85150-*B MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05126 Rev. *B Page 9 of 10 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY62157DV18 MoBL2 Document History Page Document Title: CY62157DV18 MoBL2 8M (512K x 16) Static RAM Document Number: 38-05126 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 112603 03/01/02 GAV New Data Sheet, Die rev replacing CY62157CV18 *A 116601 06/14/02 MGN Added second power bin (L and LL) Changed from Advance Information to Preliminary *B 124694 03/18/03 DPM Changed Preliminary to Final Added LL Bin to Iccdr = 3 uA max Added new footnotes (1 and 2) Filled in TBD values Document #: 38-05126 Rev. *B Page 10 of 10