TI TAS5707

TAS5707
www.ti.com........................................................................................................................................................................................... SLOS556 – NOVEMBER 2008
20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC
FEATURES
1
•
•
•
•
Audio Input/Output
– 20-W Into an 8-Ω Load From an 18-V Supply
– Wide PVDD Range, From 8 V to 24 V
– Efficient Class-D Operation Eliminates
Need for Heatsinks
– Requires Only 3.3 V and PVDD
– One Serial Audio Input (Two Audio
Channels)
– Supports 8-kHz to 48-kHz Sample Rate
(LJ/RJ/I2S)
Audio/PWM Processing
– Independent Channel Volume Controls With
24-dB to Mute
– Soft Mute (50% Duty Cycle)
– Programmable Dynamic Range Control
– 14 Programmable Biquads for Speaker EQ
and Other Audio Processing Features
– Programmable Coefficients for DRC Filters
– DC Blocking Filters
General Features
– Serial Control Interface Operational Without
MCLK
– Factory-Trimmed Internal Oscillator for
automatic rate detection
– Surface Mount, 48-PIN, 7-mm × 7-mm
HTQFP Package
– Thermal and Short-Circuit Protection
Benefits
– EQ: Speaker Equalization Improves Audio
Performance
– DRC: Dynamic Range Compression. Can
Be Used As Power Limiter. Enables
Speaker Protection, Easy Listening,
Night-Mode Listening.
– Autobank Switching: Preload Coefficients
for Different Sample Rates. No Need to
Write new Coefficients to the Part When
Sample Rate Changes.
– Autodetect: Automatically Detects
Sample-Rate Changes. No Need for
External Microprocessor Intervention
DESCRIPTION
The TAS5707 is a 20-W, efficient, digital audio power
amplifier for driving stereo bridge-tied speakers. One
serial data input allows processing of up to two
discrete audio channels and seamless integration to
most digital audio processors and MPEG decoders.
The device accepts a wide range of input data and
data rates. A fully programmable data path routes
these channels to the internal speaker drivers.
The TAS5707 is a slave-only device receiving all
clocks from external sources. The TAS5707 operates
with a PWM carrier between 384-kHz switching rate
and 352-KHz switching rate depending on the input
sample rate. Oversampling combined with a
fourth-order noise shaper provides a flat noise floor
and excellent dynamic range from 20 Hz to 20 kHz.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
TAS5707
SLOS556 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
SIMPLIFIED APPLICATION DIAGRAM
3.3 V
8 V–24 V
AVDD/DVDD
PVDD
OUT_A
LRCLK
Digital
Audio
Source
SCLK
BST_A
MCLK
LC
Left
LC
Right
BST_B
SDIN
OUT_B
2
I C
Control
SDA
OUT_C
SCL
BST_C
Control
Inputs
RESET
BST_D
PDN
OUT_D
PLL_FLTP
Loop
Filter*
PLL_FLTM
B0264-03
*Refer to user's guide for Loop Filter details.
2
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FUNCTIONAL VIEW
L
SDIN
OUT_A
7 BQ
V
O
L
U
M
E
Serial
Audio
Port
R
7 BQ
th
DRC
S
R
C
4
Order
Noise
Shaper
and
PWM
2´ HB
FET Out
OUT_B
OUT_C
2´ HB
FET Out
OUT_D
mDAP
Protection
Logic
MCLK
SCLK
LRCLK
SDA
SCL
Click and Pop
Control
Sample Rate
Autodetect
and PLL
Serial
Control
Microcontroller
Based
System
Control
Terminal Control
B0262-02
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FAULT
Undervoltage
Protection
FAULT
4
4
Power
On
Reset
Protection
and
I/O Logic
AGND
Temp.
Sense
GND
VALID
Overcurrent
Protection
Isense
OC_ADJ
BST_D
PVDD_D
PWM Controller
PWM_D
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_D
Pulldown Resistor
PGND_CD
GVDD_CD
Regulator
GVDD_CD
BST_C
PVDD_C
PWM_C
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_C
Pulldown Resistor
PGND_CD
BST_B
PVDD_B
PWM_B
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_B
Pulldown Resistor
GVDD_AB
Regulator
PGND_AB
GVDD_AB
BST_A
PVDD_A
PWM_A
PWM
Rcv
Ctrl
Timing
Gate
Drive
OUT_A
Pulldown Resistor
PGND_AB
B0034-05
Figure 1. Power Stage Functional Block Diagram
4
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B0341-01
DAP Process Structure
46[D0]
DRC
ON/ OFF
Attack
DRC1 Decay
Vol2
30-36
R
50[D7]
7 BQ EQ
´
ealpha
3A
3A
ealpha
29-2F
´
Vol1
7 BQ EQ
L
Hex numbers refer to I2C subaddresses
[Di] = bit "i" of subaddress
3B-3C 1
´
´
To PWM
Energy
MAXMUX
Input Muxing
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48-TERMINAL, HTQFP PACKAGE (TOP VIEW)
PGND_CD
PGND_CD
PVDD_C
OUT_C
PVDD_C
BST_C
PVDD_B
BST_B
PVDD_B
OUT_B
PGND_AB
PGND_AB
PHP Package
(Top View)
48 47 46 45 44 43 42 41 40 39 38 37
OUT_A
1
36
OUT_D
PVDD_A
2
35
PVDD_D
PVDD_A
3
34
PVDD_D
BST_A
4
33
BST_D
GVDD_OUT
5
32
GVDD_OUT
SSTIMER
6
31
VREG
OC_ADJ
7
30
AGND
NC
8
29
GND
AVSS
9
28
DVSS
PLL_FLTM
10
27
DVDD
PLL_FLTP
11
26
STEST
VR_ANA
12
25
RESET
TAS5707
SCL
SDA
SDIN
SCLK
LRCLK
PDN
VR_DIG
DVSSO
OSC_RES
FAULT
MCLK
AVDD
13 14 15 16 17 18 19 20 21 22 23 24
P0075-01
PIN FUNCTIONS
PIN
NAME
TYPE
NO.
(1)
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
AGND
30
P
Analog ground for power stage
AVDD
13
P
3.3-V analog power supply
AVSS
9
P
Analog 3.3-V supply ground
BST_A
4
P
High-side bootstrap supply for half-bridge A
BST_B
43
P
High-side bootstrap supply for half-bridge B
BST_C
42
P
High-side bootstrap supply for half-bridge C
BST_D
33
P
High-side bootstrap supply for half-bridge D
DVDD
27
P
3.3-V digital power supply
DVSSO
17
P
Oscillator ground
DVSS
28
P
Digital ground
GND
29
P
Analog ground for power stage
GVDD_OUT
5, 32
P
LRCLK
20
DI
5-V
Pulldown
Input serial audio data left/right clock (sample rate clock)
MCLK
15
DI
5-V
Pulldown
Master clock input
(1)
(2)
6
Gate drive internal regulator output
TYPE: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
All pullups are weak pullups and all pulldowns are weak pulldowns. The pullups and pulldowns are included to assure proper input logic
levels if the pins are left unconnected (pullups → logic 1 input; pulldowns → logic 0 input).
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PIN FUNCTIONS (continued)
PIN
NAME
TYPE
NO.
(1)
5-V
TOLERANT
TERMINATION
DESCRIPTION
(2)
NC
8
–
OC_ADJ
7
AO
No connection
Analog overcurrent programming. Requires resistor to ground.
OSC_RES
16
AO
Oscillator trim resistor. Connect an 18.2-kΩ 1% resistor to DVSSO.
OUT_A
1
O
Output, half-bridge A
OUT_B
46
O
Output, half-bridge B
OUT_C
39
O
Output, half-bridge C
OUT_D
36
O
PDN
19
DI
PGND_AB
47, 48
P
Power ground for half-bridges A and B
PGND_CD
37, 38
P
Power ground for half-bridges C and D
PLL_FLTM
10
AO
PLL negative loop filter terminal
PLL_FLTP
11
AO
PLL positive loop filter terminal
PVDD_A
2, 3
P
Power supply input for half-bridge output A
PVDD_B
44, 45
P
Power supply input for half-bridge output B
PVDD_C
40, 41
P
Power supply input for half-bridge output C
PVDD_D
34, 35
P
RESET
25
DI
5-V
SCL
24
DI
5-V
SCLK
21
DI
5-V
SDA
23
DIO
5-V
SDIN
22
DI
5-V
SSTIMER
6
AI
Controls ramp time of OUT_X to minimize pop. Leave this pin floating
for BD mode. Requires capacitor of 2.2 nF to GND in AD mode. The
capacitor determines the ramp time.
STEST
26
DI
Factory test pin. Connect directly to DVSS.
FAULT
14
DO
Backend error indicator. Asserted LOW for over temperature, over
current, over voltage, and under voltage error conditions. De-asserted
upon recovery from error condition.
VR_ANA
12
P
Internally regulated 1.8-V analog supply voltage. This pin must not be
used to power external devices.
VR_DIG
18
P
Internally regulated 1.8-V digital supply voltage. This pin must not be
used to power external devices.
VREG
31
P
Digital regulator output. Not to be used for powering external circuitry.
Output, half-bridge D
5-V
Pullup
Power down, active-low. PDN prepares the device for loss of power
supplies by shutting down the Noise Shaper and initiating PWM stop
sequence.
Power supply input for half-bridge output D
Pullup
Reset, active-low. A system reset is generated by applying a logic low
to this pin. RESET is an asynchronous control signal that restores the
DAP to its default conditions, and places the PWM in the hard mute
state (tristated).
I2C serial control clock input
Pulldown
Serial audio data clock (shift clock). SCLK is the serial audio port input
data bit clock.
I2C serial control data interface input/output
Pulldown
Serial audio data input. SDIN supports three discrete (stereo) data
formats.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Supply voltage
(1)
VALUE
UNIT
DVDD, AVDD
–0.3 to 3.6
V
PVDD_X
–0.3 to 30
V
OC_ADJ
3.3-V digital input
Input voltage
5-V tolerant (2) digital input (except MCLK)
5-V tolerant MCLK input
–0.3 to 4.2
V
–0.5 to DVDD + 0.5
V
–0.5 to DVDD + 2.5 (3)
V
(3)
V
–0.5 to AVDD + 2.5
OUT_x to PGND_X
32 (4)
V
BST_x to PGND_X
43 (4)
V
Input clamp current, IIK
±20
mA
Output clamp current, IOK
±20
mA
Operating free-air temperature
0 to 85
°C
Operating junction temperature range
0 to 150
°C
–40 to 125
°C
Storage temperature range, Tstg
(1)
Stresses beyond those listed under absolute ratings may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are
not implied. Exposure to absolute-maximum conditions for extended periods may affect device reliability.
5-V tolerant inputs are PDN, RESET, SCLK, LRCLK, MCLK, SDIN, SDA, and SCL.
Maximum pin voltage should not exceed 6.0Vele
DC voltage + peak ac waveform measured at the pin should be below the allowed limit for all conditions.
(2)
(3)
(4)
DISSIPATION RATINGS (1)
PACKAGE
DERATING FACTOR
ABOVE TA = 25°C
TA ≤ 25°C
POWER RATING
TA = 45°C
POWER RATING
TA = 70°C
POWER RATING
7-mm × 7-mm HTQFP
40 mW/°C
5W
4.2 W
3.2 W
(1)
This data was taken using 1 oz trace and copper pad that is soldered directly to a JEDEC standard high-k PCB. The thermal pad must
be soldered to a thermal land on the printed-circuit board. See TI Technical Briefs SLMA002 for more information about using the
HTQFP thermal pad
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
Digital/analog supply voltage
DVDD, AVDD
3
3.3
3.6
V
Half-bridge supply voltage
PVDD_X
8
24
V
VIH
High-level input voltage
5-V tolerant
2
VIL
Low-level input voltage
5-V tolerant
TA
Operating ambient temperature range
Operating junction temperature range
TJ
(1)
RL (BTL)
LO (BTL)
(1)
Load impedance
Output filter: L = 15 µH, C = 680 nF.
Output-filter inductance
Minimum output inductance under
short-circuit condition
UNIT
V
0.8
V
0
85
°C
0
125
°C
6
Ω
8
10
µH
Continuous operation above the recommended junction temperature may result in reduced reliability and/or lifetime of the device.
PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS
PARAMETER
Output sample rate
8
VALUE
UNIT
11.025/22.05/44.1-kHz data rate ±2%
TEST CONDITIONS
352.8
kHz
48/24/12/8/16/32-kHz data rate ±2%
384
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PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS
PARAMETER
fMCLKI
tr /
tf(MCLK)
TEST CONDITIONS
MIN
MCLK Frequency
2.8224
MCLK duty cycle
40%
TYP
50%
Rise/fall time for MCLK
LRCLK allowable drift before LRCLK reset
External PLL filter capacitor C1
SMD 0603 Y5V
External PLL filter capacitor C2
External PLL filter resistor R
MAX
UNIT
24.576
MHz
60%
5
ns
4
MCLKs
47
nF
SMD 0603 Y5V
4.7
nF
SMD 0603, metal film
470
Ω
ELECTRICAL CHARACTERISTICS
DC Characteristics
TA = 25°, PVCC_X = 18V, DVDD = AVDD = 3.3V, RL= 8Ω, BTL AD Mode, FS = 48KHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VOH
High-level output voltage
FAULTZ and SDA
IOH = –4 mA
DVDD = 3 V
VOL
Low-level output voltage
FAULTZ and SDA
IOL = 4 mA
DVDD = 3 V
0.5
V
IIL
Low-level input current
VI < VIL ; DVDD = AVDD
= 3.6V
75
µA
IIH
High-level input current
VI > VIH ; DVDD =
AVDD = 3.6V
75
µA
IDD
3.3 V supply current
3.3 V supply voltage (DVDD,
AVDD)
IPVDD
Half-bridge supply current
No load (PVDD_X)
rDS(on) (1)
2.4
UNIT
V
Normal Mode
48
83
Reset (RESET = low,
PDN = high)
24
32
Normal Mode
30
55
5
13
Reset (RESET = low,
PDN = high)
Drain-to-source resistance, LS TJ = 25°C, includes metallization resistance
180
Drain-to-source resistance,
HS
TJ = 25°C, includes metallization resistance
180
mA
mA
mΩ
I/O Protection
Vuvp
Undervoltage protection limit
PVDD falling
7.2
Vuvp,hyst
Undervoltage protection limit
PVDD rising
7.6
V
OTE (2)
Overtemperature error
150
°C
OTEHYST (2)
Extra temperature drop
required to recover from error
30
°C
OLPC
Overload protection counter
fPWM = 384 kHz
1.25
ms
IOC
Overcurrent limit protection
Resistor—programmable, max. current, ROCP = 22 kΩ
IOCT
Overcurrent response time
ROCP
OC programming resistor
range
Resistor tolerance = 5% for typical value; the minimum
resistance should not be less than 20 kΩ.
RPD
Internal pulldown resistor at
the output of each half-bridge
Connected when drivers are tristated to provide bootstrap
capacitor charge.
(1)
(2)
20
V
4.5
A
150
ns
22
kΩ
3
kΩ
This does not include bond-wire or pin resistance.
Specified by design
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AC Characteristics (BTL)
PVDD_X = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter,
fPWM = 384 kHz, TA = 25°C (unless otherwise noted). All performance is in accordance with recommended operating
conditions, unless otherwise specified.
PARAMETER
PO
Power output per channel
THD+N
Vn
Total harmonic distortion + noise
Output integrated noise (rms)
Crosstalk
SNR
(1)
10
Signal-to-noise ratio
(1)
TEST CONDITIONS
MIN
TYP
PVDD = 18 V,10% THD, 1-kHz input signal
20.6
PVDD = 18 V, 7% THD, 1-kHz input signal
19.5
PVDD = 12 V, 10% THD, 1-kHz input
signal
9.4
PVDD = 12 V, 7% THD, 1-kHz input signal
8.9
PVDD = 8 V, 10% THD, 1-kHz input signal
4.1
PVDD = 8 V, 7% THD, 1-kHz input signal
3.8
PVDD= 18 V; PO = 1 W
0.06%
PVDD= 12 V; PO = 1 W
0.13%
PVDD= 8 V; PO = 1 W
0.2%
MAX
UNIT
W
56
µV
PO = 0.25 W, f = 1kHz (BD Mode)
–82
dB
PO = 0.25 W, f = 1kHz (AD Mode)
-69
dB
A-weighted, f = 1 kHz, maximum power at
THD < 1%
106
dB
A-weighted
SNR is calculated relative to 0-dBFS input level.
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SERIAL AUDIO PORTS SLAVE MODE
over recommended operating conditions (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
MIN
CL = 30 pF
TYP
1.024
MAX
UNIT
12.288
MHz
fSCLKIN
Frequency, SCLK 32 × fS, 48 × fS, 64 × fS
tsu1
Setup time, LRCLK to SCLK rising edge
10
ns
th1
Hold time, LRCLK from SCLK rising edge
10
ns
tsu2
Setup time, SDIN to SCLK rising edge
10
ns
th2
Hold time, SDIN from SCLK rising edge
10
LRCLK frequency
ns
8
48
48
SCLK duty cycle
40%
50%
60%
LRCLK duty cycle
40%
50%
60%
SCLK rising edges between LRCLK rising edges
t(edge)
LRCLK clock edge with respect to the falling edge of SCLK
tr /
tf(SCLK/LRCLK)
Rise/fall time for SCLK/LRCLK
kHz
32
64
SCLK
edges
–1/4
1/4
SCLK
period
8
tr
ns
tf
SCLK
(Input)
t(edge)
th1
tsu1
LRCLK
(Input)
th2
tsu2
SDIN
T0026-04
Figure 2. Slave Mode Serial Data Interface Timing
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I2C SERIAL CONTROL PORT OPERATION
Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
No wait states
MAX
UNIT
400
kHz
fSCL
Frequency, SCL
tw(H)
Pulse duration, SCL high
0.6
tw(L)
Pulse duration, SCL low
1.3
tr
Rise time, SCL and SDA
300
ns
tf
Fall time, SCL and SDA
300
ns
tsu1
Setup time, SDA to SCL
th1
Hold time, SCL to SDA
t(buf)
µs
µs
100
ns
0
ns
Bus free time between stop and start condition
1.3
µs
tsu2
Setup time, SCL to start condition
0.6
µs
th2
Hold time, start condition to SCL
0.6
µs
tsu3
Setup time, SCL to stop condition
0.6
CL
Load capacitance for each bus line
µs
400
tw(H)
tw(L)
pF
tf
tr
SCL
tsu1
th1
SDA
T0027-01
Figure 3. SCL and SDA Timing
SCL
t(buf)
th2
tsu2
tsu3
SDA
Start
Condition
Stop
Condition
T0028-01
Figure 4. Start and Stop Conditions Timing
12
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RESET TIMING (RESET)
Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended
Use Model section on usage of all terminals.
PARAMETER
tw(RESET)
Pulse duration, RESET active
td(I2C_ready)
Time to enable I2C
MIN
TYP
MAX
UNIT
13.5
ms
100
us
RESET
tw(RESET)
2
2
I C Active
I C Active
td(I2C_ready)
System Initialization.
2
Enable via I C.
T0421-01
NOTE: On power up, it is recommended that the TAS5707 RESET be held LOW for at least 100 µs after DVDD has reached
3.0 V
NOTE: If the RESET is asserted LOW while PDN is LOW, then the RESET must continue to be held LOW for at least 100 µs
after PDN is deasserted (HIGH).
Figure 5. Reset Timing
TYPICAL CHARACTERISTICS, BTL CONFIGURATION
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PVDD = 18 V
RL = 8 Ω
1
P=5W
0.1
P=1W
0.01
0.001
20
100
1k
10k 20k
PVDD = 12 V
RL = 8 Ω
1
P = 2.5 W
0.1
0.01
0.001
20
f − Frequency − Hz
P = 0.5 W
100
1k
10k 20k
f − Frequency − Hz
G001
Figure 6.
G002
Figure 7.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
TOTAL HARMONIC DISTORTION + NOISE
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
10
PVDD = 8 V
RL = 8 Ω
P = 2.5 W
1
0.1
P = 0.5 W
P=1W
0.01
0.001
20
100
1k
PVDD = 18 V
RL = 8 Ω
1
f = 1 kHz
0.1
f = 20 Hz
0.01
f = 10 kHz
0.001
0.01
10k 20k
0.1
f − Frequency − Hz
G003
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE
vs
OUTPUT POWER
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
40
G004
Figure 9.
PVDD = 12 V
RL = 8 Ω
1
f = 1 kHz
0.1
f = 20 Hz
0.01
f = 10 kHz
0.1
1
PO − Output Power − W
10
40
PVDD = 8 V
RL = 8 Ω
1
f = 1 kHz
0.1
f = 20 Hz
0.01
0.001
0.01
G005
Figure 10.
14
10
Figure 8.
10
0.001
0.01
1
PO − Output Power − W
f = 10 kHz
0.1
1
PO − Output Power − W
10
40
G006
Figure 11.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
OUTPUT POWER
vs
SUPPLY VOLTAGE
EFFICIENCY
vs
OUTPUT POWER
20
100
RL = 8 Ω
18
90
80
PVDD = 18 V
14
PVDD = 12 V
70
THD+N = 10%
Efficiency − %
PO − Output Power − W
16
12
10
THD+N = 1%
8
PVDD = 8 V
60
50
40
30
6
20
4
10
2
RL = 8 Ω
0
8
9
10
11
12
13
14
15
16
17
18
0
4
PVDD − Supply Voltage − V
G010
−20
16
20
24
Figure 13.
CROSSTALK
vs
FREQUENCY
CROSSTALK
vs
FREQUENCY
28
32
36
40
G012
0
PO = 0.25 W
PVDD = 18 V
RL = 8 Ω
−10
−20
PO = 0.25 W
PVDD = 12 V
RL = 8 Ω
−30
Crosstalk − dB
−30
Crosstalk − dB
12
Figure 12.
0
−10
8
PO − Output Power (Per Channel) − W
−40
−50
−60
Right to Left
−70
−40
−50
−60
Right to Left
−70
−80
−80
Left to Right
Left to Right
−90
−100
20
−90
100
1k
10k 20k
−100
20
f − Frequency − Hz
100
1k
10k 20k
f − Frequency − Hz
G013
Figure 14.
G014
Figure 15.
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TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued)
CROSSTALK
vs
FREQUENCY
0
−10
−20
PO = 0.25 W
PVDD = 8 V
RL = 8 Ω
Crosstalk − dB
−30
−40
−50
−60
Right to Left
−70
−80
Left to Right
−90
−100
20
100
1k
10k 20k
f − Frequency − Hz
G015
Figure 16.
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DETAILED DESCRIPTION
POWER SUPPLY
To facilitate system design, the TAS5707 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage
supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all
circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap
circuitry requiring only a few external capacitors.
In order to provide good electrical and acoustical characteristics, the PWM signal path for the output stage is
designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins
(BST_X), and power-stage supply pins (PVDD_X). The gate drive voltages (GVDD_AB and GVDD_CD) are
derived from the PVDD voltage. Special attention should be paid to placing all decoupling capacitors as close to
their associated pins as possible. In general, inductance between the power-supply pins and decoupling
capacitors must be avoided.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin
(BST_X) to the power-stage output pin (OUT_X). When the power-stage output is low, the bootstrap capacitor is
charged through an internal diode connected between the gate-drive regulator output pin (GVDD_X) and the
bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output
potential and thus provides a suitable voltage supply for the high-side gate driver. In an application with PWM
switching frequencies in the range from 352 kHz to 384 kHz, it is recommended to use 33-nF ceramic capacitors,
size 0603 or 0805, for the bootstrap supply. These 33-nF capacitors ensure sufficient energy storage, even
during minimal PWM duty cycles, to keep the high-side power stage FET (LDMOS) fully turned on during the
remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB
placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD_X). For
optimal electrical performance, EMI compliance, and system reliability, it is important that each PVDD_X pin is
decoupled with a 100-nF ceramic capacitor placed as close as possible to each supply pin.
The TAS5707 is fully protected against erroneous power-stage turnon due to parasitic gate charging.
ERROR REPORTING
Any fault resulting in device shutdown is signaled by the FAULT pin going low (see Table 1). A sticky version of
this pin is available on D1 of register 0X02.
Table 1. FAULT Output States
FAULT
DESCRIPTION
0
Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or over
voltage ERROR
1
No faults (normal operation)
DEVICE PROTECTION SYSTEM
Overcurrent (OC) Protection With Current Limiting
The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The
detector outputs are closely monitored by two protection systems. The first protection system controls the power
stage in order to prevent the output current further increasing, i.e., it performs a cycle-by-cycle current-limiting
function, rather than prematurely shutting down during combinations of high-level music transients and extreme
speaker load impedance drops. If the high-current condition situation persists, i.e., the power stage is being
overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in
the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short
circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges.
That is, if the bridge-tied load between half-bridges A and B causes an overcurrent fault, half-bridges A, B, C,
and D are shut down.
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Overtemperature Protection
The TAS5707 has over temperature-protection system. If the device junction temperature exceeds 150°C
(nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the
high-impedance (Hi-Z) state and FAULT being asserted low. The TAS5707 recovers automatically once the
temperature drops approximately 30°.
Undervoltage Protection (UVP) and Power-On
Reset (POR)
The UVP and POR circuits of the TAS5707 fully protect the device in any power-up/down and brownout situation.
While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully
operational when the PVDD and AVDD supply voltages reach 7.6 V and 2.7 V, respectively. Although PVDD and
AVDD are independently monitored, a supply voltage drop below the UVP threshold on AVDD or either PVDD
pin results in all half-bridge outputs immediately being set in the high-impedance (Hi-Z) state and FAULT being
asserted low.
SSTIMER FUNCTIONALITY
The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when
exiting all-channel shutdown. The capacitor on the SSTIMER pin is slowly charged through an internal current
source, and the charge time determines the rate at which the output transitions from a near zero duty cycle to the
desired duty cycle. This allows for a smooth transition that minimizes audible pops and clicks. When the part is
shutdown the drivers are tristated and transition slowly down through a 3K resistor, similarly minimizing pops and
clicks. The shutdown transition time is independent of SSTIMER pin capacitance. Larger capacitors will increase
the start-up time, while capacitors smaller than 2.2 nF will decrease the start-up time. The SSTIMER pin should
be left floating for BD modulation.
CLOCK, AUTO DETECTION, AND PLL
The TAS5707 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP)
supports all the sample rates and MCLK rates that are defined in the clock control register.
The TAS5707 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 ×
fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections. The clock section
uses MCLK or the internal oscillator clock (when MCLK is unstable, out of range, or absent) to produce the
internal clock (DCLK) running at 512 time the PWM switching frequency.
The DAP can autodetect and set the internal clock control logic to the appropriate settings for all supported clock
rates as defined in the clock control register.
TAS5707 has robust clock error handling that uses the bulit-in trimmed oscillator clock to quickly detect
changes/errors. Once the system detects a clock change/error, it will mute the audio (through a single step mute)
and then force PLL to limp using the internal oscillator as a reference clock. Once the clocks are stable, the
system will auto detect the new rate and revert to normal operation. During this process, the default volume will
be restored in a single step (also called hard unmute). The ramp process can be programmed to ramp back
slowly (also called soft unmute) as defined in volume register (0X0E).
SERIAL DATA INTERFACE
Serial data is input on SDIN. The PWM outputs are derived from SDIN. The TAS5707 DAP accepts serial data in
16-, 20-, or 24-bit left-justified, right-justified, and I2S serial data formats.
PWM Section
The TAS5707 DAP device uses noise-shaping and sophisticated non-linear correction algorithms to achieve high
power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to
increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP
and outputs two BTL PWM audio output channels.
The PWM section has individual channel dc blocking filters that can be enabled and disabled. The filter cutoff
frequency is less than 1 Hz. Individual channel de-emphasis filters for 44.1- and 48-kHz are included and can be
enabled and disabled.
18
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Finally, the PWM section has an adjustable maximum modulation limit of 93.8% to 99.2%.
For detailed description of using audio processing features like DRC and EQ, please refer to User's Guide and
TAS570X GDE software development tool documentation. Also refer to GDE software development tool for
device data path.
I2C COMPATIBLE SERIAL CONTROL INTERFACE
The TAS5707 DAP has an I2C serial control slave interface to receive commands from a system controller. The
serial control interface supports both normal-speed (100-kHz) and high-speed (400-kHz) operations without wait
states. As an added feature, this interface operates even if MCLK is absent.
The serial control interface supports both single-byte and multi-byte read and write operations for status registers
and the general control registers associated with the PWM.
SERIAL INTERFACE CONTROL AND TIMING
I2S Timing
I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the
right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or
64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes
state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge of bit
clock. The DAP masks unused trailing data bit positions.
2
2-Channel I S (Philips Format) Stereo Input
32 Clks
LRCLK (Note Reversed Phase)
32 Clks
Right Channel
Left Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 17. I2S 64-fS Format
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2
2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size)
LRCLK
24 Clks
24 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
24-Bit Mode
23 22
MSB
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
3
2
1
0
LSB
23 22
17 16
9
8
5
4
19 18
13 12
5
4
1
0
15 14
9
1
0
3
2
1
20-Bit Mode
19 18
16-Bit Mode
15 14
8
8
T0092-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 18. I2S 48-fS Format
2
2-Channel I S (Philips Format) Stereo Input
LRCLK
16 Clks
16 Clks
Left Channel
Right Channel
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
MSB
LSB
11 10
9
8
5
4
3
2
1
0
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
T0266-01
NOTE: All data presented in 2s-complement form with MSB first.
Figure 19. I2S 32-fS Format
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Left-Justified
Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it
is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32,
48, or 64 × fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK
toggles. The data is written MSB first and is valid on the rising edge of the bit clock. The DAP masks unused
trailing data bit positions.
2-Channel Left-Justified Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
9
8
5
4
5
4
1
0
1
0
1
0
MSB
LSB
23 22
9
8
5
4
19 18
5
4
1
0
15 14
1
0
1
0
20-Bit Mode
19 18
16-Bit Mode
15 14
T0034-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 20. Left-Justified 64-fS Format
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2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
21
LSB
17 16
9
8
5
4
13 12
5
4
1
0
9
1
0
1
0
MSB
LSB
21
17 16
9
8
5
4
19 18 17
13 12
5
4
1
0
15 14 13
9
1
0
23 22
1
0
20-Bit Mode
19 18 17
16-Bit Mode
15 14 13
8
8
T0092-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 21. Left-Justified 48-fS Format
2-Channel Left-Justified Stereo Input
16 Clks
16 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
16-Bit Mode
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
MSB
15 14 13 12
LSB
11 10
9
8
5
4
3
2
1
0
T0266-02
NOTE: All data presented in 2s-complement form with MSB first.
Figure 22. Left-Justified 32-fS Format
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Right-Justified
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
2-Channel Right-Justified (Sony Format) Stereo Input
32 Clks
32 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
MSB
LSB
23 22
19 18
15 14
1
0
19 18
15 14
1
0
15 14
1
0
20-Bit Mode
16-Bit Mode
T0034-03
Figure 23. Right Justified 64-fS Format
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2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size)
24 Clks
24 Clks
Left Channel
Right Channel
LRCLK
SCLK
SCLK
MSB
24-Bit Mode
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
MSB
23 22
LSB
19 18
15 14
6
5
2
1
0
19 18
15 14
6
5
2
1
0
15 14
6
5
2
1
0
20-Bit Mode
16-Bit Mode
T0092-03
Figure 24. Right Justified 48-fS Format
Figure 25. Right Justified 32-fS Format
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I2C SERIAL CONTROL INTERFACE
The TAS5707 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and
supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations.
This is a slave only device that does not support a multimaster bus environment or wait state insertion. The
control interface is used to program the registers of the device and to read device status.
The DAP supports the standard-mode I2C bus operation (100 kHz maximum) and the fast I2C bus operation
(400 kHz maximum). The DAP performs all I2C operations without I2C wait cycles.
General I2C Operation
The I2C bus employs two signals; SDA (data) and SCL (clock), to communicate between integrated circuits in a
system. Data is transferred on the bus serially one bit at a time. The address and data can be transferred in byte
(8-bit) format, with the most significant bit (MSB) transferred first. In addition, each byte transferred on the bus is
acknowledged by the receiving device with an acknowledge bit. Each transfer operation begins with the master
device driving a start condition on the bus and ends with the master device driving a stop condition on the bus.
The bus uses transitions on the data pin (SDA) while the clock is high to indicate a start and stop conditions. A
high-to-low transition on SDA indicates a start and a low-to-high transition indicates a stop. Normal data bit
transitions must occur within the low time of the clock period. These conditions are shown in Figure 26. The
master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another
device and then waits for an acknowledge condition. The TAS5707 holds SDA low during the acknowledge clock
period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence.
Each device is addressed by a unique 7-bit slave address plus R/W bit (1 byte). All compatible devices share the
same signals via a bidirectional bus using a wired-AND connection. An external pullup resistor must be used for
the SDA and SCL signals to set the high level for the bus.
SDA
R/
A
W
7-Bit Slave Address
7
6
5
4
3
2
1
0
8-Bit Register Address (N)
7
6
5
4
3
2
1
0
8-Bit Register Data For
Address (N)
A
7
6
5
4
3
2
1
8-Bit Register Data For
Address (N)
A
0
7
6
5
4
3
2
1
A
0
SCL
Start
Stop
T0035-01
2
Figure 26. Typical I C Sequence
There is no limit on the number of bytes that can be transmitted between start and stop conditions. When the last
word transfers, the master generates a stop condition to release the bus. A generic data transfer sequence is
shown in Figure 26.
The 7-bit address for TAS5707 is 0011 011 (0x36).
TAS5707 address can be changed from 0X36 to 0X38 by writing 0x38 to device address register 0XF9.
Single- and Multiple-Byte Transfers
The serial control interface supports both single-byte and multiple-byte read/write operations for subaddresses
0x00 to 0x1F. However, for the subaddresses 0x20 to 0xFF, the serial control interface supports only
multiple-byte read/write operations (in multiples of 4 bytes).
During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress
assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does
not contain 32 bits, the unused bits are read as logic 0.
During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes
that are required for each specific subaddress. For example, if a write command is received for a biquad
subaddress, the DAP expects to receive five 32-bit words. If fewer than five 32-bit data words have been
received when a stop command (or another start command) is received, the data received is discarded.
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Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5707
also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for
that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the
data for all 16 subaddresses is successfully received by the TAS5707. For I2C sequential write transactions, the
subaddress then serves as the start address, and the amount of data subsequently transmitted, before a stop or
start is transmitted, determines how many subaddresses are written. As was true for random addressing,
sequential addressing requires that a complete set of data be transmitted. If only a partial set of data is written to
the last subaddress, the data for the last subaddress is discarded. However, all other data written is accepted;
only the incomplete data is discarded.
Single-Byte Write
As shown in Figure 27, a single-byte data write transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of
the data transfer. For a write data transfer, the read/write bit will be a 0. After receiving the correct I2C device
address and the read/write bit, the DAP responds with an acknowledge bit. Next, the master transmits the
address byte or bytes corresponding to the TAS5707 internal memory address being accessed. After receiving
the address byte, the TAS5707 again responds with an acknowledge bit. Next, the master device transmits the
data byte to be written to the memory address being accessed. After receiving the data byte, the TAS5707 again
responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the
single-byte data write transfer.
Start
Condition
Acknowledge
A6
A5
A4
A3
A2
A1
A0
Acknowledge
R/W ACK A7
A6
A5
2
A4
A3
A2
A1
Acknowledge
A0 ACK D7
D6
Subaddress
I C Device Address and
Read/Write Bit
D5
D4
D3
D2
D1
D0 ACK
Stop
Condition
Data Byte
T0036-01
Figure 27. Single-Byte Write Transfer
Multiple-Byte Write
A multiple-byte data write transfer is identical to a single-byte data write transfer except that multiple data bytes
are transmitted by the master device to the DAP as shown in Figure 28. After receiving each data byte, the
TAS5707 responds with an acknowledge bit.
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
2
I C Device Address and
Read/Write Bit
A6
A5
A4
A3
Subaddress
A1
Acknowledge
Acknowledge
Acknowledge
Acknowledge
A0 ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-02
Figure 28. Multiple-Byte Write Transfer
26
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Single-Byte Read
As shown in Figure 29, a single-byte data read transfer begins with the master device transmitting a start
condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write
followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal
memory address to be read. As a result, the read/write bit becomes a 0. After receiving the TAS5707 address
and the read/write bit, TAS5707 responds with an acknowledge bit. In addition, after sending the internal memory
address byte or bytes, the master device transmits another start condition followed by the TAS5707 address and
the read/write bit again. This time the read/write bit becomes a 1, indicating a read transfer. After receiving the
address and the read/write bit, the TAS5707 again responds with an acknowledge bit. Next, the TAS5707
transmits the data byte from the memory address being read. After receiving the data byte, the master device
transmits a not acknowledge followed by a stop condition to complete the single byte data read transfer.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
A5
A1
A0 R/W ACK A7
Acknowledge
A6
2
A5
A4
A0 ACK
A6
A5
A1
A0 R/W ACK D7
D6
2
Subaddress
I C Device Address and
Read/Write Bit
Not
Acknowledge
Acknowledge
D1
D0 ACK
Stop
Condition
Data Byte
I C Device Address and
Read/Write Bit
T0036-03
Figure 29. Single-Byte Read Transfer
Multiple-Byte Read
A multiple-byte data read transfer is identical to a single-byte data read transfer except that multiple data bytes
are transmitted by the TAS5707 to the master device as shown in Figure 30. Except for the last data byte, the
master device responds with an acknowledge bit after receiving each data byte.
Repeat Start
Condition
Start
Condition
Acknowledge
A6
2
A0 R/W ACK A7
I C Device Address and
Read/Write Bit
Acknowledge
A6
A5
Subaddress
A6
A0 ACK
2
Acknowledge
Acknowledge
Acknowledge
Not
Acknowledge
A0 R/W ACK D7
D0 ACK D7
D0 ACK D7
D0 ACK
I C Device Address and
Read/Write Bit
First Data Byte
Other Data Bytes
Last Data Byte
Stop
Condition
T0036-04
Figure 30. Multiple Byte Read Transfer
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Dynamic Range Control (DRC)
The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the
left/right channels.
The DRC input/output diagram is shown in Figure 31.
Output Level (dB)
K
1:1 Transfer Function
O
Implemented Transfer Function
T
Input Level (dB)
M0091-02
Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
• One DRC for left/right
• The DRC has adjustable threshold, offset, and compression levels
• Programmable energy, attack, and decay time constants
• Transparent compression: compressors can attack fast enough to avoid apparent clipping before engaging,
and decay times can be set slow enough to avoid pumping.
Figure 31. Dynamic Range Control
Audio Input
DRC
Energy
Filter
Compression
Control
Attack
and
Decay
Filters
a, w
T, K, O
aa, wa / ad, wd
0x3A
0x40, 0x41, 0x42
0x3B / 0x3C
DRC Coefficient
Alpha Filter Structure
S
a
w
–1
Z
NOTE:
w=1–a
B0265-01
Figure 32. DRC Structure
28
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BANK SWITCHING
The TAS5707 uses an approach called bank switching together with automatic sample-rate detection. All
processing features that must be changed for different sample rates are stored internally in three banks. The
user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is
used in 44.1/48 kHz mode, and bank 3 is used for all other rates. Combined with the clock-rate autodetection
feature, bank switching allows the TAS5707 to detect automatically a change in the input sample rate and switch
to the appropriate bank without any MCU intervention.
An external controller configures bankable locations (0x29-0x36 and 0x3A-0x3C) for all three banks during the
initialization sequence.
If auto bank switching is enabled (register 0x50, bits 2:0) , then the TAS5707 automatically swaps the coefficients
for subsequent sample rate changes, avoiding the need for any external controller intervention for a sample rate
change.
By default, bits 2:0 have the value 000; indicating that bank switching is disabled. In that state, updates to
bankable locations take immediate effect. A write to register 0x50 with bits 2:0 being 001, 010, or 011 brings the
system into the coefficient-bank-update state update bank1, update bank2, or update bank3, respectively. Any
subsequent write to bankable locations updates the coefficient banks stored outside the DAP. After updating all
the three banks, the system controller should issue a write to register 0x50 with bits 2:0 being 100; this changes
the system state to automatic bank switching mode. In automatic bank switching mode, the TAS5707
automatically swaps banks based on the sample rate.
Command sequences for updating DAP coefficients can be summarized as follows:
1. Bank switching disabled (default): DAP coefficient writes take immediate effect and are not
influenced by subsequent sample rate changes.
OR
Bank switching enabled:
a. Update bank-1 mode: Write "001" to bits 2:0 of reg 0x50. Load the 32 kHz coefficients.
b. Update bank-2 mode: Write "010" to bits 2:0 of reg 0x50. Load the 48 kHz coefficients.
c. Update bank-3 mode: Write "011" to bits 2:0 of reg 0x50. Load the other coefficients.
d. Enable automatic bank switching by writing "100" to bits 2:0 of reg 0x50.
26-Bit 3.23 Number Format
All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.23
numbers means that there are 3 bits to the left of the decimal point and 23 bits to the right of the decimal point.
This is shown in Figure 33 .
2
–23
2
2
–5
–1
Bit
Bit
Bit
0
2 Bit
1
2 Bit
Sign Bit
S_xx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx
M0125-01
Figure 33. 3.23 Format
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The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 33. If the
most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct
number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must
be inverted, a 1 added to the result, and then the weighting shown in Figure 34 applied to obtain the magnitude
of the negative number.
0
1
2 Bit
2 Bit
1
2
–1
Bit
0
2
(1 or 0) ´ 2 + (1 or 0) ´ 2 + (1 or 0) ´ 2
–1
–4
Bit
2
+ ....... (1 or 0) ´ 2
–4
–23
Bit
+ ....... (1 or 0) ´ 2
–23
M0126-01
Figure 34. Conversion Weighting Factors—3.23 Format to Floating Point
Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit
number (4-byte or 8-digit hexadecimal number) is shown in Figure 35
Fraction
Digit 6
Sign
Bit
Fraction
Digit 1
Integer
Digit 1
Fraction
Digit 2
Fraction
Digit 3
Fraction
Digit 4
Fraction
Digit 5
u u u u
u u S x
x. x x x
x x x x
x x x x
x x x x
x x x x
x x x x 0
Coefficient
Digit 8
Coefficient
Digit 7
Coefficient
Digit 6
Coefficient
Digit 5
Coefficient
Digit 4
Coefficient
Digit 3
Coefficient
Digit 2
Coefficient
Digit 1
u = unused or don’t care bits
Digit = hexadecimal digit
M0127-01
Figure 35. Alignment of 3.23 Coefficient in 32-Bit I2C Word
Sample calculation for 3.23 format
db
Linear
Decimal
0
1
8388608
Hex (3.23 Format)
800000
5
1.77
14917288
00E39EA8
-5
0.56
4717260
0047FACC
X
L = 10(X/20)
D = 8388608 × L
H = dec2hex (D, 8)
Sample calculation for 9.17 format
db
30
Linear
Decimal
Hex (9.17 Format)
0
1
131072
20000
5
1.77
231997
38A3D
-5
0.56
73400
11EB8
X
L = 10(X/20)
D = 131072 × L
H = dec2hex (D, 8)
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2
I C
PVDD
RESET
SCL
SDA
0 ns
100 ms
0 ns
0 ns
100 μs
3V
10 ms
8V
6V
13.5 ms
Trim
50 ms
DAP
Config
Other
Config
Stable and Valid Clocks
(1)
tPLL
(1) tPLL has to be greater than 240 ms + 1.3 tstart.
This constraint only applies to the first trim command following AVDD/DVDD power-up.
It does not apply to trim commands following subsequent resets.
(2) tstart/tstop = PWM start/stop time as defined in register 0X1A
2
I S
MCLK
LRCLK
SCLK
SDIN
PDN
AVDD/DVDD
Initialization
Exit
SD
tPLL
(1)
(2)
1 ms + 1.3 tstart
(2)
1 ms + 1.3 tstart
Volume and Mute Commands
Clock Changes/Errors OK
Normal Operation
Enter
SD
50 ms
1 ms + 1.3 tstop
(2)
Stable and Valid Clocks
Shutdown
2 ms
2 ms
2 ms
2 ms
8V
6V
0 ns
Powerdown
T0419-01
3V
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Recommended Use Model
Figure 36. Recommended Command Sequence
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3V
AVDD/DVDD
0 ns
PDN
2 ms
0 ns
2
I S
2 ms
0 ns
2
I C
2 ms
RESET
2 ms
0 ns
8V
PVDD
6V
T0420-01
Figure 37. Power Loss Sequence
Recommended Command Sequences
The DAP has two groups of commands. One set is for configuration and is intended for use only during
initialization. The other set has built-in click and pop protection and may be used during normal operation while
audio is streaming. The following supported command sequences illustrate how to initialize, operate, and
shutdown the device.
Initialization Sequence
Use the following sequence to power-up and initialize the device:
1.
Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V.
2.
Initialize digital inputs and PVDD supply as follows:
•
Drive RESETZ=0, PDNZ=1, and other digital inputs to their desired state while ensuring that
all are never more than 2.5V above AVDD/DVDD. Provide stable and valid I2S clocks
(MCLK, LRCLK, and SCLK). Wait at least 100us, drive RESETZ=1, and wait at least another
13.5ms.
•
Ramp up PVDD to at least 8V while ensuring that it remains below 6V for at least 100us after
AVDD/DVDD reaches 3V. Then wait at least another 10us.
3.
Trim oscillator (write 0x00 to register 0x1B) and wait at least 50ms.
4.
Configure the DAP via I2C (see Users's Guide for typical values):
Biquads (0x29-36)
DRC parameters (0x3A-3C, 0x40-42, and 0x46)
Bank select (0x50)
32
5.
Configure remaining registers
6.
Exit shutdown (sequence defined below).
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Normal Operation
The following are the only events supported during normal operation:
(a) Writes to master/channel volume registers
(b) Writes to soft mute register
(c) Enter and exit shutdown (sequence defined below)
(d) Clock errors and rate changes
Note: Events (c) and (d) are not supported for 240ms+1.3*Tstart after trim following AVDD/DVDD powerup
ramp (where Tstart is specified by register 0x1A).
Shutdown Sequence
Enter:
1.
Ensure I2S clocks have been stable and valid for at least 50ms.
2.
Write 0x40 to register 0x05.
3.
Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A).
4.
Once in shutdown, stable clocks are not required while device remains idle.
5.
If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before
returning to step 4 of initialization sequence.
1.
Ensure I2S clocks have been stable and valid for at least 50ms.
2.
Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240ms
after trim following AVDD/DVDD powerup ramp).
3.
Wait at least 1ms+1.3*Tstart (where Tstart is specified by register 0x1A).
4.
Proceed with normal operation.
Exit:
Powerdown Sequence
Use the following sequence to powerdown the device and its supplies:
1.
If time permits, enter shutdown (sequence defined above); else, in case of sudden power loss,
assert PDNZ=0 and wait at least 2ms.
2.
Assert RESETZ=0.
3.
Drive digital inputs low and ramp down PVDD supply as follows:
4.
•
Drive all digital inputs low after RESETZ has been low for at least 2us.
•
Ramp down PVDD while ensuring that it remains above 8V until RESETZ has been low for at
least 2us.
Ramp down AVDD/DVDD while ensuring that it remains above 3V until PVDD is below 6V and
that it is never more than 2.5V below the digital inputs.
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Table 2. Serial Control Interface Register Summary
SUBADDRESS
REGISTER NAME
NO. OF
BYTES
INITIALIZATION
VALUE
CONTENTS
A u indicates unused bits.
0x00
Clock control register
1
Description shown in subsequent section
0x6C
0x01
Device ID register
1
Description shown in subsequent section
0x70
0x02
Error status register
1
Description shown in subsequent section
0x00
0x03
System control register 1
1
Description shown in subsequent section
0xA0
0x04
Serial data interface
register
1
Description shown in subsequent section
0x05
0x05
System control register 2
1
Description shown in subsequent section
0x40
0x06
Soft mute register
1
Description shown in subsequent section
0x00
0x07
Master volume
1
Description shown in subsequent section
0xFF (mute)
0x08
Channel 1 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x09
Channel 2 vol
1
Description shown in subsequent section
0x30 (0 dB)
0x0A
Fine master volume
1
Description shown in subsequent section
0x00 (0 dB)
0x0B - 0X0D
0x0E
Volume configuration
register
0x0F
(1)
1
Reserved
1
Description shown in subsequent section
1
Reserved (1)
0x91
0x10
Modulation limit register
1
Description shown in subsequent section
0x02
0x11
IC delay channel 1
1
Description shown in subsequent section
0xAC
0x12
IC delay channel 2
1
Description shown in subsequent section
0x54
0x13
IC delay channel 3
1
Description shown in subsequent section
0xAC
0x14
IC delay channel 4
1
Description shown in subsequent section
0x54
1
Reserved (1)
0x15-0x19
0x1A
Start/stop period register
1
Description shown in subsequent section
0x0F
0x1B
Oscillator trim register
1
Description shown in subsequent section
0x82
0x1C
BKND_ERR register
1
Description shown in subsequent section
0x02
1
Reserved (1)
4
Description shown in subsequent section
4
Reserved (1)
4
Description shown in subsequent section
0x1D–0x1F
0x20
Input MUX register
0x21-0X24
0x25
PWM MUX register
0x26-0x28
0x29
0x2A
0x2B
ch1_bq[0]
ch1_bq[1]
ch1_bq[2]
(1)
Reserved registers should not be accessed.
34
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0x0001 7772
0x0102 1345
(1)
4
Reserved
20
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
20
20
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Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
REGISTER NAME
ch1_bq[3]
ch1_bq[4]
ch1_bq[5]
ch1_bq[6]
ch2_bq[0]
ch2_bq[1]
ch2_bq[2]
ch2_bq[3]
ch2_bq[4]
NO. OF
BYTES
20
20
20
20
20
20
20
20
20
CONTENTS
INITIALIZATION
VALUE
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
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Table 2. Serial Control Interface Register Summary (continued)
SUBADDRESS
0x35
0x36
REGISTER NAME
ch2_bq[5]
ch2_bq[6]
NO. OF
BYTES
20
20
0x3B
0x3C
DRC ae (3)
DRC (1 – ae)
DRC aa
DRC (1 – aa)
DRC ad
DRC (1 – ad)
8
8
8
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], b0[25:0]
0x0080 0000
u[31:26], b1[25:0]
0x0000 0000
u[31:26], b2[25:0]
0x0000 0000
u[31:26], a1[25:0]
0x0000 0000
u[31:26], a2[25:0]
0x0000 0000
u[31:26], ae[25:0]
0x0080 0000
u[31:26], (1 – ae)[25:0]
0x0000 0000
u[31:26], aa[25:0]
0x0080 0000
u[31:26], (1 – aa)[25:0]
0x0000 0000
u[31:26], ad[25:0]
0x0080 0000
u[31:26], (1 – ad)[25:0]
0x0000 0000
Reserved(2)
0x3D–0x3F
0x40
DRC-T
4
T[31:0] (9.23 format)
0xFDA2 1490
0x41
DRC-K
4
u[31:26], K[25:0]
0x0384 2109
0x42
DRC-O
4
u[31:26], O[25:0]
0x0008 4210
Reserved(2)
0x43–0x45
0x46
DRC control
4
0x50
Bank switch control
4
0x0000 0000
Description shown in subsequent section
0x0F70 8000
(2)
0x51–0xF8
0xF9
Description shown in subsequent section
Reserved(2)
0x47–0x4F
Reserved
Update device address
register
0xFA-0xFF
(2)
(3)
u[31:26], b0[25:0]
Reserved (2)
0x37 - 0x39
0x3A
INITIALIZATION
VALUE
CONTENTS
4
u[31:8],New Dev Id[7:0] (New Dev Id = 0x38)
0x00000036
Reserved(2)
Reserved registers should not be accessed.
"ae" stands for ∝ of energy filter, "aa" stands for ∝ of attack filter and "ad" stands for ∝ of decay filter and 1- ∝ = ω.
All DAP coefficients are 3.23 format unless specified otherwise.
36
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CLOCK CONTROL REGISTER (0x00)
The clocks and data rates are automatically determined by the TAS5707. The clock control register contains the
auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency.
Table 3. Clock Control Register (0x00)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
fS = 32-kHz sample rate
0
0
1
–
–
–
–
–
Reserved (1)
0
1
0
–
–
–
–
–
Reserved (1)
0
1
1
–
–
–
–
–
fS = 44.1/48-kHz sample rate
1
0
0
–
–
–
–
–
fs = 16-kHz sample rate
1
0
1
–
–
–
–
–
fs = 22.05/24 -kHz sample rate
1
1
0
–
–
–
–
–
fs = 8-kHz sample rate
1
1
1
–
–
–
–
–
fs = 11.025/12 -kHz sample rate
–
–
–
0
0
0
–
–
MCLK frequency = 64 × fS (3)
–
–
–
0
0
1
–
–
MCLK frequency = 128 × fS (3)
–
–
–
0
1
0
–
–
MCLK frequency = 192 × fS
–
–
–
0
1
1
–
–
MCLK frequency = 256 × fS
–
–
–
1
0
0
–
–
MCLK frequency = 384 × fS
–
–
–
1
0
1
–
–
MCLK frequency = 512 × fS
–
–
–
1
1
0
–
–
Reserved (1)
–
–
–
1
1
1
–
–
Reserved (1)
–
–
–
–
–
–
0
–
Reserved (1)
–
–
–
–
–
–
–
0
Reserved (1)
(1)
(2)
(3)
(4)
(5)
FUNCTION
(2)
(4)
(2) (5)
Reserved registers should not be accessed.
Default values are in bold.
Only available for 44.1 kHz and 48 kHz rates.
Rate only available for 32/44.1/48 KHz sample rates
Not available at 8 kHz
DEVICE ID REGISTER (0x01)
The device ID register contains the ID code for the firmware revision.
Table 4. General Status Register (0x01)
D7
D6
D5
D4
D3
D2
D1
D0
X
–
–
–
–
–
–
–
Reserved
FUNCTION
–
1
1
1
0
0
0
0
Identification code
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ERROR STATUS REGISTER (0x02)
The error bits are sticky and are not cleared by the hardware. This means that the software must clear the
register (write zeroes) and then read them to determine if they are persistent errors.
Error Definitions:
• MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing.
• SCLK Error: The number of SCLKs per LRCLK is changing.
• LRCLK Error: LRCLK frequency is changing.
• Frame Slip: LRCLK phase is drifting with respect to internal Frame Sync.
Table 5. Error Status Register (0x02)
D7
D6
D5
D4
D3
D2
D1
D0
1
-
–
–
–
–
–
–
MCLK error
–
1
–
–
–
–
–
–
PLL autolock error
–
–
1
–
–
–
–
–
SCLK error
–
–
–
1
–
–
–
–
LRCLK error
–
–
–
–
1
–
–
–
Frame slip
–
–
–
–
–
–
1
–
Over current, Over Temperature, Over voltage or Under voltage errors.
–
–
–
–
–
–
–
1
Overtemperature warning (sets around 145°)
0
0
0
0
0
0
0
0
No errors
(1)
FUNCTION
(1)
Default values are in bold.
SYSTEM CONTROL REGISTER 1 (0x03)
The system control register 1 has several functions:
Bit D7:
If 0, the dc-blocking filter for each channel is disabled.
If 1, the dc-blocking filter (–3 dB cutoff <1 Hz) for each channel is enabled (default).
Bit D5:
If 0, use soft unmute on recovery from clock error. This is a slow recovery. Unmute takes same
time as volume ramp defined in reg 0X0E.
If 1, use hard unmute on recovery from clock error (default). This is a fast recovery, a single step
volume ramp
Bits D1–D0: Select de-emphasis
Table 6. System Control Register 1 (0x03)
D7
D6
D5
D4
D3
D2
D1
D0
0
–
–
–
–
–
–
–
PWM high-pass (dc blocking) disabled
1
–
–
–
–
–
–
–
PWM high-pass (dc blocking) enabled
(1)
38
FUNCTION
(1)
(1)
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Soft unmute on recovery from clock error
–
–
1
–
–
–
–
–
Hard unmute on recovery from clock error
–
–
–
0
–
–
–
–
Reserved
–
–
–
–
0
–
–
–
Reserved
(1)
(1)
(1)
(1)
–
–
–
–
–
0
–
–
Reserved
–
–
–
–
–
–
0
0
No de-emphasis
–
–
–
–
–
–
0
1
Reserved
–
–
–
–
–
–
1
0
De-emphasis for fS = 44.1 kHz
–
–
–
–
–
–
1
1
De-emphasis for fS = 48 kHz
(1)
Default values are in bold.
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SERIAL DATA INTERFACE REGISTER (0x04)
As shown in Table 7, the TAS5707 supports 9 serial data modes. The default is 24-bit, I2S mode,
Table 7. Serial Data Interface Control Register (0x04) Format
RECEIVE SERIAL DATA
INTERFACE FORMAT
WORD
LENGTH
D7–D4
D3
D2
D1
D0
Right-justified
16
0000
0
0
0
0
Right-justified
20
0000
0
0
0
1
Right-justified
24
0000
0
0
1
0
2
I S
16
000
0
0
1
1
I2S
20
0000
0
1
0
0
24
0000
0
1
0
1
Left-justified
16
0000
0
1
1
0
Left-justified
20
0000
0
1
1
1
Left-justified
24
0000
1
0
0
0
Reserved
0000
1
0
0
1
Reserved
0000
1
0
1
0
Reserved
0000
1
0
1
1
Reserved
0000
1
1
0
0
Reserved
0000
1
1
0
1
Reserved
0000
1
1
1
0
Reserved
0000
1
1
1
1
I2S
(1)
(1)
Default values are in bold.
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SYSTEM CONTROL REGISTER 2 (0x05)
When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs
are shut down(hard mute).
Table 8. System Control Register 2 (0x05)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
(1)
0
–
–
–
–
–
–
–
Reserved
–
1
–
–
–
–
–
–
Enter all channel shut down (hard mute). (1)
–
0
–
–
–
–
–
–
Eit all channel shutdown (normal operation)
–
–
0
0
0
0
0
0
Reserved
(1)
(1)
Default values are in bold.
SOFT MUTE REGISTER (0x06)
Writing a 1 to any of the following bits sets the output of the respective channel to 50% duty cycle (soft mute).
Table 9. Soft Mute Register (0x06)
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
1
Soft mute channel 1
–
–
–
–
–
–
–
0
Soft unmute channel 1
–
–
–
–
–
–
1
–
Soft mute channel 2
–
–
–
–
–
–
0
–
Soft unmute channel 2
0
0
0
0
0
0
–
–
Reserved
40
FUNCTION
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VOLUME REGISTERS (0x07, 0x08, 0x09)
Step size is 0.5 dB.
Master volume
– 0x07 (default is mute)
Channel-1 volume
– 0x08 (default is 0 dB)
Channel-2 volume
– 0x09 (default is 0 dB)
Table 10. Volume Registers (0x07, 0x08, 0x09)
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
0
0
0
0
0
0
0
24 dB
0
0
1
1
0
0
0
0
0 dB (default for individual channel volume)
1
1
0
0
1
1
0
1
–78.5 dB
1
1
0
0
1
1
1
0
–79.0 dB
1
1
0
0
1
1
1
1
Values between 0xCF and 0xFE are Reserved
1
1
1
1
1
1
1
1
MUTE (default for master volume)
(1)
FUNCTION
(1)
Default values are in bold.
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MASTER FINE VOLUME REGISTER (0x0A)
This register can be used to provide precision tuning of master volume.
Table 11. Master Fine Volume Register (0x0A)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
(1)
–
–
–
–
–
–
0
0
0 dB
–
–
–
–
–
–
0
1
0.125 dB
–
–
–
–
–
–
1
0
0.25 dB
–
–
–
–
–
–
1
1
0.375 dB
1
–
–
–
–
–
–
–
Write enable bit
0
–
–
–
–
–
–
–
Ignore Write to register 0X0A
(1)
Default values are in bold.
VOLUME CONFIGURATION REGISTER (0x0E)
Bits
D2–D0:
Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the
number of steps in a volume ramp.Volume steps occur at a rate that depends on the sample rate of
the I2S data as follows
Sample Rate (KHz)
Approximate Ramp Rate
8/16/32
125 us/step
11.025/22.05/44.1
90.7 us/step
12/24/48
83.3 us/step
Table 12. Volume Control Register (0x0E)
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
–
–
–
Reserved
–
–
–
–
–
0
0
0
Volume slew 512 steps (43 ms volume ramp time at 48kHz)
–
–
–
–
–
0
0
1
Volume slew 1024 steps (85 ms volume ramp time at 48kHz)
–
–
–
–
–
0
1
0
Volume slew 2048 steps (171 ms volume ramp time at 48kHz)
–
–
–
–
–
0
1
1
Volume slew 256 steps (21ms volume ramp time at 48kHz)
–
–
–
–
–
1
X
X
Reserved
(1)
42
FUNCTION
(1)
(1)
Default values are in bold.
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MODULATION LIMIT REGISTER (0x10)
Table 13. Modulation Limit Register (0x10)
D7
D6
D5
D4
D3
D2
D1
D0
MODULATION LIMIT
–
–
–
–
–
0
0
0
99.2%
–
–
–
–
–
0
0
1
98.4%
–
–
–
–
–
0
1
0
97.7%
–
–
–
–
–
0
1
1
96.9%
–
–
–
–
–
1
0
0
96.1%
–
–
–
–
–
1
0
1
95.3%
–
–
–
–
–
1
1
0
94.5%
–
–
–
–
–
1
1
1
93.8%
0
0
0
0
0
–
–
–
RESERVED
INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)
Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.
Table 14. Channel Interchannel Delay Register Format
BITS DEFINITION
(1)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
–
–
Minimum absolute delay, 0 DCLK cycles
FUNCTION
0
1
1
1
1
1
–
–
Maximum positive delay, 31 × 4 DCLK cycles
1
0
0
0
0
0
–
–
Maximum negative delay, –32 × 4 DCLK cycles
0
0
RESERVED
SUBADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Delay = (value) × 4 DCLKs
0x11
1
0
1
0
1
1
–
–
Default value for channel 1
(1)
0x12
0
1
0
1
0
1
–
–
Default value for channel 2
(1)
0x13
1
0
1
0
1
1
–
–
Default value for channel 1
(1)
0x14
0
1
0
1
0
1
–
–
Default value for channel 2
(1)
Default values are in bold.
ICD settings have high impact on audio performance (eg: Dynamic Range, THD, Cross talk etc.) Therefore,
appropriate ICD settings must be used. By default device has ICD settings for AD mode.If used in BD mode,
then update these registers before coming out of all channel shutdown.
MODE
AD MODE
BD MODE
0x11
AC
4C
0x12
54
34
0x13
AC
1C
0x14
54
64
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START/STOP PERIOD REGISTER (0x1A)
This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down
command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are
only approximate and vary depending on device activity level and I2S clock stability.
Table 15. Start/Stop Period Register (0x1A)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
–
–
–
–
–
Reserved
–
–
–
0
0
–
–
–
No 50% duty cycle start/stop period
–
–
–
0
1
0
0
0
16.5-ms 50% duty cycle start/stop period
–
–
–
0
1
0
0
1
23.9-ms 50% duty cycle start/stop period
–
–
–
0
1
0
1
0
31.4-ms 50% duty cycle start/stop period
–
–
–
0
1
0
1
1
40.4-ms 50% duty cycle start/stop period
–
–
–
0
1
1
0
0
53.9-ms 50% duty cycle start/stop period
–
–
–
0
1
1
0
1
70.3-ms 50% duty cycle start/stop period
–
–
–
0
1
1
1
0
94.2-ms 50% duty cycle start/stop period
–
–
–
0
1
1
1
1
125.7-ms 50% duty cycle start/stop period (1)
–
–
–
1
0
0
0
0
164.6-ms 50% duty cycle start/stop period
–
–
–
1
0
0
0
1
239.4-ms 50% duty cycle start/stop period
–
–
–
1
0
0
1
0
314.2-ms 50% duty cycle start/stop period
–
–
–
1
0
0
1
1
403.9-ms 50% duty cycle start/stop period
–
–
–
1
0
1
0
0
538.6-ms 50% duty cycle start/stop period
–
–
–
1
0
1
0
1
703.1-ms 50% duty cycle start/stop period
–
–
–
1
0
1
1
0
942.5-ms 50% duty cycle start/stop period
–
–
–
1
0
1
1
1
1256.6-ms 50% duty cycle start/stop period
–
–
–
1
1
0
0
0
1728.1-ms 50% duty cycle start/stop period
–
–
–
1
1
0
0
1
2513.6-ms 50% duty cycle start/stop period
–
–
–
1
1
0
1
0
3299.1-ms 50% duty cycle start/stop period
–
–
–
1
1
0
1
1
4241.7-ms 50% duty cycle start/stop period
–
–
–
1
1
1
0
0
5655.6-ms 50% duty cycle start/stop period
–
–
–
1
1
1
0
1
7383.7-ms 50% duty cycle start/stop period
–
–
–
1
1
1
1
0
9897.3-ms 50% duty cycle start/stop period
–
–
–
1
1
1
1
1
13,196.4-ms 50% duty cycle start/stop period
(1)
44
FUNCTION
Default values are in bold.
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OSCILLATOR TRIM REGISTER (0x1B)
The TAS5707 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This
reduces system cost because an external reference is not required. Currently, TI recommends a reference
resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO.
Writing 0X00 to reg 0X1B enables the trim that was programmed at the factory.
Note that trim must always be run following reset of the device.
Table 16. Oscillator Trim Register (0x1B)
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
(1)
1
–
–
–
–
–
–
–
Reserved
–
0
–
–
–
–
–
–
Oscillator trim not done (read-only)
–
1
–
–
–
–
–
–
Oscillator trim done (read only)
–
–
0
0
0
0
–
–
Reserved
–
–
–
–
–
–
0
–
Select factory trim (Write a 0 to select factory trim; default is 1.)
–
–
–
–
–
–
1
–
Factory trim disabled
–
–
–
–
–
–
–
0
Reserved
(1)
(1)
(1)
(1)
(1)
Default values are in bold.
BKND_ERR REGISTER (0x1C)
When a back-end error signal is received from the internal power stage, the power stage is reset stopping all
PWM activity. Subsequently, the modulator waits approximately for the time listed in Table 17 before attempting
to re-start the power stage.
Table 17. BKND_ERR Register (0x1C) (1)
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
X
Reserved
–
–
–
–
0
0
1
0
Set back-end reset period to 299 ms
–
–
–
–
0
0
1
1
Set back-end reset period to 449 ms
–
–
–
–
0
1
0
0
Set back-end reset period to 598 ms
–
–
–
–
0
1
0
1
Set back-end reset period to 748 ms
–
–
–
–
0
1
1
0
Set back-end reset period to 898 ms
–
–
–
–
0
1
1
1
Set back-end reset period to 1047 ms
–
–
–
–
1
0
0
0
Set back-end reset period to 1197 ms
–
–
–
–
1
0
0
1
Set back-end reset period to 1346 ms
–
–
–
–
1
0
1
X
Set back-end reset period to 1496 ms
–
–
–
–
1
1
X
X
Set back-end reset period to 1496 ms
(1)
(2)
FUNCTION
(2)
This register can be written only with a "non-Reserved" value. Also this register can be written once after the reset.
Default values are in bold.
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INPUT MULTIPLEXER REGISTER (0x20)
This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal
channels.
Table 18. Input Multiplexer Register (0x20)
(1)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
FUNCTION
D23
D22
D21
D20
D19
D18
D17
D16
0
–
–
–
–
–
–
–
Channel-1 AD mode
1
–
–
–
–
–
–
–
Channel-1 BD mode
–
0
0
0
–
–
–
–
SDIN-L to channel 1
–
0
0
1
–
–
–
–
SDIN-R to channel 1
–
0
1
0
–
–
–
–
Reserved
–
0
1
1
–
–
–
–
Reserved
–
1
0
0
–
–
–
–
Reserved
–
1
0
1
–
–
–
–
Reserved
–
1
1
0
–
–
–
–
Ground (0) to channel 1
–
1
1
1
–
–
–
–
Reserved
–
–
–
–
0
–
–
–
Channel 2 AD mode
–
–
–
–
1
–
–
–
Channel 2 BD mode
–
–
–
–
–
0
0
0
SDIN-L to channel 2
–
–
–
–
–
0
0
1
SDIN-R to channel 2
–
–
–
–
–
0
1
0
Reserved
–
–
–
–
–
0
1
1
Reserved
–
–
–
–
–
1
0
0
Reserved
–
–
–
–
–
1
0
1
Reserved
–
–
–
–
–
1
1
0
Ground (0) to channel 2
–
–
–
–
–
1
1
1
Reserved
D15
D14
D13
D12
D11
D10
D9
D8
0
1
1
1
0
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
1
0
0
1
0
Reserved
(1)
FUNCTION
(1)
(1)
FUNCTION
Reserved
(1)
Reserved
(1)
FUNCTION
Default values are in bold.
PWM OUTPUT MUX REGISTER (0x25)
This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be
output to any external output pin.
Bits D21–D20:
Selects which PWM channel is output to OUT_A
Bits D17–D16:
Selects which PWM channel is output to OUT_B
Bits D13–D12:
Selects which PWM channel is output to OUT_C
Bits D09–D08:
Selects which PWM channel is output to OUT_D
Note that channels are enclosed so that channel 1 = 0x00, channel 2 = 0x01, channet 1 = 0x02, and channel 2 =
0x03.
46
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Table 19. PWM Output Mux Register (0x25)
D31
D30
D29
D28
D27
D26
D25
D24
FUNCTION
Reserved
(1)
0
0
0
0
0
0
0
1
D23
D22
D21
D20
D19
D18
D17
D16
0
0
–
–
–
–
–
–
Reserved (1)
–
–
0
0
–
–
–
–
Multiplex channel 1 to OUT_A
–
–
0
1
–
–
–
–
Multiplex channel 2 to OUT_A
–
–
1
0
–
–
–
–
Multiplex channel 1 to OUT_A
–
–
1
1
–
–
–
–
Multiplex channel 2 to OUT_A
–
–
–
–
0
0
–
–
Reserved
–
–
–
–
–
–
0
0
Multiplex channel 1 to OUT_B
–
–
–
–
–
–
0
1
Multiplex channel 2 to OUT_B
–
–
–
–
–
–
1
0
Multiplex channel 1 to OUT_B
–
–
–
–
–
–
1
1
Multiplex channel 2 to OUT_B
D15
D14
D13
D12
D11
D10
D9
D8
FUNCTION
(1)
(1)
(1)
FUNCTION
(1)
0
0
–
–
–
–
–
–
Reserved
–
–
0
0
–
–
–
–
Multiplex channel 1 to OUT_C
–
–
0
1
–
–
–
–
Multiplex channel 2 to OUT_C (1)
–
–
1
0
–
–
–
–
Multiplex channel 1 to OUT_C
–
–
1
1
–
–
–
–
Multiplex channel 2 to OUT_C
–
–
–
–
0
0
–
–
Reserved
–
–
–
–
–
–
0
0
Multiplex channel 1 to OUT_D
–
–
–
–
–
–
0
1
Multiplex channel 2 to OUT_D
–
–
–
–
–
–
1
0
Multiplex channel 1 to OUT_D
–
–
–
–
–
–
1
1
Multiplex channel 2 to OUT_D
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
0
1
0
1
(1)
(1)
(1)
FUNCTION
RESERVED
Default values are in bold.
DRC CONTROL (0x46)
D31
D30
D29
D28
D27
D26
D25
D24
0
0
0
0
0
0
0
0
D23
D22
D21
D20
D19
D18
D17
D16
FUNCTION
Reserved
(1)
Reserved
(1)
Reserved
(1)
FUNCTION
0
0
0
0
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
–
–
–
–
–
–
–
0
DRC turned OFF
–
–
–
–
–
–
–
1
DRC turned ON
0
0
0
0
0
0
0
–
Reserved
(1)
FUNCTION
FUNCTION
(1)
(1)
Default values are in bold.
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47
TAS5707
SLOS556 – NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
BANK SWITCH AND EQ CONTROL (0x50)
Table 20. Bank Switching Command
D31
D30
D29
D28
D27
D26
D25
D24
0
–
–
–
–
–
–
–
32 kHz, does not use bank 3
1
–
–
–
–
–
–
–
32 kHz, uses bank 3
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Reserved
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 3
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 3
–
–
–
–
0
–
–
–
16 kHz, does not use bank 3
–
–
–
–
1
–
–
–
16 kHz, uses bank 3
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 3
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 3
–
–
–
–
–
–
0
–
8 kHz, does not use bank 3
–
–
–
–
–
–
1
–
8 kHz, uses bank 3
–
–
–
–
–
–
–
0
11.025 kHz/12, does not use bank 3
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 3
D23
D22
D21
D20
D19
D18
D17
D16
0
–
–
–
–
–
–
–
32 kHz, does not use bank 2
1
–
–
–
–
–
–
–
32 kHz, uses bank 2
–
1
–
–
–
–
–
–
Reserved
(1)
–
–
1
–
–
–
–
–
Reserved
(1)
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 2
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 2
–
–
–
–
0
–
–
–
16 kHz, does not use bank 2
–
–
–
–
1
–
–
–
16 kHz, uses bank 2
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 2
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 2
–
–
–
–
–
–
0
–
8 kHz, does not use bank 2
–
–
–
–
–
–
1
–
8 kHz, uses bank 2
–
–
–
–
–
–
–
0
11.025/12 kHz, does not use bank 2
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 2
D15
D14
D13
D12
D11
D10
D9
D8
0
–
–
–
–
–
–
–
32 kHz, does not use bank 1
1
–
–
–
–
–
–
–
32 kHz, uses bank 1
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Reserved
–
–
–
0
–
–
–
–
44.1/48 kHz, does not use bank 1
–
–
–
1
–
–
–
–
44.1/48 kHz, uses bank 1
–
–
–
–
0
–
–
–
16 kHz, does not use bank 1
–
–
–
–
1
–
–
–
16 kHz, uses bank 1
–
–
–
–
–
0
–
–
22.025/24 kHz, does not use bank 1
–
–
–
–
–
1
–
–
22.025/24 kHz, uses bank 1
–
–
–
–
–
–
0
–
8 kHz, does not use bank 1
–
–
–
–
–
–
1
–
8 kHz, uses bank 1
–
–
–
–
–
–
–
0
11.025/12 kHz, does not use bank 1
–
–
–
–
–
–
–
1
11.025/12 kHz, uses bank 1
(1)
48
FUNCTION
(1)
(1)
(1)
(1)
(1)
(1)
FUNCTION
(1)
(1)
(1)
(1)
(1)
(1)
FUNCTION
(1)
(1)
(1)
(1)
(1)
(1)
Default values are in bold.
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Product Folder Link(s): TAS5707
TAS5707
www.ti.com........................................................................................................................................................................................... SLOS556 – NOVEMBER 2008
Table 20. Bank Switching Command (continued)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
–
–
–
–
–
–
–
EQ OFF (bypass BQ 0-6 of channels 1 and 2)
–
0
–
–
–
–
–
–
Reserved
–
–
0
–
–
–
–
–
Ignore bank-mapping in bits D31–D8.Use default mapping.
–
–
–
0
–
–
–
–
L and R can be written independently.
–
–
–
1
–
–
–
–
L and R are ganged for EQ biquads; a write to Left channel BQ is
also written to Right channel BQ. (0X29-2F is ganged to 0X30-0X36).
–
–
–
–
0
–
–
–
Reserved
–
–
–
–
–
0
0
0
No bank switching. All updates to DAP
–
–
–
–
–
0
0
1
Configure bank 1 (32 kHz by default)
–
–
–
–
–
0
1
0
Configure bank 2 (44.1/48 kHz by default)
–
–
–
–
–
0
1
1
Configure bank 3 (other sample rates by default)
–
–
–
–
–
1
0
0
Automatic bank selection
–
–
–
–
–
1
0
1
Reserved
–
–
–
–
–
1
1
X
Reserved
1
(2)
FUNCTION
EQ ON
(2)
(2)
Use bank-mapping in bits D31–D8.
(2)
(2)
(2)
Default values are in bold.
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49
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TAS5707PHPR
Package Package Pins
Type Drawing
HTQFP
PHP
48
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Nov-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TAS5707PHPR
HTQFP
PHP
48
1000
346.0
346.0
33.0
Pack Materials-Page 2
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