TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Piccolo Microcontrollers Check for Samples: TMS320F280270, TMS320F280260, TMS320F280230, TMS320F280220 1 TMS320F2802x0 ( Piccolo™) MCUs 1.1 Features 123 • Highlights – High-Efficiency 32-Bit CPU ( TMS320C28x™) – 50-MHz and 40-MHz Devices – Single 3.3-V Supply – Integrated Power-on Resets and Brown-out Resets – Two Internal Zero-pin Oscillators – Up to 22 Multiplexed GPIO Pins – Three 32-Bit CPU Timers – On-Chip Flash, SARAM, OTP Memory – Code-security Module – Serial Port Peripherals (SCI/SPI/I2C) – Enhanced Control Peripherals • Up to 3 Enhanced Pulse Width Modulator (ePWM) Modules for up to 6 Channels • Enhanced Capture (eCAP) • Analog-to-Digital Converter (ADC) • On-Chip Temperature Sensor • Up to 2 Comparators (280270 Only) – 38-Pin and 48-Pin Packages • High-Efficiency 32-Bit CPU ( TMS320C28x™) – 50 MHz (20-ns Cycle Time) – 40 MHz (25-ns Cycle Time) – 16 x 16 and 32 x 32 MAC Operations – 16 x 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly) • Endianness: Little Endian • Low Device and System Cost: – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on and Brown-out Resets – Small Packaging, as Low as 38-Pin Available – Low Power – No Analog Support Pins • Clocking: – Two Internal Zero-pin Oscillators – On-Chip Crystal Oscillator/External Clock Input – Dynamic PLL Ratio Changes Supported – Watchdog Timer Module – Missing Clock Detection Circuitry • Up to 22 Individually Programmable, Multiplexed GPIO Pins With Input Filtering • Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts • Three 32-Bit CPU Timers • Independent 16-Bit Timer in Each ePWM Module • On-Chip Memory – Flash, SARAM, OTP, Boot ROM Available • 128-Bit Security Key/Lock – Protects Secure Memory Blocks – Prevents Firmware Reverse Engineering • Serial Port Peripherals – One SCI (UART) Module – One SPI Module – One Inter-Integrated-Circuit (I2C) Bus • Advanced Emulation Features – Analysis and Breakpoint Functions – Real-Time Debug via Hardware • 2802x0 Packages – 38-Pin DA Thin Shrink Small-Outline Package (TSSOP) – 48-Pin PT Low-Profile Quad Flatpack (LQFP) 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510, XDS560 are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 2 3 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 1.2 www.ti.com Description The F2802x0 Piccolo™ family of microcontrollers provides the power of the C28x™ core coupled with highly integrated control peripherals in low pin-count devices. This family is code-compatible with previous C28x-based code, as well as providing a high level of analog integration. An internal voltage regulator allows for single rail operation. Analog comparators with internal 10-bit references have been added and can be routed directly to control the PWM outputs. The ADC converts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. The ADC interface has been optimized for low overhead/latency. 2 TMS320F2802x0 ( Piccolo™) MCUs Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com Functional Block Diagram Memory Bus 1.3 SPRS810 – APRIL 2012 M0 SARAM 1K x 16 (0-wait) OTP 1K x 16 Secure SARAM 1K/2K x 16 (0-wait) Secure M1 SARAM 1K x 16 (0-wait) Code Security Module FLASH 8K/16K x 16 Secure Boot-ROM 8K x 16 (0-wait) OTP/Flash Wrapper PSWD Memory Bus TRST TCK TDI TMS TDO GPIO 32-bit periph eral bus COMP1OUT COMP2OUT MUX COMP1A COMP1B COMP2A COMP2B COMP C28x 32-bit CPU 3 External Interrupts PIE CPU Timer 0 AIO CPU Timer 1 MUX CPU Timer 2 GPIO Mux XCLKIN OSC1, OSC2, Ext, PLL, LPM, WD X1 X2 LPM Wakeup XRS ADC A7:0 Memory Bus POR/ BOR B7:0 eCAP EPWMxB TZx EPWMxA SCLx SDAx From COMP1OUT, COMP2OUT ECA Px ePWM EPWMSYNCO 32-bit Peripheral Bus I2C (4L FIFO) SPISTEx SPICLKx SPISIMOx SPI (4L FIFO) SPISOMIx SCITXDx SCIRXDx SCI (4L FIFO) 32-Bit Peripheral Bus EPWMSYNCI 16-bit Peripheral Bus VREG GPIO MUX A. Not all peripheral pins are available at the same time due to multiplexing. Figure 1-1. Functional Block Diagram TMS320F2802x0 ( Piccolo™) MCUs Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 3 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 1 ................. 1 ............................................. 1 1.2 Description ........................................... 2 1.3 Functional Block Diagram ........................... 3 Device Overview ........................................ 5 2.1 Device Characteristics ............................... 5 2.2 Memory Maps ........................................ 6 2.3 Brief Descriptions ................................... 11 2.4 Register Map ....................................... 19 2.5 Device Emulation Registers ........................ 20 2.6 VREG/BOR/POR ................................... 20 2.7 System Control ..................................... 22 2.8 Low-power Modes Block ........................... 30 2.9 Thermal Design Considerations .................... 30 Device Pins ............................................. 31 3.1 Pin Assignments .................................... 31 3.2 Terminal Functions ................................. 33 Device Operating Conditions ....................... 38 4.1 Absolute Maximum Ratings ........................ 38 4.2 Recommended Operating Conditions .............. 38 TMS320F2802x0 ( Piccolo™) MCUs 1.1 2 3 4 5 Features ........... 46 ................................. 46 5.2 Clocking ............................................ 48 5.3 Interrupts ............................................ 52 Peripheral Information and Timings ............... 57 6.1 Parameter Information .............................. 57 6.2 Analog-to-Digital Converter (ADC) ................. 58 6.3 Comparator Block .................................. 71 6.4 Serial Peripheral Interface (SPI) .................... 73 6.5 Serial Communications Interface (SCI) ............. 82 6.6 Inter-Integrated Circuit (I2C) ........................ 85 6.7 Enhanced Pulse Width Modulator (ePWM) ........ 88 6.8 Enhanced Capture Module (eCAP) ................ 93 6.9 JTAG Port .......................................... 95 6.10 General-Purpose Input/Output (GPIO) ............. 97 Device and Documentation Support ............. 109 7.1 Device Support .................................... 109 7.2 Documentation Support ........................... 111 7.3 Community Resources ............................ 112 Power, Reset, Clocking, and Interrupts 5.1 6 7 8 Power Sequencing Mechanical Packaging and Orderable Information ............................................ 113 4.3 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) 39 8.1 Thermal Data for Package 113 4.4 Current Consumption 40 8.2 Packaging Information 113 4.5 4 www.ti.com ... ............................... Flash Timing ........................................ Contents ........................ ............................ 44 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 2 Device Overview 2.1 Device Characteristics Table 2-1 lists the features of the TMS320F2802x0 devices. Table 2-1. Hardware Features FEATURE 280270 (50 MHz) TYPE (1) 38-Pin DA TSSOP Package Type 280260 (50 MHz) 48-Pin PT LQFP 38-Pin DA TSSOP 280230 (40 MHz) 48-Pin PT LQFP 38-Pin DA TSSOP 280220 (40 MHz) 48-Pin PT LQFP 38-Pin DA TSSOP 48-Pin PT LQFP Instruction cycle – 20 ns 20 ns 25 ns 25 ns On-chip flash (16-bit word) – 16K 8K 16K 8K On-chip SARAM (16-bit word) – 4K 3K 4K 3K Code security for on-chip flash/SARAM/OTP blocks – Yes Yes Yes Yes Boot ROM (8K x 16) – Yes Yes Yes Yes One-time programmable (OTP) ROM (16-bit word) – 1K 1K 1K 1K ePWM outputs 1 6 (ePWM1/2/3) 6 (ePWM1/2/3) 6 (ePWM1/2/3) 6 (ePWM1/2/3) eCAP inputs 0 1 1 1 1 Yes Watchdog timer – MSPS Conversion Time Channels 12-Bit ADC Temperature Sensor Yes Yes Yes 1.25 1.25 1 1 800 ns 800 ns 1000 ns 1000 ns 6 8 6 8 6 8 6 8 3 Dual Sample-andHold Yes Yes Yes Yes Yes Yes Yes Yes 3 3 3 – – – 32-Bit CPU timers – Comparators w/ Integrated DACs 0 3 Inter-integrated circuit (I2C) 0 1 1 1 1 Serial Peripheral Interface (SPI) 1 1 1 1 1 Serial Communications Interface (SCI) 0 1 1 1 1 2-pin Oscillator 1 1 1 1 0-pin Oscillator 2 2 2 2 Yes Yes Yes Yes 1 Power-on Reset (POR)/ Brown-out Reset (BOR) I/O pins (shared) Digital (GPIO) – Analog (AIO) – 2 20 22 20 6 22 20 6 22 20 6 22 6 External interrupts – 3 3 3 3 Supply voltage (nominal) – 3.3 V 3.3 V 3.3 V 3.3 V Temperature options Product status (1) (2) T: –40°C to 105°C – Yes Yes Yes Yes Yes Yes Yes Yes S: –40°C to 125°C – Yes Yes Yes Yes Yes Yes Yes Yes (2) – TMS TMS TMS TMS A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) and in the peripheral reference guides. See Section 7.1.3, Device and Development Support Tool Nomenclature, for descriptions of device stages. The "TMS" product status denotes a fully qualified production device. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 5 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 2.2 www.ti.com Memory Maps In Figure 2-1 and Figure 2-2, the following apply: • Memory blocks are not to scale. • Peripheral Frame 0, Peripheral Frame 1 and Peripheral Frame 2 memory maps are restricted to data memory only. A user program cannot access these memory maps in program space. • Protected means the order of Write-followed-by-Read operations is preserved rather than the pipeline order. • Certain memory ranges are EALLOW protected against spurious writes after configuration. • Locations 0x3D7C80 – 0x3D7CC0 contain the internal oscillator and ADC calibration routines. These locations are not programmable by the user. 6 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Prog Space Data Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 0x00 2000 Reserved 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) 0x00 7000 0x00 8000 Reserved Peripheral Frame 2 (4K x 16, Protected) L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0x00 8800 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 7CE0 0x3D 7E80 0x3D 7EB0 0x3D 7FFF 0x3D 8000 Reserved Calibration Data Get_mode function Reserved Calibration Data Reserved PARTID Reserved 0x3F 4000 FLASH (16K x 16, 4 Sectors, Secure Zone + ECSL) 0x3F 7FF8 128-Bit Password 0x3F 8000 L0 SARAM (2K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0x3F 8800 Reserved 0x3F E000 Boot ROM (8K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 2-1. 280270/280230 Memory Map Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 7 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Prog Space Data Space 0x00 0000 M0 Vector RAM (Enabled if VMAP = 0) 0x00 0040 M0 SARAM (1K x 16, 0-Wait) 0x00 0400 0x00 0800 0x00 0D00 0x00 0E00 M1 SARAM (1K x 16, 0-Wait) Peripheral Frame 0 PIE Vector - RAM (256 x 16) (Enabled if VMAP = 1, ENPIE = 1) Reserved Peripheral Frame 0 0x00 2000 Reserved 0x00 6000 Peripheral Frame 1 (4K x 16, Protected) 0x00 7000 0x00 8000 Reserved Peripheral Frame 2 (4K x 16, Protected) L0 SARAM (1K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0x00 8400 Reserved 0x3D 7800 User OTP (1K x 16, Secure Zone + ECSL) 0x3D 7C00 Reserved 0x3D 7C80 0x3D 7CC0 0x3D 7CE0 0x3D 7E80 0x3D 7EB0 0x3D 7FFF 0x3D 8000 Calibration Data Get_mode function Reserved Calibration Data Reserved PARTID Reserved 0x3F 6000 FLASH (8K x 16, 2 Sectors, Secure Zone + ECSL) 0x3F 7FF8 0x3F 8000 128-Bit Password L0 SARAM (1K x 16) (0-Wait, Secure Zone + ECSL, Dual Mapped) 0x3F 8400 Reserved 0x3F E000 Boot ROM (8K x 16, 0-Wait) 0x3F FFC0 Vector (32 Vectors, Enabled if VMAP = 1) Figure 2-2. 280260/280220 Memory Map 8 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 2-2. Addresses of Flash Sectors in F280270/280230 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 4000 – 0x3F 4FFF Sector D (4K x 16) 0x3F 5000 – 0x3F 5FFF Sector C (4K x 16) 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7F7F Sector A (4K x 16) 0x3F 7F80 – 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 – 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 – 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) Table 2-3. Addresses of Flash Sectors in F280260/280220 ADDRESS RANGE PROGRAM AND DATA SPACE 0x3F 6000 – 0x3F 6FFF Sector B (4K x 16) 0x3F 7000 – 0x3F 7F7F Sector A (4K x 16) 0x3F 7F80 – 0x3F 7FF5 Program to 0x0000 when using the Code Security Module 0x3F 7FF6 – 0x3F 7FF7 Boot-to-Flash Entry Point (program branch instruction here) 0x3F 7FF8 – 0x3F 7FFF Security Password (128-Bit) (Do not program to all zeros) NOTE • When the code-security passwords are programmed, all addresses between 0x3F 7F80 and 0x3F 7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F 7F80 through 0x3F 7FEF may be used for code or data. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data and should not contain program code. Table 2-4 shows how to handle these memory locations. Table 2-4. Impact of Using the Code Security Module ADDRESS 0x3F 7F80 – 0x3F 7FEF 0x3F 7FF0 – 0x3F 7FF5 FLASH CODE SECURITY ENABLED Fill with 0x0000 CODE SECURITY DISABLED Application code and data Reserved for data only Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 9 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/read peripheral block protected. The protected mode makes sure that all accesses to these blocks happen as written. Because of the pipeline, a write immediately followed by a read to different memory locations, will appear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheral applications where the user expected the write to occur first (as written). The CPU supports a block protection mode where a region of memory can be protected so that operations occur as written (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it protects the selected zones. The wait-states for the various spaces in the memory map area are listed in Table 2-5. Table 2-5. Wait-states AREA WAIT-STATES (CPU) M0 and M1 SARAMs 0-wait COMMENTS Fixed Peripheral Frame 0 0-wait Peripheral Frame 1 0-wait (writes) Cycles can be extended by peripheral generated ready. 2-wait (reads) Back-to-back write operations to Peripheral Frame 1 registers will incur a 1-cycle stall (1-cycle delay). 0-wait (writes) Fixed. Cycles cannot be extended by the peripheral. Peripheral Frame 2 2-wait (reads) L0 SARAM 0-wait data and program OTP FLASH Assumes no CPU conflicts Programmable Programmed via the Flash registers. 1-wait minimum 1-wait is minimum number of wait states allowed. Programmable Programmed via the Flash registers. 0-wait Paged min 1-wait Random min Random ≥ Paged 10 FLASH Password 16-wait fixed Boot-ROM 0-wait Device Overview Wait states of password locations are fixed. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 2.3 SPRS810 – APRIL 2012 Brief Descriptions 2.3.1 CPU The 2802x0 (C28x) family is a member of the TMS320C2000™ microcontroller (MCU) platform. The C28x-based controllers have the same 32-bit fixed-point architecture as existing C28x MCUs. It is a very efficient C/C++ engine, enabling users to develop not only their system control software in a high-level language, but also enabling development of math algorithms using C/C++. The device is as efficient at MCU math tasks as it is at system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x 32-bit MAC 64-bit processing capabilities enable the controller to handle higher numerical resolution problems efficiently. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency. The device has an 8-leveldeep protected pipeline with pipelined memory accesses. This pipelining enables it to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance. 2.3.2 Memory Bus (Harvard Bus Architecture) As with many MCU-type devices, multiple busses are used to move data between the memories and peripherals and the CPU. The memory bus architecture contains a program read bus, data read bus, and data write bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed Harvard Bus, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus prioritize memory accesses. Generally, the priority of memory bus accesses can be summarized as follows: Highest: Data Writes (Simultaneous data and program writes cannot occur on the memory bus.) Program Writes (Simultaneous data and program writes cannot occur on the memory bus.) Data Reads Lowest: 2.3.3 Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.) Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.) Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) MCU family of devices, the devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals. Three versions of the peripheral bus are supported. One version supports only 16-bit accesses (called peripheral frame 2). Another version supports both 16- and 32-bit accesses (called peripheral frame 1). 2.3.4 Real-Time JTAG and Analysis The devices implement the standard IEEE 1149.1 JTAG (1) interface for in-circuit based debug. Additionally, the devices support real-time mode of operation allowing modification of the contents of memory, peripheral, and register locations while the processor is running and executing code and servicing interrupts. The user can also single step through non-time-critical code while enabling timecritical interrupts to be serviced without interference. The device implements the real-time mode in (1) IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 11 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com hardware within the CPU. This is a feature unique to the 28x family of devices, requiring no software monitor. Additionally, special analysis hardware is provided that allows setting of hardware breakpoint or data/address watch-points and generating various user-selectable break events when a match occurs. These devices do not support boundary scan; however, IDCODE and BYPASS features are available if the following considerations are taken into account. The IDCODE does not come by default. The user needs to go through a sequence of SHIFT IR and SHIFT DR state of JTAG to get the IDCODE. For BYPASS instruction, the first shifted DR value would be 1. 2.3.5 Flash The F280270/280230 devices contain 16K x 16 of embedded flash memory, segregated into four 4K x 16 sectors. The F280260/280220 devices contain 8K x 16 of embedded flash memory, segregated into two 4K x 16 sectors. All devices also contain a single 1K x 16 of OTP memory at address range 0x3D 7800 – 0x3D 7BFF. The user can individually erase, program, and validate a flash sector while leaving other sectors untouched. However, it is not possible to use one sector of the flash or the OTP to execute flash algorithms that erase/program other sectors. Special memory pipelining is provided to enable the flash module to achieve higher performance. The flash/OTP is mapped to both program and data space; therefore, it can be used to execute code or store data information. Addresses 0x3F 7FF0 – 0x3F 7FF5 are reserved for data variables and should not contain program code. NOTE The Flash and OTP wait-states can be configured by the application. This allows applications running at slower frequencies to configure the flash to use fewer wait-states. Flash effective performance can be improved by enabling the flash pipeline mode in the Flash options register. With this mode enabled, effective performance of linear code execution will be much faster than the raw performance indicated by the wait-state configuration alone. The exact performance gain when using the Flash pipeline mode is application-dependent. For more information on the Flash options, Flash wait-state, and OTP wait-state registers, see the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3). 2.3.6 M0, M1 SARAMs All devices contain these two blocks of single access memory, each 1K x 16 in size. The stack pointer points to the beginning of block M1 on reset. The M0 and M1 blocks, like all other memory blocks on C28x devices, are mapped to both program and data space. Hence, the user can use M0 and M1 to execute code or for data variables. The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages. 2.3.7 L0 SARAM The device contains up to 2K x 16 of single-access RAM. See the device-specific memory map figures in Section 2.2 to ascertain the exact size for a given device. This block is mapped to both program and data space. 2.3.8 Boot ROM The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell the bootloader software what boot mode to use on power up. The user can select to boot normally or to download new software from an external connection or to select boot software that is programmed in the internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use in math-related algorithms. 12 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 2-6. Boot Mode Selection MODE GPIO37/TDO GPIO34/COMP2OUT TRST 3 1 1 0 GetMode 2 1 0 0 Wait (see Section 2.3.9 for description) 1 0 1 0 SCI 0 0 0 0 Parallel IO EMU x x 1 Emulation Boot 2.3.8.1 MODE Emulation Boot When the emulator is connected, the GPIO37/TDO pin cannot be used for boot mode selection. In this case, the boot ROM detects that an emulator is connected and uses the contents of two reserved SARAM locations in the PIE vector table to determine the boot mode. If the content of either location is invalid, then the Wait boot option is used. All boot mode options can be accessed in emulation boot. 2.3.8.2 GetMode The default behavior of the GetMode option is to boot to flash. This behavior can be changed to another boot option by programming two locations in the OTP. If the content of either OTP location is invalid, then boot to flash is used. One of the following loaders can be specified: SCI, SPI, I2C, or OTP. 2.3.8.3 Peripheral Pins Used by the Bootloader Table 2-7 shows which GPIO pins are used by each peripheral bootloader. Refer to the GPIO mux table to see if these conflict with any of the peripherals you would like to use in your application. Table 2-7. Peripheral Bootload Pins BOOTLOADER SCIRXDA (GPIO28) SCITXDA (GPIO29) Parallel Boot Data (GPIO[7:0]) 28x Control (GPIO16) Host Control (GPIO12) SPI SPISIMOA (GPIO16) SPISOMIA (GPIO17) SPICLKA (GPIO18) SPISTEA (GPIO19) I2C SDAA (GPIO32) (1) SCLA (GPIO33) (1) (1) 2.3.9 PERIPHERAL LOADER PINS SCI GPIO pins 32 and 33 may not be available on your device package. On these devices, this bootload option is unavailable. Security The devices support high levels of security to protect the user firmware from being reverse engineered. The security features a 128-bit password (hardcoded for 16 wait-states), which the user programs into the flash. One code security module (CSM) is used to protect the flash/OTP and the L0/L1 SARAM blocks. The security feature prevents unauthorized users from examining the memory contents via the JTAG port, executing code from external memory or trying to boot-load some undesirable software that would export the secure memory contents. To enable access to the secure blocks, the user must write the correct 128bit KEY value that matches the value stored in the password locations within the Flash. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 13 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com In addition to the CSM, the emulation code security logic (ECSL) has been implemented to prevent unauthorized users from stepping through secure code. Any code or data access to flash, user OTP, or L0 memory while the emulator is connected will trip the ECSL and break the emulation connection. To allow emulation of secure code, while maintaining the CSM protection against secure memory reads, the user must write the correct value into the lower 64 bits of the KEY register, which matches the value stored in the lower 64 bits of the password locations within the flash. Note that dummy reads of all 128 bits of the password in the flash must still be performed. If the lower 64 bits of the password locations are all ones (unprogrammed), then the KEY value does not need to match. When initially debugging a device with the password locations in flash programmed (i.e., secured), the CPU will start running and may execute an instruction that performs an access to a protected ECSL area. If this happens, the ECSL will trip and cause the emulator connection to be cut. The solution is to use the Wait boot option. This will sit in a loop around a software breakpoint to allow an emulator to be connected without tripping security. The user can then exit this mode once the emulator is connected by using one of the emulation boot options as described in the TMS320x2802x Piccolo Boot ROM Reference Guide (literature number SPRUFN6). Piccolo devices do not support a hardware wait-inreset mode. NOTE • When the code-security passwords are programmed, all addresses between 0x3F7F80 and 0x3F7FF5 cannot be used as program code or data. These locations must be programmed to 0x0000. • If the code security feature is not used, addresses 0x3F7F80 through 0x3F7FEF may be used for code or data. Addresses 0x3F7FF0 – 0x3F7FF5 are reserved for data and should not contain program code. The 128-bit password (at 0x3F 7FF8 – 0x3F 7FFF) must not be programmed to zeros. Doing so would permanently lock the device. Disclaimer Code Security Module Disclaimer THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE. TI DOES NOT, HOWEVER, WARRANT OR REPRESENT THAT THE CSM CANNOT BE COMPROMISED OR BREACHED OR THAT THE DATA STORED IN THE ASSOCIATED MEMORY CANNOT BE ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT AS SET FORTH ABOVE, TI MAKES NO WARRANTIES OR REPRESENTATIONS CONCERNING THE CSM OR OPERATION OF THIS DEVICE, INCLUDING ANY IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL TI BE LIABLE FOR ANY CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, OR PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING IN ANY WAY OUT OF YOUR USE OF THE CSM OR THIS DEVICE, WHETHER OR NOT TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, BUT ARE NOT LIMITED TO LOSS OF DATA, LOSS OF GOODWILL, LOSS OF USE OR INTERRUPTION OF BUSINESS OR OTHER ECONOMIC LOSS. 14 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 2.3.10 Peripheral Interrupt Expansion (PIE) Block The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE block can support up to 96 peripheral interrupts. On the F2802x0, 29 of the possible 96 interrupts are used by peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt lines (INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user. The vector is automatically fetched by the CPU on servicing the interrupt. It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual interrupt can be enabled/disabled within the PIE block. 2.3.11 External Interrupts (XINT1–XINT3) The devices support three masked external interrupts (XINT1–XINT3). Each of the interrupts can be selected for negative, positive, or both negative and positive edge triggering and can also be enabled/disabled. These interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is detected. This counter can be used to accurately time stamp the interrupt. There are no dedicated pins for the external interrupts. XINT1, XINT2, and XINT3 interrupts can accept inputs from GPIO0–GPIO31 pins. 2.3.12 Internal Zero Pin Oscillators, Oscillator, and PLL The device can be clocked by either of the two internal zero-pin oscillators, an external oscillator, or by a crystal attached to the on-chip oscillator circuit (48-pin devices only). A PLL is provided supporting up to 12 input-clock-scaling ratios. The PLL ratios can be changed on-the-fly in software, enabling the user to scale back on operating frequency if lower power operation is desired. See Section 5.2.1, Device Clock Table, for timing details. The PLL block can be set in bypass mode. 2.3.13 Watchdog Each device contains two watchdogs: CPU-Watchdog that monitors the core and NMI-Watchdog that is a missing clock-detect circuit. The user software must regularly reset the CPU-watchdog counter within a certain time frame; otherwise, the CPU-watchdog generates a reset to the processor. The CPU-watchdog can be disabled if necessary. The NMI-Watchdog engages only in case of a clock failure and can either generate an interrupt or a device reset. 2.3.14 Peripheral Clocking The clocks to each individual peripheral can be enabled/disabled to reduce power consumption when a peripheral is not in use. Additionally, the system clock to the serial ports (except I2C) can be scaled relative to the CPU clock. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 15 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 2.3.15 Low-power Modes The devices are full static CMOS devices. Three low-power modes are provided: IDLE: Place CPU in low-power mode. Peripheral clocks may be turned off selectively and only those peripherals that need to function during IDLE are left operating. An enabled interrupt from an active peripheral or the watchdog timer will wake the processor from IDLE mode. STANDBY: Turns off clock to CPU and peripherals. This mode leaves the oscillator and PLL functional. An external interrupt event will wake the processor and the peripherals. Execution begins on the next valid cycle after detection of the interrupt event HALT: This mode basically shuts down the device and places it in the lowest possible power consumption mode. If the internal zero-pin oscillators are used as the clock source, the HALT mode turns them off, by default. To keep these oscillators from shutting down, the INTOSCnHALTI bits in CLKCTL register may be used. The zero-pin oscillators may thus be used to clock the CPU-watchdog in this mode. If the on-chip crystal oscillator is used as the clock source, it is shut down in this mode. A reset or an external signal (through a GPIO pin) or the CPU-watchdog can wake the device from this mode. The CPU clock (OSCCLK) and WDCLK should be from the same clock source before attempting to put the device into HALT or STANDBY. 2.3.16 Peripheral Frames 0, 1, 2 (PFn) The device segregates peripherals into three sections. The mapping of peripherals is as follows: PF0: PF1: PF2: 16 Device Overview PIE: PIE Interrupt Enable and Control Registers Plus PIE Vector Table Flash: Flash Waitstate Registers Timers: CPU-Timers 0, 1, 2 Registers CSM: Code Security Module KEY Registers ADC: ADC Result Registers GPIO: GPIO MUX Configuration and Control Registers ePWM: Enhanced Pulse Width Modulator Module and Registers eCAP: Enhanced Capture Module and Registers Comparators: Comparator Modules SYS: System Control Registers SCI: Serial Communications Interface (SCI) Control and RX/TX Registers SPI: Serial Port Interface (SPI) Control and RX/TX Registers ADC: ADC Status, Control, and Configuration Registers I2C: Inter-Integrated Circuit Module and Registers XINT: External Interrupt Registers Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 2.3.17 General-Purpose Input/Output (GPIO) Multiplexer Most of the peripheral signals are multiplexed with general-purpose input/output (GPIO) signals. This enables the user to use a pin as GPIO if the peripheral signal or function is not used. On reset, GPIO pins are configured as inputs. The user can individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles. This is to filter unwanted noise glitches. The GPIO signals can also be used to bring the device out of specific low-power modes. 2.3.18 32-Bit CPU-Timers (0, 1, 2) CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. It is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 2 can be clocked by any one of the following: • SYSCLKOUT (default) • Internal zero-pin oscillator 1 (INTOSC1) • Internal zero-pin oscillator 2 (INTSOC2) • External clock source 2.3.19 Control Peripherals The devices support the following peripherals that are used for embedded control and communication: ePWM: The enhanced PWM peripheral supports independent/complementary PWM generation, adjustable dead-band generation for leading/trailing edges, latched/cycle-by-cycle trip mechanism. The type 1 module found on 2802x0 devices also supports increased dead-band resolution, enhanced SOC and interrupt generation, and advanced triggering including trip functions based on comparator outputs. eCAP: The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. ADC: The ADC block is a 12-bit converter. It has up to 8 single-ended channels pinned out, depending on the device. It contains two sample-and-hold units for simultaneous sampling. Comparator: Each comparator block consists of one analog comparator along with an internal 10-bit reference for supplying one input of the comparator. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 17 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 2.3.20 Serial Port Peripherals The devices support the following serial communication peripherals: 18 SPI: The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multi-device communications are supported by the master/slave operation of the SPI. The SPI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. SCI: The serial communications interface is a two-wire asynchronous serial port, commonly known as UART. The SCI contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. I2C: The inter-integrated circuit (I2C) module provides an interface between a MCU and other devices compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit data to/from the MCU through the I2C module. The I2C contains a 4-level receive and transmit FIFO for reducing interrupt servicing overhead. Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 2.4 SPRS810 – APRIL 2012 Register Map The devices contain three peripheral register spaces. The spaces are categorized as follows: Peripheral Frame 0: These are peripherals that are mapped directly to the CPU memory bus. See Table 2-8. Peripheral Frame 1: These are peripherals that are mapped to the 32-bit peripheral bus. See Table 2-9. Peripheral Frame 2: These are peripherals that are mapped to the 16-bit peripheral bus. See Table 2-10. Table 2-8. Peripheral Frame 0 Registers (1) ADDRESS RANGE SIZE (×16) EALLOW PROTECTED (2) Device Emulation Registers 0x00 0880 – 0x00 0984 261 Yes System Power Control Registers 0x00 0985 – 0x00 0987 3 Yes FLASH Registers (3) 0x00 0A80 – 0x00 0ADF 96 Yes Code Security Module Registers 0x00 0AE0 – 0x00 0AEF 16 Yes ADC registers (0 wait read only) 0x00 0B00 – 0x00 0B0F 16 No CPU–TIMER0/1/2 Registers 0x00 0C00 – 0x00 0C3F 64 No PIE Registers 0x00 0CE0 – 0x00 0CFF 32 No PIE Vector Table 0x00 0D00 – 0x00 0DFF 256 No NAME (1) (2) (3) Registers in Frame 0 support 16-bit and 32-bit accesses. If registers are EALLOW protected, then writes cannot be performed until the EALLOW instruction is executed. The EDIS instruction disables writes to prevent stray code or pointers from corrupting register contents. The Flash Registers are also protected by the Code Security Module (CSM). Table 2-9. Peripheral Frame 1 Registers NAME ADDRESS RANGE SIZE (×16) Comparator 1 registers 0x00 6400 – 0x00 641F 32 (1) Comparator 2 registers 0x00 6420 – 0x00 643F 32 (1) ePWM1 registers 0x00 6800 – 0x00 683F 64 (1) ePWM2 registers 0x00 6840 – 0x00 687F 64 (1) ePWM3 registers 0x00 6880 – 0x00 68BF 64 (1) eCAP1 registers 0x00 6A00 – 0x00 6A1F 32 No GPIO registers 0x00 6F80 – 0x00 6FFF 128 (1) EALLOW PROTECTED (1) Some registers are EALLOW protected. See the module reference guide for more information. Table 2-10. Peripheral Frame 2 Registers NAME ADDRESS RANGE SIZE (×16) EALLOW PROTECTED System Control Registers 0x00 7010 – 0x00 702F 32 Yes SPI-A Registers 0x00 7040 – 0x00 704F 16 No SCI-A Registers 0x00 7050 – 0x00 705F 16 No NMI Watchdog Interrupt Registers 0x00 7060 – 0x00 706F 16 Yes External Interrupt Registers 0x00 7070 – 0x00 707F 16 Yes ADC Registers 0x00 7100 – 0x00 717F 128 (1) I2C-A Registers 0x00 7900 – 0x00 793F 64 (1) (1) Some registers are EALLOW protected. See the module reference guide for more information. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 19 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 2.5 www.ti.com Device Emulation Registers These registers are used to control the protection mode of the C28x CPU and to monitor some critical device signals. The registers are defined in Table 2-11. Table 2-11. Device Emulation Registers NAME ADDRESS RANGE SIZE (x16) 0x0880 0x0881 2 Device Configuration Register 0x3D 7FFF 1 Part ID Register DEVICECNF PARTID CLASSID 0x0882 REVID 2.6 0x0883 1 1 EALLOW PROTECTED DESCRIPTION Class ID Register Revision ID Register Yes TMS320F280270PT 0x000F TMS320F280270DA 0x000E TMS320F280260PT 0x0007 TMS320F280260DA 0x0006 TMS320F280230PT 0x000D TMS320F280230DA 0x000C TMS320F280220PT 0x0005 TMS320F280220DA 0x0004 TMS320F280270PT/DA 0x00C7 TMS320F280260PT/DA 0x00C7 TMS320F280230PT/DA 0x00C7 TMS320F280220PT/DA 0x00C7 0x0000 - Silicon Rev. 0 - TMS 0x0001 - Silicon Rev. A - TMS No No No VREG/BOR/POR Although the core and I/O circuitry operate on two different voltages, these devices have an on-chip voltage regulator (VREG) to generate the VDD voltage from the VDDIO supply. This eliminates the cost and space of a second external regulator on an application board. Additionally, internal power-on reset (POR) and brown-out reset (BOR) circuits monitor both the VDD and VDDIO rails during power-up and run mode. 2.6.1 On-chip Voltage Regulator (VREG) A linear regulator generates the core voltage (VDD) from the VDDIO supply. Therefore, although capacitors are required on each VDD pin to stabilize the generated voltage, power need not be supplied to these pins to operate the device. Conversely, the VREG can be disabled, should power or redundancy be the primary concern of the application. 2.6.1.1 Using the On-chip VREG To utilize the on-chip VREG, the VREGENZ pin should be tied low and the appropriate recommended operating voltage should be supplied to the VDDIO and VDDA pins. In this case, the VDD voltage needed by the core logic will be generated by the VREG. Each VDD pin requires on the order of 1.2 μF (minimum) capacitance for proper regulation of the VREG. These capacitors should be located as close as possible to the VDD pins. 2.6.1.2 Disabling the On-chip VREG To conserve power, it is also possible to disable the on-chip VREG and supply the core logic voltage to the VDD pins with a more efficient external regulator. To enable this option, the VREGENZ pin must be tied high. 20 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 2.6.2 SPRS810 – APRIL 2012 On-chip Power-On Reset (POR) and Brown-Out Reset (BOR) Circuit Two on-chip supervisory circuits, the power-on reset (POR) and the brown-out reset (BOR) remove the burden of monitoring the VDD and VDDIO supply rails from the application board. The purpose of the POR is to create a clean reset throughout the device during the entire power-up procedure. The trip point is a looser, lower trip point than the BOR, which watches for dips in the VDD or VDDIO rail during device operation. The POR function is present on both VDD and VDDIO rails at all times. After initial device powerup, the BOR function is present on VDDIO at all times, and on VDD when the internal VREG is enabled (VREGENZ pin is tied low). Both functions tie the XRS pin low when one of the voltages is below their respective trip point. Additionally, when the internal voltage regulator is enabled, an over-voltage protection circuit will tie XRS low if the VDD rail rises above its trip point. See Section 4.3 for the various trip points as well as the delay time for the device to release the XRS pin after the under/over-voltage condition is removed. Figure 2-3 shows the VREG, POR, and BOR. To disable both the VDD and VDDIO BOR functions, a bit is provided in the BORCFG register. Refer to the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for details. In I/O Pin Out (Force Hi-Z When High) DIR (0 = Input, 1 = Output) SYSRS Internal Weak PU SYSCLKOUT Deglitch Filter XRS Sync RS MCLKRS PLL + Clocking Logic XRS Pin C28 Core JTAG TCK Detect Logic VREGHALT (A) WDRST (B) PBRS A. B. POR/BOR Generating Module On-Chip Voltage Regulator (VREG) VREGENZ WDRST is the reset signal from the CPU-watchdog. PBRS is the reset signal from the POR/BOR module. Figure 2-3. VREG + POR + BOR + Reset Signal Connectivity Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 21 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 2.7 www.ti.com System Control This section describes the oscillator and clocking mechanisms, the watchdog function and the low power modes. Table 2-12. PLL, Clocking, Watchdog, and Low-Power Mode Registers NAME DESCRIPTION (1) ADDRESS SIZE (x16) BORCFG 0x00 0985 1 BOR Configuration Register XCLK 0x00 7010 1 XCLKOUT Control PLLSTS 0x00 7011 1 PLL Status Register CLKCTL 0x00 7012 1 Clock Control Register PLLLOCKPRD 0x00 7013 1 PLL Lock Period INTOSC1TRIM 0x00 7014 1 Internal Oscillator 1 Trim Register INTOSC2TRIM 0x00 7016 1 Internal Oscillator 2 Trim Register LOSPCP 0x00 701B 1 Low-Speed Peripheral Clock Prescaler Register PCLKCR0 0x00 701C 1 Peripheral Clock Control Register 0 PCLKCR1 0x00 701D 1 Peripheral Clock Control Register 1 LPMCR0 0x00 701E 1 Low Power Mode Control Register 0 PCLKCR3 0x00 7020 1 Peripheral Clock Control Register 3 PLLCR 0x00 7021 1 PLL Control Register SCSR 0x00 7022 1 System Control and Status Register WDCNTR 0x00 7023 1 Watchdog Counter Register WDKEY 0x00 7025 1 Watchdog Reset Key Register WDCR 0x00 7029 1 Watchdog Control Register (1) 22 All registers in this table are EALLOW protected. Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Figure 2-4 shows the various clock domains that are discussed. Figure 2-5 shows the various clock sources (both internal and external) that can provide a clock for device operation. SYSCLKOUT LOSPCP (System Ctrl Regs) PCLKCR0/1/3 (System Ctrl Regs) Clock Enables SPI-A, SCI-A I/O C28x Core CLKIN LSPCLK Peripheral Registers PF2 Peripheral Registers PF1 Peripheral Registers PF1 Peripheral Registers PF2 Clock Enables eCAP1 I/O GPIO Mux Clock Enables I/O ePWM1/.../3 Clock Enables I2C-A I/O Clock Enables 16 Ch 12-Bit ADC PF2 PF0 Analog GPIO Mux Clock Enables 6 A. ADC Registers COMP1/2 COMP Registers PF1 CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 2-4. Clock and Reset Domains Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 23 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com CLKCTL[WDCLKSRCSEL] Internal OSC 1 (10 MHz) (A) INTOSC1TRIM Reg 0 OSC1CLK OSCCLKSRC1 WDCLK CPU-Watchdog (OSC1CLK on XRS reset) OSCE 1 CLKCTL[INTOSC1OFF] 1 = Turn OSC Off CLKCTL[OSCCLKSRCSEL] CLKCTL[INTOSC1HALT] WAKEOSC 1 = Ignore HALT 0 Internal OSC2CLK OSC 2 (10 MHz) (A) INTOSC2TRIM Reg OSCCLK PLL Missing-Clock-Detect Circuit (OSC1CLK on XRS reset) (B) 1 OSCE CLKCTL[TRM2CLKPRESCALE] CLKCTL[TMR2CLKSRCSEL] 1 = Turn OSC Off 10 CLKCTL[INTOSC2OFF] 11 1 = Ignore HALT Prescale /1, /2, /4, /8, /16 01, 10, 11 CPUTMR2CLK 01 1 00 CLKCTL[INTOSC2HALT] SYSCLKOUT OSCCLKSRC2 0 0 = GPIO38 1 = GPIO19 XCLK[XCLKINSEL] SYNC Edge Detect CLKCTL[OSCCLKSRC2SEL] CLKCTL[XCLKINOFF] 0 XCLKIN 1 GPIO19 or GPIO38 0 XCLKIN X1 EXTCLK (Crystal) OSC XTAL WAKEOSC (Oscillators enabled when this signal is high) X2 CLKCTL[XTALOSCOFF] A. B. 0 = OSC on (default on reset) 1 = Turn OSC off Register loaded from TI OTP-based calibration function. See Section 2.7.4 for details on missing clock detection. Figure 2-5. Clock Tree 24 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 2.7.1 SPRS810 – APRIL 2012 Internal Zero Pin Oscillators The F2802x0 devices contain two independent internal zero pin oscillators. By default both oscillators are turned on at power up, and internal oscillator 1 is the default clock source at this time. For power savings, unused oscillators may be powered down by the user. The center frequency of these oscillators is determined by their respective oscillator trim registers, written to in the calibration routine as part of the boot ROM execution. See Section 5.2.1, Device Clock Table, for more information on these oscillators. 2.7.2 Crystal Oscillator Option The typical specifications for the external quartz crystal (fundamental mode, parallel resonant) are listed in Table 2-13. Furthermore, ESR range = 30 to 150 Ω. Table 2-13. Typical Specifications for External Quartz Crystal (1) (1) FREQUENCY (MHz) Rd (Ω) CL1 (pF) CL2 (pF) 5 2200 18 18 10 470 15 15 15 0 15 15 20 0 12 12 Cshunt should be less than or equal to 5 pF. XCLKIN/GPIO19/38 Turn off XCLKIN path in CLKCTL register A. X1 X2 Rd CL1 Crystal CL2 X1/X2 pins are available in 48-pin package only. Figure 2-6. Using the On-chip Crystal Oscillator NOTE 1. CL1 and CL2 are the total capacitance of the circuit board and components excluding the IC and crystal. The value is usually approximately twice the value of the crystal's load capacitance. 2. The load capacitance of the crystal is described in the crystal specifications of the manufacturers. 3. TI recommends that customers have the resonator/crystal vendor characterize the operation of their device with the MCU chip. The resonator/crystal vendor has the equipment and expertise to tune the tank circuit. The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. XCLKIN/GPIO19/38 External Clock Signal (Toggling 0−VDDIO) X1 X2 NC Figure 2-7. Using a 3.3-V External Oscillator Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 25 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 2.7.3 www.ti.com PLL-Based Clock Module The devices have an on-chip, PLL-based clock module. This module provides all the necessary clocking signals for the device, as well as control for low-power mode entry. The PLL has a 4-bit ratio control PLLCR[DIV] to select different CPU clock rates. The watchdog module should be disabled before writing to the PLLCR register. It can be re-enabled (if need be) after the PLL module has stabilized, which takes 1 ms. The input clock and PLLCR[DIV] bits should be chosen in such a way that the output frequency of the PLL (VCOCLK) is at least 50 MHz. Table 2-14. PLL Settings PLLCR[DIV] VALUE (1) (1) (2) (3) SYSCLKOUT (CLKIN) (2) PLLSTS[DIVSEL] = 0 or 1 (3) PLLSTS[DIVSEL] = 2 PLLSTS[DIVSEL] = 3 0000 (PLL bypass) OSCCLK/4 (Default) (1) OSCCLK/2 OSCCLK 0001 (OSCCLK * 1)/4 (OSCCLK * 1)/2 (OSCCLK * 1)/1 0010 (OSCCLK * 2)/4 (OSCCLK * 2)/2 (OSCCLK * 2)/1 0011 (OSCCLK * 3)/4 (OSCCLK * 3)/2 (OSCCLK * 3)/1 0100 (OSCCLK * 4)/4 (OSCCLK * 4)/2 (OSCCLK * 4)/1 0101 (OSCCLK * 5)/4 (OSCCLK * 5)/2 (OSCCLK * 5)/1 0110 (OSCCLK * 6)/4 (OSCCLK * 6)/2 (OSCCLK * 6)/1 0111 (OSCCLK * 7)/4 (OSCCLK * 7)/2 (OSCCLK * 7)/1 1000 (OSCCLK * 8)/4 (OSCCLK * 8)/2 (OSCCLK * 8)/1 1001 (OSCCLK * 9)/4 (OSCCLK * 9)/2 (OSCCLK * 9)/1 1010 (OSCCLK * 10)/4 (OSCCLK * 10)/2 (OSCCLK * 10)/1 1011 (OSCCLK * 11)/4 (OSCCLK * 11)/2 (OSCCLK * 11)/1 1100 (OSCCLK * 12)/4 (OSCCLK * 12)/2 (OSCCLK * 12)/1 The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog reset only. A reset issued by the debugger or the missing clock detect logic has no effect. This register is EALLOW protected. See the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for more information. By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /1.) PLLSTS[DIVSEL] must be 0 before writing to the PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1. Table 2-15. CLKIN Divide Options 26 Device Overview PLLSTS [DIVSEL] CLKIN DIVIDE 0 /4 1 /4 2 /2 3 /1 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 The PLL-based clock module provides four modes of operation: • INTOSC1 (Internal Zero-pin Oscillator 1): This is the on-chip internal oscillator 1. This can provide the clock for the Watchdog block, core and CPU-Timer 2 • INTOSC2 (Internal Zero-pin Oscillator 2): This is the on-chip internal oscillator 2. This can provide the clock for the Watchdog block, core and CPU-Timer 2. Both INTOSC1 and INTOSC2 can be independently chosen for the Watchdog block, core and CPU-Timer 2. • Crystal/Resonator Operation: The on-chip (crystal) oscillator enables the use of an external crystal/resonator attached to the device to provide the time base. The crystal/resonator is connected to the X1/X2 pins. Some devices may not have the X1/X2 pins. See Table 3-1 for details. • External Clock Source Operation: If the on-chip (crystal) oscillator is not used, this mode allows it to be bypassed. The device clocks are generated from an external clock source input on the XCLKIN pin. Note that the XCLKIN is multiplexed with GPIO19 or GPIO38 pin. The XCLKIN input can be selected as GPIO19 or GPIO38 via the XCLKINSEL bit in XCLK register. The CLKCTL[XCLKINOFF] bit disables this clock input (forced low). If the clock source is not used or the respective pins are used as GPIOs, the user should disable at boot time. Before changing clock sources, ensure that the target clock is present. If a clock is not present, then that clock source must be disabled (using the CLKCTL register) before switching clocks. Table 2-16. Possible PLL Configuration Modes REMARKS PLLSTS[DIVSEL] CLKIN AND SYSCLKOUT Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block is disabled in this mode. This can be useful to reduce system noise and for low power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass) before entering this mode. The CPU clock (CLKIN) is derived directly from the input clock on either X1/X2, X1 or XCLKIN. 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 0, 1 2 3 OSCCLK/4 OSCCLK/2 OSCCLK/1 0, 1 2 3 OSCCLK * n/4 OSCCLK * n/2 OSCCLK * n/1 PLL MODE PLL Off PLL Bypass is the default PLL configuration upon power-up or after an external reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or PLL Bypass while the PLL locks to a new frequency after the PLLCR register has been modified. In this mode, the PLL itself is bypassed but the PLL is not turned off. PLL Enable 2.7.4 Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the PLLCR the device will switch to PLL Bypass mode until the PLL locks. Loss of Input Clock (NMI Watchdog Function) The 2802x0 devices may be clocked from either one of the internal zero-pin oscillators (INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of the clock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL will issue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals at a typical frequency of 1–5 MHz. When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt. Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be fired immediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, the Missing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detect the input clock failure and initiate necessary corrective action such as switching over to an alternative clock source (if available) or initiate a shut-down procedure for the system. If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after a preprogrammed time interval. Figure 2-8 shows the interrupt mechanisms involved. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 27 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Set Clear XRS NMINT Generate Interrupt Pulse When Input = 1 1 0 NMIFLG[CLOCKFAIL] Clear Latch Clear Set 0 NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT NMICFG[CLOCKFAIL] XRS NMIFLGFRC[CLOCKFAIL] SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] NMI Watchdog NMIRS See System Control Section Figure 2-8. NMI-watchdog 2.7.5 CPU-Watchdog Module The CPU-watchdog module on the 2802x0 device is similar to the one used on the 281x/280x/283xx devices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user must disable the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resets the watchdog counter. Figure 2-9 shows the various functional blocks within the watchdog module. Normally, when the input clocks are present, the CPU-watchdog counter decrements to initiate a CPUwatchdog reset or WDINT interrupt. However, when the external input clock fails, the CPU-watchdog counter stops decrementing (i.e., the watchdog counter does not change with the limp-mode clock). NOTE The CPU-watchdog is different from the NMI watchdog. It is the legacy watchdog that is present in all 28x devices. NOTE Applications in which the correct CPU operating frequency is absolutely critical should implement a mechanism by which the MCU will be held in reset, should the input clocks ever fail. For example, an R-C circuit may be used to trigger the XRS pin of the MCU, should the capacitor ever get fully charged. An I/O pin may be used to discharge the capacitor on a periodic basis to prevent it from getting fully charged. Such a circuit would also help in detecting failure of the flash memory. 28 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR(7:0) WDCLK Watchdog Prescaler /512 WDCLK 8-Bit Watchdog Counter CLR Clear Counter Internal Pullup WDKEY(7:0) Watchdog 55 + AA Key Detector WDRST Generate Output Pulse WDINT (512 OSCCLKs) Good Key XRS Core-reset WDCR (WDCHK[2:0]) WDRST(A) A. 1 0 Bad WDCHK Key SCSR (WDENINT) 1 The WDRST signal is driven low for 512 OSCCLK cycles. Figure 2-9. CPU-watchdog Module The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode. In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the CPU-watchdog. This module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 2.8, Low-power Modes Block, for more details. In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode. In HALT mode, the CPU-watchdog can be used to wake up the device through a device reset. Device Overview Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 29 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 2.8 www.ti.com Low-power Modes Block Table 2-17 summarizes the various modes. Table 2-17. Low-power Modes EXIT (1) MODE LPMCR0(1:0) OSCCLK CLKIN SYSCLKOUT IDLE 00 On On On XRS, CPU-watchdog interrupt, any enabled interrupt STANDBY 01 On (CPU-watchdog still running) Off Off XRS, CPU-watchdog interrupt, GPIO Port A signal, debugger (2) 1X Off (on-chip crystal oscillator and PLL turned off, zero-pin oscillator and CPU-watchdog state dependent on user code.) Off Off XRS, GPIO Port A signal, debugger (2), CPU-watchdog HALT (3) (1) (2) (3) The Exit column lists which signals or under what conditions the low power mode is exited. A low signal, on any of the signals, exits the low power condition. This signal must be kept low long enough for an interrupt to be recognized by the device. Otherwise, the low-power mode will not be exited and the device will go back into the indicated low power mode. The JTAG port can still function even if the CPU clock (CLKIN) is turned off. The WDCLK must be active for the device to go into HALT mode. The various low-power modes operate as follows: IDLE Mode: This mode is exited by any enabled interrupt that is recognized by the processor. The LPM block performs no tasks during this mode as long as the LPMCR0(LPM) bits are set to 0,0. STANDBY Mode: Any GPIO port A signal (GPIO[31:0]) can wake the device from STANDBY mode. The user must select which signal(s) will wake the device in the GPIOLPMSEL register. The selected signal(s) are also qualified by the OSCCLK before waking the device. The number of OSCCLKs is specified in the LPMCR0 register. HALT Mode: CPU-watchdog, XRS, and any GPIO port A signal (GPIO[31:0]) can wake the device from HALT mode. The user selects the signal in the GPIOLPMSEL register. NOTE The low-power modes do not affect the state of the output pins (PWM pins included). They will be in whatever state the code left them in when the IDLE instruction was executed. See the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for more details. 2.9 Thermal Design Considerations Based on the end application design and operational profile, the IDD and IDDIO currents could vary. Systems that exceed the recommended maximum power dissipation in the end product may require additional thermal enhancements. Ambient temperature (TA) varies with the end application and product design. The critical factor that affects reliability and functionality is TJ, the junction temperature, not the ambient temperature. Hence, care should be taken to keep TJ within the specified limits. Tcase should be measured to estimate the operating junction temperature TJ. Tcase is normally measured at the center of the package top-side surface. The thermal application reports IC Package Thermal Metrics (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices (literature number SPRA963) help to understand the thermal metrics and definitions. 30 Device Overview Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 3 Device Pins 3.1 Pin Assignments 36 35 34 33 32 31 30 29 28 27 26 25 GPIO33/SCLA/EPWMSYNCO/ADCSOCBO VDDIO VREGENZ VSS VDD GPIO32/SDAA/EPWMSYNCI/ADCSOCAO TEST GPIO0/EPWM1A GPIO1/EPWM1B/COMP1OUT GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 Figure 3-1 shows the 48-pin PT low-profile quad flatpack (LQFP) pin assignments. Figure 3-2 shows the 38-pin DA thin shrink small-outline package (TSSOP) pin assignments. GPIO2/EPWM2A GPIO3/EPWM2B/COMP2OUT GPIO4/EPWM3A GPIO5/EPWM3B/ECAP1 GPIO6/EPWMSYNCI/EPWMSYNCO GPIO7/SCIRXDA VDD VSS 24 23 22 21 20 19 18 17 16 15 14 13 GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO38/XCLKIN (TCK) GPIO37 (TDO) GPIO36 (TMS) GPIO35 (TDI) GPIO34/COMP2OUT VSSA ADCINB6/AIO14 ADCINB4/COMP2B/AIO12 VSSA ADCINB2/COMP1B/AIO10 ADCINB1 TRST XRS ADCINA6/AIO6 ADCINA4/COMP2A/AIO4 VSSA VSSA ADCINA1 ADCINA2/COMP1A/AIO2 VREFHI VDDA VSSA/VREFLO GPIO29/SCITXDA/SCLA/TZ3 1 2 3 4 5 6 7 8 9 10 11 12 X1 X2 GPIO12/TZ1/SCITXDA GPIO28/SCIRXDA/SDAA/TZ2 37 38 39 40 41 42 43 44 45 46 47 48 Figure 3-1. 2802x0 48-Pin PT LQFP (Top View) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Device Pins 31 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com VDD VSS VREGENZ VDDIO GPIO2/EPWM2A GPIO3/EPWM2B GPIO4/EPWM3A GPIO5/EPWM3B/ECAP1 GPIO6/EPWMSYNCI/EPWMSYNCO GPIO7/SCIRXDA VDD VSS GPIO12/TZ1/SCITXDA GPIO28/SCIRXDA/SDAA/TZ2 GPIO29/SCITXDA/SCLA/TZ3 TRST XRS ADCINA6/AIO6 ADCINA4/AIO4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 TEST GPIO0/EPWM1A GPIO1/EPWM1B/COMP1OUT GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3 GPIO19/XCLKIN/SPISTEA/SCIRXDA/ECAP1 GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO38/XCLKIN (TCK) GPIO37 (TDO) GPIO36 (TMS) GPIO35 (TDI) GPIO34 ADCINB6/AIO14 ADCINB4/AIO12 ADCINB2/COMP1B/AIO10 VSSA/VREFLO VDDA VREFHI ADCINA2/COMP1A/AIO2 Figure 3-2. 2802x0 38-Pin DA TSSOP (Top View) 32 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 3.2 SPRS810 – APRIL 2012 Terminal Functions Table 3-1 describes the signals. With the exception of the JTAG pins, the GPIO function is the default at reset, unless otherwise mentioned. The peripheral signals that are listed under them are alternate functions. Some peripheral functions may not be available in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled on a per-pin basis. This feature only applies to the GPIO pins. The pullups on the PWM pins are not enabled at reset. The pullups on other GPIO pins are enabled upon reset. The AIO pins do not have an internal pullup. NOTE: When the on-chip VREG is used, the GPIO19, GPIO34, GPIO35, GPIO36, GPIO37, and GPIO38 pins could glitch during power up. If this is unacceptable in an application, 1.8 V could be supplied externally. There is no power-sequencing requirement when using an external 1.8-V supply. However, if the 3.3-V transistors in the level-shifting output buffers of the I/O pins are powered prior to the 1.9-V transistors, it is possible for the output buffers to turn on, causing a glitch to occur on the pin during power up. To avoid this behavior, power the VDD pins prior to or simultaneously with the VDDIO pins, ensuring that the VDD pins have reached 0.7 V before the VDDIO pins reach 0.7 V. Table 3-1. Terminal Functions (1) TERMINAL I/O/Z DESCRIPTION 16 I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. NOTE: TRST is an active high test pin and must be maintained low at all times during normal device operation. An external pulldown resistor is required on this pin. The value of this resistor should be based on drive strength of the debugger pods applicable to the design. A 2.2-kΩ resistor generally offers adequate protection. Since this is application-specific, it is recommended that each target board be validated for proper operation of the debugger and the application. (↓) TCK See GPIO38 I See GPIO38. JTAG test clock with internal pullup (↑) TMS See GPIO36 I See GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. (↑) TDI See GPIO35 I See GPIO35. JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. (↑) TDO See GPIO37 O/Z See GPIO37. JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK. (8-mA drive) NAME PT PIN # DA PIN # JTAG TRST 2 FLASH TEST 30 38 I/O Test Pin. Reserved for TI. Must be left unconnected. O/Z See GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. I See GPIO19 and GPIO38. External oscillator input. Pin source for the clock is controlled by the XCLKINSEL bit in the XCLK register, GPIO38 is the default selection. This pin feeds a clock from an external 3.3-V oscillator. In this case, the X1 pin, if available, must be tied to GND and the on-chip crystal oscillator must be disabled via bit 14 in the CLKCTL register. If a crystal/resonator is used, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. NOTE: Designs that use the GPIO38/TCK/XCLKIN pin to supply an external clock for normal device operation may need to incorporate some hooks to disable this path during debug using the JTAG connector. This is to prevent contention with the TCK signal, which is active during JTAG debug sessions. The zero-pin internal oscillators may be used during this time to clock the device. CLOCK XCLKOUT XCLKIN (1) See GPIO18 See GPIO19 and GPIO38 I = Input, O = Output, Z = High Impedance, OD = Open Drain, ↑ = Pullup, ↓ = Pulldown Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Device Pins 33 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL PT PIN # DA PIN # I/O/Z X1 45 – I On-chip crystal-oscillator input. To use this oscillator, a quartz crystal or a ceramic resonator must be connected across X1 and X2. In this case, the XCLKIN path must be disabled by bit 13 in the CLKCTL register. If this pin is not used, it must be tied to GND. (I) X2 46 – O On-chip crystal-oscillator output. A quartz crystal or a ceramic resonator must be connected across X1 and X2. If X2 is not used, it must be left unconnected. (O) NAME DESCRIPTION RESET XRS 3 17 I/OD Device Reset (in) and Watchdog Reset (out). Piccolo devices have a built-in poweron-reset (POR) and brown-out-reset (BOR) circuitry. As such, no external circuitry is needed to generate a reset pulse. During a power-on or brown-out condition, this pin is driven low by the device. See Section 4.3 for thresholds of the POR/BOR block. This pin is also driven low by the MCU when a watchdog reset occurs. During watchdog reset, the XRS pin is driven low for the watchdog reset duration of 512 OSCCLK cycles. If need be, an external circuitry may also drive this pin to assert a device reset. In this case, it is recommended that this pin be driven by an open-drain device. An R-C circuit must be connected to this pin for noise immunity reasons. Regardless of the source, a device reset causes the device to terminate execution. The program counter points to the address contained at the location 0x3FFFC0. When reset is deactivated, execution begins at the location designated by the program counter. The output buffer of this pin is an open-drain with an internal pullup. (I/OD) ADC, COMPARATOR, ANALOG I/O ADCINA6 AIO6 4 18 I I/O ADC Group A, Channel 6 input Digital AIO 6 ADCINA4 COMP2A AIO4 5 19 I I I/O ADC Group A, Channel 4 input Comparator Input 2A (available in 48-pin device only) Digital AIO 4 ADCINA2 COMP1A AIO2 9 20 I I I/O ADC Group A, Channel 2 input Comparator Input 1A Digital AIO 2 ADCINA1 8 – I ADC Group A, Channel 1 input ADC Group B, Channel 6 input Digital AIO 14 ADCINB6 AIO14 17 26 I I/O ADCINB4 COMP2B AIO12 16 25 I I I/O ADC Group B, Channel 4 input Comparator Input 2B (available in 48-pin device only) Digital AIO12 ADCINB2 COMP1B AIO10 14 24 I I I/O ADC Group B, Channel 2 input Comparator Input 1B Digital AIO 10 ADCINB1 13 – I ADC Group B, Channel 1 input 34 Device Pins Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL I/O/Z DESCRIPTION PT PIN # DA PIN # VDDA 11 22 Analog Power Pin. Tie with a 2.2-µF capacitor (typical) close to the pin. VSSA 6 – Analog Ground Pin VSSA 7 – Analog Ground Pin VSSA VREFLO 12 23 VREFHI 10 21 VSSA 15 – Analog Ground Pin VSSA 18 – Analog Ground Pin VDD 32 1 VDD 43 11 CPU and Logic Digital Power Pins – no supply source needed when using internal VREG. Tie with 1.2 µF (minimum) ceramic capacitor (10% tolerance) to ground when using internal VREG. Higher value capacitors may be used, but could impact supplyrail ramp-up time. VDDIO 35 4 VSS 33 2 VSS 44 12 NAME CPU AND I/O POWER Analog Ground Pin ADC Low Reference (always tied to ground) I ADC External Reference – only used when in ADC external reference mode. See Section 6.2.1, Analog-to-Digital Converter Device-Specific Information. I Digital I/O and Flash Power Pin – Single Supply source when VREG is enabled. Tie with a 2.2-µF capacitor (typical) close to the pin. Digital Ground Pins VOLTAGE REGULATOR CONTROL SIGNAL VREGENZ 34 3 I Internal VREG Enable/Disable. Pull low to enable the internal voltage regulator (VREG), pull high to disable VREG. GPIO AND PERIPHERAL SIGNALS GPIO0 29 37 I/O/Z General-purpose input/output 0 EPWM1A O Enhanced PWM1 Output A – – – – – – GPIO1 28 36 I/O/Z EPWM1B O – – COMP1OUT O GPIO2 37 5 EPWM2A I/O/Z O – General-purpose input/output 1 Enhanced PWM1 Output B Direct output of Comparator 1 General-purpose input/output 2 Enhanced PWM2 Output A – – – GPIO3 38 6 EPWM2B I/O/Z O – General-purpose input/output 3 Enhanced PWM2 Output B – COMP2OUT GPIO4 O 39 7 EPWM3A I/O/Z O Direct output of Comparator 2 (available in 48-pin device only) General-purpose input/output 4 Enhanced PWM3 output A – – – – (1) (1) The GPIO function (shown in bold italics) is the default at reset. The peripheral signals that are listed under them are alternate functions. For JTAG pins that have the GPIO functionality multiplexed, the input path to the GPIO block is always valid. The output path from the GPIO block and the path to the JTAG block from a pin is enabled/disabled based on the condition of the TRST signal. See the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for details. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Device Pins 35 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME PT PIN # DA PIN # I/O/Z 40 8 I/O/Z GPIO5 EPWM3B O – DESCRIPTION General-purpose input/output 5 Enhanced PWM3 output B – ECAP1 I/O GPIO6 41 9 I/O/Z – Enhanced Capture input/output 1 General-purpose input/output 6 – EPWMSYNCI I External ePWM sync pulse input EPWMSYNCO O External ePWM sync pulse output GPIO7 42 10 I/O/Z – General-purpose input/output 7 – SCIRXDA I – SCI-A receive data – GPIO12 47 13 I/O/Z General-purpose input/output 12 TZ1 I Trip Zone input 1 SCITXDA O SCI-A transmit data – – GPIO16 27 35 SPISIMOA I/O/Z I/O – General-purpose input/output 16 SPI slave in, master out – TZ2 I GPIO17 26 34 SPISOMIA I/O/Z I/O – Trip Zone input 2 General-purpose input/output 17 SPI-A slave out, master in – TZ3 I GPIO18 24 32 I/O/Z Trip zone input 3 General-purpose input/output 18 SPICLKA I/O SPI-A clock input/output SCITXDA O SCI-A transmit XCLKOUT GPIO19 25 33 O/Z Output clock derived from SYSCLKOUT. XCLKOUT is either the same frequency, one-half the frequency, or one-fourth the frequency of SYSCLKOUT. This is controlled by bits 1:0 (XCLKOUTDIV) in the XCLK register. At reset, XCLKOUT = SYSCLKOUT/4. The XCLKOUT signal can be turned off by setting XCLKOUTDIV to 3. The mux control for GPIO18 must also be set to XCLKOUT for this signal to propogate to the pin. I/O/Z General-purpose input/output 19 External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken not to enable this path for clocking if it is being used for the other periperhal functions XCLKIN SPISTEA I/O SCIRXDA I ECAP1 GPIO28 SCIRXDA SDAA 14 Enhanced Capture input/output 1 I/O/Z General-purpose input/output 28 I I Device Pins SCI-A receive I/O I/OD TZ2 36 48 SPI-A slave transmit enable input/output SCI receive data I2C data open-drain bidirectional port Trip zone input 2 Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 3-1. Terminal Functions(1) (continued) TERMINAL NAME GPIO29 PT PIN # DA PIN # I/O/Z 1 15 I/O/Z SCITXDA O SCLA I/OD TZ3 GPIO32 I 31 – SDAA DESCRIPTION General-purpose input/output 29. SCI transmit data I2C clock open-drain bidirectional port Trip zone input 3 I/O/Z General-purpose input/output 32 I/OD I2C data open-drain bidirectional port EPWMSYNCI I Enhanced PWM external sync pulse input ADCSOCAO O ADC start-of-conversion A GPIO33 36 – SCLA I/O/Z General-Purpose Input/Output 33 I/OD I2C clock open-drain bidirectional port EPWMSYNCO O Enhanced PWM external synch pulse output ADCSOCBO O ADC start-of-conversion B GPIO34 19 27 COMP2OUT I/O/Z O – – 20 28 TDI GPIO36 21 29 I/O/Z I 22 30 TDO GPIO38 I/O/Z I TMS GPIO37 Direct output of Comparator 2. COMP2OUT signal is not available in the DA package. – – GPIO35 General-Purpose Input/Output 34 23 31 General-Purpose Input/Output 35 JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK General-Purpose Input/Output 36 JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. I/O/Z General-Purpose Input/Output 37 O/Z JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK (8 mA drive) I/O/Z General-Purpose Input/Output 38 TCK I JTAG test clock with internal pullup XCLKIN I External Oscillator Input. The path from this pin to the clock block is not gated by the mux function of this pin. Care must be taken to not enable this path for clocking if it is being used for the other functions. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Device Pins 37 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 4 Device Operating Conditions 4.1 Absolute Maximum Ratings (1) (2) Supply voltage range, VDDIO (I/O and Flash) with respect to VSS –0.3 V to 4.6 V Supply voltage range, VDD with respect to VSS –0.3 V to 2.5 V Analog voltage range, VDDA with respect to VSSA –0.3 V to 4.6 V Input voltage range, VIN (3.3 V) –0.3 V to 4.6 V Output voltage range, VO –0.3 V to 4.6 V Input clamp current, IIK (VIN < 0 or VIN > VDDIO) (3) ±20 mA Output clamp current, IOK (VO < 0 or VO > VDDIO) ±20 mA Junction temperature range, TJ (4) Storage temperature range, Tstg (1) (2) (3) (4) 4.2 –40°C to 150°C (4) –65°C to 150°C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Section 4.2 is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage values are with respect to VSS, unless otherwise noted. Continuous clamp current per pin is ± 2 mA. Long-term high-temperature storage and/or extended use at maximum temperature conditions may result in a reduction of overall device life. For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). Recommended Operating Conditions Device supply voltage, I/O, VDDIO (1) (2) Device supply voltage CPU, VDD (When internal VREG is disabled and 1.8 V is supplied externally) MIN NOM 2.97 1.71 2.97 3.3 Supply ground, VSS Analog ground, VSSA 3.63 V 1.8 1.995 V 3.63 Low-level output sink current, VOL = VOL(MAX), IOL (4) V 40 280270, 280260 2 50 2 VDDIO + 0.3 V VSS – 0.3 0.8 V All GPIO/AIO pins –4 mA Group 2 (3) –8 mA 4 mA 8 mA All GPIO/AIO pins Group 2 Junction temperature, TJ V 2 Low-level input voltage, VIL (3.3 V) High-level output source current, VOH = VOH(MIN), IOH V 280230, 280220 High-level input voltage, VIH (3.3 V) 38 3.3 0 Device clock frequency (system clock) (3) (4) UNIT 0 Analog supply voltage, VDDA (1) (1) (2) MAX (3) T version –40 105 S version –40 125 MHz °C VDDIO and VDDA should be maintained within ~0.3 V of each other. A tolerance of ±10% may be used for VDDIO if the BOR is not used. See the TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200, TMS320F280270, TMS320F280260, TMS320F280230, TMS320F280220 Piccolo MCU Silicon Errata (literature number SPRZ292) for more information. VDDIO tolerance is ±5% if the BOR is enabled. Group 2 pins are as follows: GPIO16, GPIO17, GPIO18, GPIO19, GPIO28, GPIO29, GPIO36, GPIO37 TA (Ambient temperature) is product- and application-dependent and can go up to the specified TJ max of the device. See Section 2.9, Thermal Design Considerations. Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 4.3 SPRS810 – APRIL 2012 Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) (1) PARAMETER VOH High-level output voltage VOL Low-level output voltage IIL IIH Input current (low level) Input current (high level) TEST CONDITIONS IOH = IOH MAX MIN MAX UNIT IOH = 50 μA V VDDIO – 0.2 IOL = IOL MAX 0.4 All GPIO –80 –140 –205 XRS pin –225 –290 –360 Pin with pullup enabled VDDIO = 3.3 V, VIN = 0 V Pin with pulldown enabled VDDIO = 3.3 V, VIN = 0 V ±2 Pin with pullup enabled VDDIO = 3.3 V, VIN = VDDIO ±2 Pin with pulldown enabled VDDIO = 3.3 V, VIN = VDDIO IOZ Output current, pullup or pulldown disabled CI Input capacitance VDDIO BOR trip point V μA μA 28 50 VO = VDDIO or 0 V 80 ±2 2 Falling VDDIO 2.42 VDDIO BOR hysteresis (1) TYP 2.4 2.65 pF 3.135 35 Supervisor reset release delay time Time after BOR/POR/OVR event is removed to XRS release VREG VDD output Internal VREG on 400 μA V mV 800 μs 1.9 V When the on-chip VREG is used, its output is monitored by the POR/BOR circuit, which will reset the device should the core voltage (VDD) go out of range. Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 39 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 4.4 www.ti.com Current Consumption Table 4-1. TMS320F280230/F280220 Current Consumption at 40-MHz SYSCLKOUT VREG ENABLED MODE TEST CONDITIONS TYP VREG DISABLED IDDIO (1) IDDA (2) (3) (3) MAX TYP MAX IDD TYP (3) IDDIO MAX TYP (3) (1) IDDA MAX TYP (3) (2) MAX Operational (Flash) The following peripheral clocks are enabled: • ePWM1/2/3 • eCAP1 • SCI-A • SPI-A • ADC • I2C • COMP1/2 • CPU Timer0/1/2 All PWM pins are toggled at 40 kHz. All I/O pins are left unconnected. (4) Code is running out of flash with 1 waitstate. XCLKOUT is turned off. 70 mA 80 mA 13 mA 18 mA 62 mA 70 mA 15 mA 18 mA 13 mA 18 mA IDLE Flash is powered down. XCLKOUT is turned off. All peripheral clocks are off. 13 mA 16 mA 53 μA 58 μA 15 mA 17 mA 120 μA 400 μA 53 μA 58 μA STANDBY Flash is powered down. Peripheral clocks are off. 3 mA 6 mA 10 μA 15 μA 3 mA 6 mA 120 μA 400 μA 10 μA 15 μA HALT Flash is powered down. Peripheral clocks are off. Input clock is disabled. (5) 50 μA 10 μA 15 μA 15 μA 10 μA 15 μA (1) (2) (3) (4) (5) 40 25 μA IDDIO current is dependent on the electrical loading on the I/O pins. In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. The TYP numbers are applicable over room temperature and nominal voltage. The following is done in a loop: • Data is continuously transmitted out of SPI-A and SCI-A ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing continuous conversion. • COMP1/2 are continuously switching voltages. • GPIO17 is toggled. If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 4-2. TMS320F280270/F280260 Current Consumption at 50-MHz SYSCLKOUT VREG ENABLED MODE TEST CONDITIONS IDDIO (1) VREG DISABLED IDDA (2) IDDIO (1) IDD IDDA (2) TYP (3) MAX TYP (3) MAX TYP (3) MAX TYP (3) MAX TYP (3) MAX Operational (Flash) The following peripheral clocks are enabled: • ePWM1/2/3 • eCAP1 • SCI-A • SPI-A • ADC • I2C • COMP1/2 • CPU Timer0/1/2 All PWM pins are toggled at 40 kHz. All I/O pins are left unconnected. (4) Code is running out of flash with 1 waitstate. XCLKOUT is turned off. 80 mA 90 mA 13 mA 18 mA 71 mA 80 mA 15 mA 18 mA 13 mA 18 mA IDLE Flash is powered down. XCLKOUT is turned off. All peripheral clocks are off. 16 mA 19 mA 64 μA 69 μA 17 mA 20 mA 120 μA 400 μA 64 μA 69 μA STANDBY Flash is powered down. Peripheral clocks are off. 4 mA 7 mA 10 μA 15 μA 4 mA 7 mA 120 μA 400 μA 10 μA 15 μA HALT Flash is powered down. Peripheral clocks are off. Input clock is disabled. (5) 50 μA 10 μA 15 μA 15 μA 10 μA 15 μA (1) (2) (3) (4) (5) 25 μA IDDIO current is dependent on the electrical loading on the I/O pins. In order to realize the IDDA currents shown for IDLE, STANDBY, and HALT, clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register. The TYP numbers are applicable over room temperature and nominal voltage. The following is done in a loop: • Data is continuously transmitted out of SPI-A and SCI-A ports. • The hardware multiplier is exercised. • Watchdog is reset. • ADC is performing continuous conversion. • COMP1/2 are continuously switching voltages. • GPIO17 is toggled. If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the on-chip crystal oscillator. NOTE The peripheral - I/O multiplexing implemented in the device prevents all available peripherals from being used at the same time. This is because more than one peripheral function may share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the same time, although such a configuration is not useful. If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 41 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 4.4.1 www.ti.com Reducing Current Consumption The 2802x0 devices incorporate a method to reduce the device current consumption. Since each peripheral unit has an individual clock-enable bit, significant reduction in current consumption can be achieved by turning off the clock to any peripheral module that is not used in a given application. Furthermore, any one of the three low-power modes could be taken advantage of to reduce the current consumption even further. Table 4-3 indicates the typical reduction in current consumption achieved by turning off the clocks. Table 4-3. Typical Current Consumption by Various Peripherals (at 60 MHz) (1) (1) (2) (3) PERIPHERAL MODULE (2) IDD CURRENT REDUCTION (mA) ADC 2 (3) I2C 3 ePWM 2 eCAP 2 SCI 2 SPI 2 COMP/DAC 1 CPU-TIMER 1 Internal zero-pin oscillator 0.5 All peripheral clocks (except CPU Timer clocks) are disabled upon reset. Writing to/reading from peripheral registers is possible only after the peripheral clocks are turned on. For peripherals with multiple instances, the current quoted is per module. For example, the 2 mA value quoted for ePWM is for one ePWM module. This number represents the current drawn by the digital portion of the ADC module. Turning off the clock to the ADC module results in the elimination of the current drawn by the analog portion of the ADC (IDDA) as well. NOTE IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off. NOTE The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is 45 mA, typical. To arrive at the IDD current for a given application, the current-drawn by the peripherals (enabled by that application) must be added to the baseline IDD current. Following are other methods to reduce power consumption further: • The flash module may be powered down if code is run off SARAM. This results in a current reduction of 18 mA (typical) in the VDD rail and 13 mA (typical) in the VDDIO rail. • Savings in IDDIO may be realized by disabling the pullups on pins that assume an output function. 42 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 4.4.2 SPRS810 – APRIL 2012 Current Consumption Graphs (VREG Enabled) Operational Current vs Frequency 100 Operational Current (mA) 90 80 70 60 50 40 30 20 10 0 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) IDDIO (m A) IDDA Figure 4-1. Typical Operational Current Versus Frequency (F2802x0) Operational Pow er vs Frequency Operational Power (mW) 450 400 350 300 250 200 10 15 20 25 30 35 40 45 50 55 60 SYSCLKOUT (MHz) Figure 4-2. Typical Operational Power Versus Frequency (F2802x0) Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 43 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 4.5 www.ti.com Flash Timing Table 4-4. Flash/OTP Endurance for T Temperature Material (1) ERASE/PROGRAM TEMPERATURE Nf Flash endurance for the array (write/erase cycles) 0°C to 105°C (ambient) NOTP OTP endurance for the array (write cycles) 0°C to 30°C (ambient) (1) MIN TYP 20000 50000 MAX UNIT cycles 1 write Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 4-5. Flash/OTP Endurance for S Temperature Material (1) ERASE/PROGRAM TEMPERATURE Nf NOTP (1) Flash endurance for the array (write/erase cycles) 0°C to 125°C (ambient) OTP endurance for the array (write cycles) 0°C to 30°C (ambient) MIN TYP 20000 50000 MAX UNIT cycles 1 write Write/erase operations outside of the temperature ranges indicated are not specified and may affect the endurance numbers. Table 4-6. Flash Parameters at 50-MHz SYSCLKOUT TEST CONDITIONS PARAMETER IDDP (1) VDD current consumption during Erase/Program cycle (1) VDDIO current consumption during Erase/Program cycle IDDIOP (1) VDDIO current consumption during Erase/Program cycle IDDIOP (1) MIN VREG disabled TYP MAX 70 UNIT mA 60 VREG enabled 110 mA Typical parameters as seen at room temperature including function call overhead, with all peripherals off. Table 4-7. Flash Parameters at 40-MHz SYSCLKOUT TEST CONDITIONS PARAMETER IDDP (1) VDD current consumption during Erase/Program cycle (1) VDDIO current consumption during Erase/Program cycle IDDIOP (1) VDDIO current consumption during Erase/Program cycle IDDIOP (1) MIN VREG disabled TYP MAX 60 UNIT mA 60 VREG enabled 100 mA Typical parameters as seen at room temperature including function call overhead, with all peripherals off. Table 4-8. Flash Program/Erase Time TEST CONDITIONS PARAMETER Program Time Erase Time (1) (1) MIN TYP MAX UNIT 50 μs 4K Sector 125 ms 4K Sector 2 16-Bit Word s The on-chip flash memory is in an erased state when the device is shipped from TI. As such, erasing the flash memory is not required prior to programming, when programming the device for the first time. However, the erase operation is needed on all subsequent programming operations. Table 4-9. Flash/OTP Access Timing PARAMETER MIN MAX UNIT ta(fp) Paged Flash access time 40 ns ta(fr) Random Flash access time 40 ns ta(OTP) OTP access time 60 ns 44 Device Operating Conditions Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 4-10. Minimum Required Flash/OTP Wait-States at Different Frequencies SYSCLKOUT (MHz) (1) SYSCLKOUT (ns) PAGE WAIT-STATE (1) RANDOM WAIT-STATE (1) OTP WAIT-STATE 50 20 1 1 2 45 22.22 1 1 2 40 25 1 1 2 35 28.57 1 1 2 30 33.33 1 1 1 25 40 0 1 1 Random wait-state must be ≥ 1. The equations to compute the Flash page wait-state and random wait-state in Table 4-10 are as follows: ù éæ t a( f · p ) ö ÷ - 1ú round up to the next highest integer Flash Page Wait State = êç úû êëçè t c (SCO ) ÷ø éæ t a(f ×r) ö ù ÷ - 1ú round up to the next highest integer, or 1, whichever is larger Flash Random Wait State = êç êëçè t c(SCO) ÷ø úû The equation to compute the OTP wait-state in Table 4-10 is as follows: éæ t a(OTP) ö ù ÷ - 1ú round up to the next highest integer, or 1, whichever is larger OTP Wait State = êç êëçè t c(SCO) ÷ø úû Device Operating Conditions Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 45 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 5 Power, Reset, Clocking, and Interrupts 5.1 Power Sequencing There is no power sequencing requirement needed to ensure the device is in the proper state after reset or to prevent the I/Os from glitching during power up/down (GPIO19, GPIO34–38 do not have glitch-free I/Os). No voltage larger than a diode drop (0.7 V) above VDDIO should be applied to any digital pin (for analog pins, it is 0.7 V above VDDA) prior to powering up the device. Furthermore, VDDIO and VDDA should always be within 0.3 V of each other. Voltages applied to pins on an unpowered device can bias internal p-n junctions in unintended ways and produce unpredictable results. VDDIO, VDDA (3.3 V) VDD (1.8 V) INTOSC1 tINTOSCST X1/X2 tOSCST (B) (A) XCLKOUT User-code dependent tw(RSL1) XRS (D) Address/data valid, internal boot-ROM code execution phase Address/Data/ Control (Internal) td(EX) th(boot-mode)(C) Boot-Mode Pins User-code execution phase User-code dependent GPIO pins as input Peripheral/GPIO function Based on boot code Boot-ROM execution starts (E) GPIO pins as input (state depends on internal PU/PD) I/O Pins User-code dependent A. B. C. D. E. Upon power up, SYSCLKOUT is OSCCLK/4. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. XCLKOUT = OSCCLK/16 during this phase. Boot ROM configures the DIVSEL bits for /1 operation. XCLKOUT = OSCCLK/4 during this phase. Note that XCLKOUT will not be visible at the pin until explicitly configured by user code. After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Using the XRS pin is optional due to the on-chip power-on reset (POR) circuitry. The internal pullup/pulldown will take effect when BOR is driven high. Figure 5-1. Power-on Reset 46 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 5-1. Reset (XRS) Timing Requirements MIN th(boot-mode) Hold time for boot-mode pins tw(RSL2) Pulse duration, XRS low on warm reset NOM MAX UNIT 1000tc(SCO) cycles 32tc(OSCCLK) cycles Table 5-2. Reset (XRS) Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS tw(RSL1) Pulse duration, XRS driven by device tw(WDRS) Pulse duration, reset pulse generated by watchdog td(EX) Delay time, address/data valid after XRS high tINTOSCST Start up time, internal zero-pin oscillator tOSCST (1) (1) MIN TYP MAX UNIT μs 600 On-chip crystal-oscillator start-up time 512tc(OSCCLK) cycles 32tc(OSCCLK) cycles 1 3 μs 10 ms Dependent on crystal/resonator and board design. INTOSC1 X1/X2 XCLKOUT User-Code Dependent tw(RSL2) XRS Address/Data/ Control (Internal) td(EX) User-Code Execution Boot-ROM Execution Starts Boot-Mode Pins User-Code Execution Phase Peripheral/GPIO Function GPIO Pins as Input th(boot-mode)(A) Peripheral/GPIO Function User-Code Execution Starts I/O Pins User-Code Dependent GPIO Pins as Input (State Depends on Internal PU/PD) User-Code Dependent A. After reset, the Boot ROM code samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 5-2. Warm Reset Power, Reset, Clocking, and Interrupts Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 47 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Figure 5-3 shows an example for the effect of writing into PLLCR register. In the first phase, PLLCR = 0x0004 and SYSCLKOUT = OSCCLK x 2. The PLLCR is then written with 0x0008. Right after the PLLCR register is written, the PLL lock-up phase begins. During this phase, SYSCLKOUT = OSCCLK/2. After the PLL lock-up is complete, SYSCLKOUT reflects the new operating frequency, OSCCLK x 4. OSCCLK Write to PLLCR SYSCLKOUT OSCCLK * 2 OSCCLK * 4 OSCCLK/2 (CPU frequency while PLL is stabilizing with the desired frequency. This period (PLL lock-up time tp) is 1 ms long.) (Current CPU Frequency) (Changed CPU frequency) Figure 5-3. Example of Effect of Writing Into PLLCR Register 5.2 Clocking 5.2.1 Device Clock Table This section provides the timing requirements and switching characteristics for the various clock options available on the 2802x0 MCUs. Table 5-3 and Table 5-4 list the cycle times of various clocks. Table 5-3. 2802x0 Clock Table and Nomenclature (40-MHz Devices) MIN SYSCLKOUT LSPCLK (1) ADC clock (1) (2) tc(SCO), Cycle time Frequency tc(LCO), Cycle time MAX UNIT 25 500 ns 2 40 MHz 40 MHz 40 MHz MAX UNIT 500 ns 50 MHz 50 MHz 25 100 (2) 10 (2) Frequency tc(ADCCLK), Cycle time NOM ns 25 ns Frequency Lower LSPCLK will reduce device power consumption. This is the default reset value if SYSCLKOUT = 40 MHz. Table 5-4. 2802x0 Clock Table and Nomenclature (50-MHz Devices) MIN SYSCLKOUT LSPCLK (1) ADC clock (1) (2) 48 tc(SCO), Cycle time Frequency tc(LCO), Cycle time 2 20 80 (2) 12.5 (2) Frequency tc(ADCCLK), Cycle time NOM 20 ns 20 Frequency ns 50 MHz Lower LSPCLK will reduce device power consumption. This is the default reset value if SYSCLKOUT = 50 MHz. Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 5-5. Device Clocking Requirements/Characteristics MIN On-chip oscillator (X1/X2 pins) (Crystal/Resonator) tc(OSC), Cycle time External oscillator/clock source (XCLKIN pin) — PLL Enabled tc(CI), Cycle time (C8) External oscillator/clock source (XCLKIN pin) — PLL Disabled tc(CI), Cycle time (C8) Limp mode SYSCLKOUT (with /2 enabled) Frequency Frequency Frequency PLL lock time (1) tp MAX UNIT 200 ns 5 20 MHz 33.3 200 ns MHz 5 30 33.33 250 ns 4 30 MHz Frequency range tc(XCO), Cycle time (C1) XCLKOUT (1) Frequency NOM 50 1 to 5 MHz 66.67 2000 0.5 15 MHz ns 1 ms The PLLLOCKPRD register must be updated based on the number of OSCCLK cycles. If the zero-pin internal oscillators (10 MHz) are used as the clock source, then the PLLLOCKPRD register must be written with a value of 10,000 (minimum). Power, Reset, Clocking, and Interrupts Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 49 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 5-6. Internal Zero-Pin Oscillator (INTOSC1/INTOSC2) Characteristics PARAMETER MIN TYP MAX UNIT Internal zero-pin oscillator 1 (INTOSC1) (1) (2) Frequency 10 MHz Internal zero-pin oscillator 2 (INTOSC2) (1) (2) Frequency 10 MHz 55 kHz Step size (coarse trim) Step size (fine trim) 14 Temperature drift (3) 3.03 4.85 kHz/°C Voltage (VDD) drift (3) 175 Hz/mV (1) (2) (3) kHz In order to achieve better oscillator accuracy (10 MHz ± 1% or better) than shown, refer to the oscillator calibration example in 2802x C/C++ Header Files and Peripheral Examples (literature number SPRC832), and the Oscillator Compensation Guide Application Report (literature number SPRAB84). Refer to Figure 5-4 for TYP/MAX values. Frequency range ensured only when VREG is enabled, VREGENZ = VSS. Output frequency of the internal oscillators follows the direction of both the temperature gradient and voltage (VDD) gradient. For example: • Increase in temperature will cause the output frequency to increase per the temperature coefficient. • Decrease in voltage (VDD) will cause the output frequency to decrease per the voltage coefficient. Zero-Pin Oscillator Frequency Movement With Temperature 10.6 10.5 Output Frequency (MHz) 10.4 10.3 10.2 10.1 10 9.9 9.8 9.7 9.6 –40 –30 –20 –10 0 Typical 10 20 30 40 50 60 70 80 90 100 110 120 Temperature (°C) Max Figure 5-4. Zero-Pin Oscillator Frequency Movement With Temperature 50 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 5.2.2 SPRS810 – APRIL 2012 Clock Requirements and Characteristics Table 5-7. XCLKIN Timing Requirements - PLL Enabled NO. MIN MAX UNIT C9 tf(CI) Fall time, XCLKIN 6 ns C10 tr(CI) Rise time, XCLKIN 6 ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % MIN MAX Table 5-8. XCLKIN Timing Requirements - PLL Disabled NO. C9 tf(CI) Fall time, XCLKIN C10 tr(CI) Rise time, XCLKIN Up to 20 MHz 6 20 MHz to 30 MHz 2 Up to 20 MHz 6 20 MHz to 30 MHz 2 UNIT ns ns C11 tw(CIL) Pulse duration, XCLKIN low as a percentage of tc(OSCCLK) 45 55 % C12 tw(CIH) Pulse duration, XCLKIN high as a percentage of tc(OSCCLK) 45 55 % The possible configuration modes are shown in Table 2-16. Table 5-9. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled) (1) (2) over recommended operating conditions (unless otherwise noted) NO. (1) (2) PARAMETER MIN TYP MAX UNIT C3 tf(XCO) Fall time, XCLKOUT 11 ns C4 tr(XCO) Rise time, XCLKOUT 11 ns C5 tw(XCOL) Pulse duration, XCLKOUT low H–2 H+2 ns C6 tw(XCOH) Pulse duration, XCLKOUT high H–2 H+2 ns A load of 40 pF is assumed for these parameters. H = 0.5tc(XCO) C10 C9 C8 XCLKIN(A) C1 C6 C3 C4 C5 XCLKOUT(B) A. B. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown is intended to illustrate the timing parameters only and may differ based on actual configuration. XCLKOUT configured to reflect SYSCLKOUT. Figure 5-5. Clock Timing Power, Reset, Clocking, and Interrupts Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 51 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 5.3 www.ti.com Interrupts Figure 5-6 shows how the various interrupt sources are multiplexed. Peripherals (SPI, SCI, ePWM, I2C, eCAP, ADC) WDINT WAKEINT LPMINT Watchdog Low-Power Modes SYSCLKOUT XINT1 Interrupt Control MUX XINT1 Sync C28 Core GPIOXINT1SEL(4:0) ADC XINT2 XINT2SOC XINT2 Interrupt Control MUX PIE INT1 to INT12 Up to 96 Interrupts XINT1CR(15:0) XINT2CTR(15:0) XINT2CR(15:0) XINT3CTR(15:0) GPIOXINT2SEL(4:0) XINT3 Interrupt Control MUX GPIO0.int XINT3 XINT3CR(15:0) GPIO MUX GPIO31.int XINT3CTR(15:0) GPIOXINT3SEL(4:0) TINT0 INT13 TINT1 INT14 TINT2 NMI CPU TIMER 0 CPU TIMER 1 CPU TIMER 2 NMI interrupt with watchdog function (See the NMI Watchdog section.) CPUTMR2CLK CLOCKFAIL NMIRS System Control (See the System Control section.) Figure 5-6. External and PIE Interrupt Sources 52 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Eight PIE block interrupts are grouped into one CPU interrupt. In total, 12 CPU interrupt groups, with 8 interrupts per group equals 96 possible interrupts. Table 5-10 shows the interrupts used by 2802x0 devices. The TRAP #VectorNumber instruction transfers program control to the interrupt service routine corresponding to the vector specified. TRAP #0 attempts to transfer program control to the address pointed to by the reset vector. The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. When the PIE is enabled, TRAP #1 through TRAP #12 will transfer program control to the interrupt service routine corresponding to the first vector within the PIE group. For example: TRAP #1 fetches the vector from INT1.1, TRAP #2 fetches the vector from INT2.1, and so forth. IFR[12:1] IER[12:1] INTM INT1 INT2 1 CPU MUX 0 INT11 INT12 (Flag) INTx INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 MUX PIEACKx (Enable/Flag) Global Enable (Enable) (Enable) (Flag) PIEIERx[8:1] PIEIFRx[8:1] From Peripherals or External Interrupts Figure 5-7. Multiplexing of Interrupts Using the PIE Block Power, Reset, Clocking, and Interrupts Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 53 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 5-10. PIE MUXed Peripheral Interrupt Vector Table (1) INT1.y INT2.y INT3.y INT4.y INT5.y INT6.y INT7.y INT8.y INT9.y INT10.y INT11.y INT12.y (1) 54 INTx.8 INTx.7 INTx.6 INTx.5 INTx.4 INTx.3 INTx.2 INTx.1 WAKEINT TINT0 ADCINT9 XINT2 XINT1 Reserved ADCINT2 ADCINT1 (LPM/WD) (TIMER 0) (ADC) Ext. int. 2 Ext. int. 1 – (ADC) (ADC) 0xD4E 0xD4C 0xD4A 0xD48 0xD46 0xD44 0xD42 0xD40 Reserved Reserved Reserved Reserved Reserved EPWM3_TZINT EPWM2_TZINT EPWM1_TZINT – – – – – (ePWM3) (ePWM2) (ePWM1) 0xD5E 0xD5C 0xD5A 0xD58 0xD56 0xD54 0xD52 0xD50 Reserved Reserved Reserved Reserved Reserved EPWM3_INT EPWM2_INT EPWM1_INT (ePWM1) – – – – – (ePWM3) (ePWM2) 0xD6E 0xD6C 0xD6A 0xD68 0xD66 0xD64 0xD62 0xD60 Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECAP1_INT (eCAP1) – – – – – – – 0xD7E 0xD7C 0xD7A 0xD78 0xD76 0xD74 0xD72 0xD70 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved – – – – – – – – 0xD8E 0xD8C 0xD8A 0xD88 0xD86 0xD84 0xD82 0xD80 Reserved Reserved Reserved Reserved Reserved Reserved SPITXINTA SPIRXINTA – – – – – – (SPI-A) (SPI-A) 0xD9E 0xD9C 0xD9A 0xD98 0xD96 0xD94 0xD92 0xD90 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved – – – – – – – – 0xDAE 0xDAC 0xDAA 0xDA8 0xDA6 0xDA4 0xDA2 0xDA0 Reserved Reserved Reserved Reserved Reserved Reserved I2CINT2A I2CINT1A – – – – – – (I2C-A) (I2C-A) 0xDBE 0xDBC 0xDBA 0xDB8 0xDB6 0xDB4 0xDB2 0xDB0 Reserved Reserved Reserved Reserved Reserved Reserved SCITXINTA SCIRXINTA (SCI-A) – – – – – – (SCI-A) 0xDCE 0xDCC 0xDCA 0xDC8 0xDC6 0xDC4 0xDC2 0xDC0 ADCINT8 ADCINT7 ADCINT6 ADCINT5 ADCINT4 ADCINT3 ADCINT2 ADCINT1 (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) (ADC) 0xDDE 0xDDC 0xDDA 0xDD8 0xDD6 0xDD4 0xDD2 0xDD0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved – – – – – – – – 0xDEE 0xDEC 0xDEA 0xDE8 0xDE6 0xDE4 0xDE2 0xDE0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved XINT3 – – – – – – – Ext. Int. 3 0xDFE 0xDFC 0xDFA 0xDF8 0xDF6 0xDF4 0xDF2 0xDF0 Out of 96 possible interrupts, some interrupts are not used. These interrupts are reserved for future devices. These interrupts can be used as software interrupts if they are enabled at the PIEIFRx level, provided none of the interrupts within the group is being used by a peripheral. Otherwise, interrupts coming in from peripherals may be lost by accidentally clearing their flag while modifying the PIEIFR. To summarize, there are two safe cases when the reserved interrupts could be used as software interrupts: • No peripheral within the group is asserting interrupts. • No peripheral interrupts are assigned to the group (e.g., PIE groups 5, 7, or 11). Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 5-11. PIE Configuration and Control Registers NAME DESCRIPTION (1) ADDRESS SIZE (x16) PIECTRL 0x0CE0 1 PIE, Control Register PIEACK 0x0CE1 1 PIE, Acknowledge Register PIEIER1 0x0CE2 1 PIE, INT1 Group Enable Register PIEIFR1 0x0CE3 1 PIE, INT1 Group Flag Register PIEIER2 0x0CE4 1 PIE, INT2 Group Enable Register PIEIFR2 0x0CE5 1 PIE, INT2 Group Flag Register PIEIER3 0x0CE6 1 PIE, INT3 Group Enable Register PIEIFR3 0x0CE7 1 PIE, INT3 Group Flag Register PIEIER4 0x0CE8 1 PIE, INT4 Group Enable Register PIEIFR4 0x0CE9 1 PIE, INT4 Group Flag Register PIEIER5 0x0CEA 1 PIE, INT5 Group Enable Register PIEIFR5 0x0CEB 1 PIE, INT5 Group Flag Register PIEIER6 0x0CEC 1 PIE, INT6 Group Enable Register PIEIFR6 0x0CED 1 PIE, INT6 Group Flag Register PIEIER7 0x0CEE 1 PIE, INT7 Group Enable Register PIEIFR7 0x0CEF 1 PIE, INT7 Group Flag Register PIEIER8 0x0CF0 1 PIE, INT8 Group Enable Register PIEIFR8 0x0CF1 1 PIE, INT8 Group Flag Register PIEIER9 0x0CF2 1 PIE, INT9 Group Enable Register PIEIFR9 0x0CF3 1 PIE, INT9 Group Flag Register PIEIER10 0x0CF4 1 PIE, INT10 Group Enable Register PIEIFR10 0x0CF5 1 PIE, INT10 Group Flag Register PIEIER11 0x0CF6 1 PIE, INT11 Group Enable Register PIEIFR11 0x0CF7 1 PIE, INT11 Group Flag Register PIEIER12 0x0CF8 1 PIE, INT12 Group Enable Register PIEIFR12 0x0CF9 1 PIE, INT12 Group Flag Register Reserved 0x0CFA – 0x0CFF 6 Reserved (1) The PIE configuration and control registers are not protected by EALLOW mode. The PIE vector table is protected. Power, Reset, Clocking, and Interrupts Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 55 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 5.3.1 www.ti.com External Interrupts Table 5-12. External Interrupt Registers ADDRESS SIZE (x16) XINT1CR NAME 0x00 7070 1 XINT1 configuration register DESCRIPTION XINT2CR 0x00 7071 1 XINT2 configuration register XINT3CR 0x00 7072 1 XINT3 configuration register XINT1CTR 0x00 7078 1 XINT1 counter register XINT2CTR 0x00 7079 1 XINT2 counter register XINT3CTR 0x00 707A 1 XINT3 counter register Each external interrupt can be enabled/disabled or qualified using positive, negative, or both positive and negative edge. For more information, see the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3). 5.3.1.1 External Interrupt Electrical Data/Timing Table 5-13. External Interrupt Timing Requirements (1) TEST CONDITIONS tw(INT) (1) (2) (2) Pulse duration, INT input low/high MIN MAX UNIT Synchronous 1tc(SCO) cycles With qualifier 1tc(SCO) + tw(IQSW) cycles For an explanation of the input qualifier parameters, see Table 6-30. This timing is applicable to any GPIO pin configured for ADCSOC functionality. Table 5-14. External Interrupt Switching Characteristics (1) over recommended operating conditions (unless otherwise noted) PARAMETER td(INT) (1) Delay time, INT low/high to interrupt-vector fetch MIN MAX UNIT tw(IQSW) + 12tc(SCO) cycles For an explanation of the input qualifier parameters, see Table 6-30. tw(INT) XINT1, XINT2, XINT3 td(INT) Address bus (internal) Interrupt Vector Figure 5-8. External Interrupt Timing 56 Power, Reset, Clocking, and Interrupts Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 6 Peripheral Information and Timings 6.1 Parameter Information 6.1.1 Timing Parameter Symbology Timing parameter symbols used are created in accordance with JEDEC Standard 100. To shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows: 6.1.1.1 Lowercase subscripts and their meanings: Letters and symbols and their meanings: a access time H High c cycle time (period) L Low d delay time V Valid f fall time X Unknown, changing, or don't care level h hold time Z High impedance r rise time su setup time t transition time v valid time w pulse duration (width) General Notes on Timing Parameters All output signals from the 28x devices (including XCLKOUT) are derived from an internal clock such that all output transitions for a given half-cycle occur with a minimum of skewing relative to each other. The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles. For actual cycle examples, see the appropriate cycle description section of this document. 6.1.2 Test Load Circuit This test load circuit is used to measure all switching characteristics provided in this document. Tester Pin Electronics 42 W Data Sheet Timing Reference Point 3.5 nH Transmission Line (A) Output Under Test Z0 = 50 W 4.0 pF A. B. Device Pin 1.85 pF (B) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns or longer) from the data sheet timing. Figure 6-1. 3.3-V Test Load Circuit Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 57 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.2 www.ti.com Analog-to-Digital Converter (ADC) A 12-bit ADC core is implemented that has different timings than the 12-bit ADC used on F280x/F2833x. The ADC wrapper is modified to incorporate the new timings and also other enhancements to improve the timing control of start of conversions. Figure 6-2 shows the interaction of the analog module with the rest of the F2802x0 system. 38-Pin 48-Pin VDDA VDDA (3.3 V) VDDA (Agnd) VSSA VREFLO Interface Reference VREFLO VREFLO Tied To Tied To VSSA VSSA Diff VREFHI VREFHI VREFHI A1 B1 A1 A2 A4 A4 A6 A6 B1 B2 B2 B4 B4 B6 B6 A2 Simultaneous Sampling Channels A2 B2 10-Bit DAC Comp1 ADC A4 B4 COMP2OUT AIO4 AIO12 10-Bit DAC Comp2 (See Note A) Temperature Sensor A6 Signal Pinout B6 A. COMP1OUT AIO2 AIO10 AIO6 AIO14 Comparator 2 is only available on the 48-pin PT package. Figure 6-2. Analog Pin Configurations 58 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.2.1 SPRS810 – APRIL 2012 Analog-to-Digital Converter Device-Specific Information The core of the ADC contains a single 12-bit converter fed by two sample-and-hold circuits. The sampleand-hold circuits can be sampled simultaneously or sequentially. These, in turn, are fed by a total of up to 8 analog input channels. The converter can be configured to run with an internal bandgap reference to create true-voltage based conversions or with a pair of external voltage references (VREFHI/VREFLO) to create ratiometric-based conversions. Contrary to previous ADC types, this ADC is not sequencer-based. It is easy for the user to create a series of conversions from a single trigger. However, the basic principle of operation is centered around the configurations of individual conversions, called SOCs, or Start-Of-Conversions. Functions of the ADC module include: • 12-bit ADC core with built-in dual sample-and-hold (S/H) • Simultaneous sampling or sequential sampling modes • Full range analog input: 0 V to 3.3 V fixed, or VREFHI/VREFLO ratiometric. The digital value of the input analog voltage is derived by: – Internal Reference (VREFLO = VSSA. VREFHI must not exceed VDDA when using either internal or external reference modes.) Digital Value = 0, when input £ 0 V Digital Value = 4096 ´ Input Analog Voltage - VREFLO 3.3 Digital Value = 4095, when 0 V < input < 3.3 V when input ³ 3.3 V – External Reference (VREFHI/VREFLO connected to external references. VREFHI must not exceed VDDA when using either internal or external reference modes.) when input £ 0 V Digital Value = 0, Digital Value = 4096 ´ Digital Value = 4095, • • • • • • Input Analog Voltage - VREFLO VREFHI - VREFLO when 0 V < input < VREFHI when input ³ VREFHI Runs at full system clock, no prescaling required Up to 16-channel, multiplexed inputs 16 SOCs, configurable for trigger, sample window, and channel 16 result registers (individually addressable) to store conversion values Multiple trigger sources – S/W – software immediate start – ePWM 1–3 – GPIO XINT2 – CPU Timers 0/1/2 – ADCINT1/2 9 flexible PIE interrupts, can configure interrupt request after any conversion Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 59 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 0-Wait Result Registers PF0 (CPU) PF2 (CPU) SYSCLKOUT ADCENCLK ADCINT 1 PIE ADCINT 9 AIO MUX ADC Channels ADC Core 12-Bit ADCTRIG 1 ADCTRIG 2 ADCTRIG 3 ADCTRIG 4 ADCTRIG 5 ADCTRIG 6 ADCTRIG 7 ADCTRIG 8 ADCTRIG 9 ADCTRIG 10 TINT 0 TINT 1 TINT 2 XINT 2SOC CPUTIMER 0 CPUTIMER 1 CPUTIMER 2 XINT 2 SOCA 1 SOCB 1 ePWM 1 SOCA 2 SOCB 2 ePWM 2 SOCA 3 SOCB 3 ePWM 3 Figure 6-3. ADC Connections ADC Connections if the ADC is Not Used It is recommended that the connections for the analog power pins be kept, even if the ADC is not used. Following is a summary of how the ADC pins should be connected, if the ADC is not used in an application: • VDDA – Connect to VDDIO • VSSA – Connect to VSS • VREFLO – Connect to VSS • ADCINAn, ADCINBn, VREFHI – Connect to VSSA When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (VSSA). NOTE: Unused ADCIN pins that are multiplexed with AIO function should not be directly connected to analog ground. They should be grounded through a 1-kΩ resistor. This is to prevent an errant code from configuring these pins as AIO outputs and driving grounded pins to a logic-high state. When the ADC is not used, be sure that the clock to the ADC module is not turned on to realize power savings. 60 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.2.2 SPRS810 – APRIL 2012 Analog-to-Digital Converter Register Descriptions Table 6-1. ADC Configuration and Control Registers ADDRESS SIZE (x16) EALLOW PROTECTED ADCCTL1 0x7100 1 Yes Control 1 Register ADCCTL2 0x7101 1 Yes Control 2 Register ADCINTFLG 0x7104 1 No Interrupt Flag Register ADCINTFLGCLR 0x7105 1 No Interrupt Flag Clear Register ADCINTOVF 0x7106 1 No Interrupt Overflow Register ADCINTOVFCLR 0x7107 1 No Interrupt Overflow Clear Register INTSEL1N2 0x7108 1 Yes Interrupt 1 and 2 Selection Register INTSEL3N4 0x7109 1 Yes Interrupt 3 and 4 Selection Register INTSEL5N6 0x710A 1 Yes Interrupt 5 and 6 Selection Register INTSEL7N8 0x710B 1 Yes Interrupt 7 and 8 Selection Register INTSEL9N10 0x710C 1 Yes Interrupt 9 Selection Register (reserved Interrupt 10 Selection) SOCPRICTL 0x7110 1 Yes SOC Priority Control Register ADCSAMPLEMODE 0x7112 1 Yes Sampling Mode Register ADCINTSOCSEL1 0x7114 1 Yes Interrupt SOC Selection 1 Register (for 8 channels) ADCINTSOCSEL2 0x7115 1 Yes Interrupt SOC Selection 2 Register (for 8 channels) ADCSOCFLG1 0x7118 1 No SOC Flag 1 Register (for 16 channels) ADCSOCFRC1 0x711A 1 No SOC Force 1 Register (for 16 channels) ADCSOCOVF1 0x711C 1 No SOC Overflow 1 Register (for 16 channels) REGISTER NAME ADCSOCOVFCLR1 DESCRIPTION 0x711E 1 No SOC Overflow Clear 1 Register (for 16 channels) 0x7120 – 0x712F 1 Yes SOC0 Control Register to SOC15 Control Register ADCREFTRIM 0x7140 1 Yes Reference Trim Register ADCOFFTRIM 0x7141 1 Yes Offset Trim Register COMPHYSTCTL 0x714C 1 Yes Comparator Hysteresis Control Register ADCREV 0x714F 1 No Revision Register ADCSOC0CTL to ADCSOC15CTL Table 6-2. ADC Result Registers (Mapped to PF0) REGISTER NAME ADCRESULT0 to ADCRESULT15 ADDRESS 0xB00 – 0xB0F SIZE (x16) EALLOW PROTECTED 1 No DESCRIPTION ADC Result 0 Register to ADC Result 15 Register Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 61 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.2.3 www.ti.com Analog-to-Digital Converter Electrical Data/Timing Table 6-3. ADC Electrical Characteristics PARAMETER MIN TYP MAX UNIT DC SPECIFICATIONS Resolution 12 ADC clock Bits 0.001 SYSCLKOUT/2 280270/280260 7 64 280230/280220 14 64 INL (Integral nonlinearity) (2) –4 4 LSB DNL (Differential nonlinearity), no missing codes –1 1 LSB LSB Sample Window (1) MHz ADC Clocks ACCURACY Offset error (3) Executing Device_Cal function –20 0 20 Executing periodic selfrecalibration (4) –4 0 4 Overall gain error with internal reference –60 60 LSB Overall gain error with external reference –40 40 LSB Channel-to-channel offset variation –4 4 LSB Channel-to-channel gain variation –4 4 LSB ADC temperature coefficient with internal reference –50 ppm/°C ADC temperature coefficient with external reference –20 ppm/°C VREFLO –100 µA VREFHI 100 µA ANALOG INPUT Analog input voltage with internal reference 0 3.3 V Analog input voltage with external reference VREFLO VREFHI V VSSA VSSA V 1.98 VDDA VREFLO input voltage (5) VREFHI input voltage (6) Input capacitance Input leakage current (1) (2) (3) (4) (5) (6) 62 with VREFLO = VSSA V 5 pF ±5 μA Only NONOVERLAP mode is supported (ADCNONOVERLAP = 1). For more information, see the "ADC Control Register 2 (ADCCTL2)" section of the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (literature number SPRUGE5). INL will degrade when the ADC input voltage goes above VDDA. 1 LSB has the weighted value of full-scale range (FSR)/4096. FSR is 3.3 V with internal reference and VREFHI - VREFLO for external reference. Periodic self-recalibration will remove system-level and temperature dependencies on the ADC zero offset error. This can be performed as needed in the application without sacrificing an ADC channel by using the procedure listed in the "ADC Zero Offset Calibration" section of the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (literature number SPRUGE5). VREFLO is always connected to VSSA. VREFHI must not exceed VDDA when using either internal or external reference modes. Since VREFHI is tied to ADCINA0, the input signal on ADCINA0 must not exceed VDDA. Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 6-4. ADC Power Modes IDDA UNITS Mode A – Operating Mode ADC OPERATING MODE ADC Clock Enabled Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWDN = 1) 13 mA Mode B – Quick Wake Mode ADC Clock Enabled Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 1) ADC Powered Up (ADCPWDN = 0) 4 mA Mode C – Comparator-Only Mode ADC Clock Enabled Bandgap On (ADCBGPWD = 1) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWDN = 0) 1.5 mA Mode D – Off Mode ADC Clock Enabled Bandgap On (ADCBGPWD = 0) Reference On (ADCREFPWD = 0) ADC Powered Up (ADCPWDN = 0) 0.075 mA 6.2.3.1 CONDITIONS ADC Start-of-Conversion Electrical Data/Timing Table 6-5. External ADC Start-of-Conversion Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tw(ADCSOCL) MIN Pulse duration, ADCSOCxO low MAX 32tc(HCO ) UNIT cycles tw(ADCSOCL) ADCSOCAO or ADCSOCBO Figure 6-4. ADCSOCAO or ADCSOCBO Timing 6.2.3.2 Internal Temperature Sensor Table 6-6. Temperature Sensor Coefficient PARAMETER (1) TSLOPE Degrees C of temperature movement per measured ADC LSB change of the temperature sensor TOFFSET ADC output at 0°C of the temperature sensor (1) (2) (3) MIN TYP 0.18 (2) (3) 1750 MAX UNIT °C/LSB LSB The temperature sensor slope and offset are given in terms of ADC LSBs using the internal reference of the ADC. Values must be adjusted accordingly in external reference mode to the external reference voltage. ADC temperature coeffieicient is accounted for in this specification Output of the temperature sensor (in terms of LSBs) is sign-consistent with the direction of the temperature movement. Increasing temperatures will give increasing ADC values relative to an initial value; decreasing temperatures will give decreasing ADC values relative to an initial value. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 63 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.2.3.3 www.ti.com ADC Power-Up Control Bit Timing Table 6-7. ADC Power-Up Delays PARAMETER (1) td(PWD) (1) MIN TYP Delay time for the ADC to be stable after power up MAX 1 UNIT ms Timings maintain compatibility to the ADC module. The 2802x0 ADC supports driving all 3 bits at the same time td(PWD) ms before first conversion. ADCPWDN/ ADCBGPWD/ ADCREFPWD/ ADCENABLE td(PWD) Request for ADC Conversion Figure 6-5. ADC Conversion Timing Rs Source Signal ADCIN Ron 3.4 kW Switch Cp 5 pF ac Ch 1.6 pF 28x DSP Typical Values of the Input Circuit Components: Switch Resistance (Ron): 3.4 k W Sampling Capacitor (Ch): 1.6 pF Parasitic Capacitance (Cp): 5 pF Source Resistance (Rs): 50 W Figure 6-6. ADC Input Impedance Model 64 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.2.3.4 SPRS810 – APRIL 2012 ADC Sequential and Simultaneous Timings Analog Input SOC0 Sample Window 0 2 SOC1 Sample Window 22 24 9 SOC2 Sample Window 42 44 29 49 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 S/H Window Pulse to Core SOC0 ADCRESULT 0 SOC1 2 ADCCLKs SOC2 Result 0 Latched ADCRESULT 1 EOC0 Pulse EOC1 Pulse ADCINTFLG.ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 1 ADCCLKs Minimum 7 ADCCLKs Conversion 1 13 ADC Clocks Figure 6-7. Timing Example for Sequential Mode / Late Interrupt Pulse Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 65 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Analog Input SOC0 Sample Window 0 9 2 SOC2 Sample Window SOC1 Sample Window 29 22 24 42 44 49 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 S/H Window Pulse to Core SOC0 SOC1 ADCRESULT 0 SOC2 Result 0 Latched ADCRESULT 1 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG.ADCINTx Minimum 7 ADCCLKs Conversion 0 13 ADC Clocks 2 ADCCLKs Minimum 7 ADCCLKs Conversion 1 13 ADC Clocks Figure 6-8. Timing Example for Sequential Mode / Early Interrupt Pulse 66 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window 35 37 42 Analog Input B 0 9 2 22 24 55 57 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 S/H Window Pulse to Core SOC0 (A/B) ADCRESULT 0 SOC2 (A/B) 2 ADCCLKs Result 0 (A) Latched Result 0 (B) Latched ADCRESULT 1 ADCRESULT 2 EOC0 Pulse 1 ADCCLK EOC1 Pulse EOC2 Pulse ADCINTFLG.ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks Conversion 0 (B) 13 ADC Clocks 2 ADCCLKs Minimum 7 ADCCLKs Conversion 1 (A) 13 ADC Clocks Figure 6-9. Timing Example for Simultaneous Mode / Late Interrupt Pulse Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 67 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Analog Input A SOC0 Sample A Window SOC2 Sample A Window SOC0 Sample B Window SOC2 Sample B Window 35 37 42 Analog Input B 0 9 2 22 24 55 57 ADCCLK ADCCTL1.INTPULSEPOS ADCSOCFLG1.SOC0 ADCSOCFLG1.SOC1 ADCSOCFLG1.SOC2 S/H Window Pulse to Core SOC0 (A/B) SOC2 (A/B) 2 ADCCLKs ADCRESULT 0 Result 0 (A) Latched Result 0 (B) Latched ADCRESULT 1 ADCRESULT 2 EOC0 Pulse EOC1 Pulse EOC2 Pulse ADCINTFLG.ADCINTx Minimum 7 ADCCLKs Conversion 0 (A) 13 ADC Clocks Conversion 0 (B) 13 ADC Clocks 2 ADCCLKs Minimum 7 ADCCLKs Conversion 1 (A) 13 ADC Clocks Figure 6-10. Timing Example for Simultaneous Mode / Early Interrupt Pulse 68 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.2.3.5 SPRS810 – APRIL 2012 Detailed Descriptions Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs one-half LSB before the first code transition. The full-scale point is defined as level one-half LSB beyond the last code transition. The deviation is measured from the center of each particular code to the true straight line between these two points. Differential Nonlinearity An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. A differential nonlinearity error of less than ±1 LSB ensures no missing codes. Zero Offset The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the deviation of the actual transition from that point. Gain Error The first code transition should occur at an analog value one-half LSB above negative full scale. The last transition should occur at an analog value one and one-half LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Signal-to-Noise Ratio + Distortion (SINAD) SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in decibels. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, (SINAD - 1.76) N= 6.02 it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first nine harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 69 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.2.4 www.ti.com ADC MUX To COMPy A or B input To ADC Channel X Logic implemented in GPIO MUX block AIOx Pin SYSCLK AIOxIN 1 AIOxINE AIODAT Reg (Read) SYNC 0 AIODAT Reg (Latch) AIOxDIR (1 = Input, 0 = Output) AIOMUX 1 Reg AIOSET, AIOCLEAR, AIOTOGGLE Regs AIODIR Reg (Latch) 1 (0 = Input, 1 = Output) 0 0 Figure 6-11. AIOx Pin Multiplexing The ADC channel and Comparator functions are always available. The digital I/O function is available only when the respective bit in the AIOMUX1 register is 0. In this mode, reading the AIODAT register reflects the actual pin state. The digital I/O function is disabled when the respective bit in the AIOMUX1 register is 1. In this mode, reading the AIODAT register reflects the output latch of the AIODAT register and the input digital I/O buffer is disabled to prevent analog signals from generating noise. On reset, the digital function is disabled. If the pin is used as an analog input, users should keep the AIO function disabled for that pin. 70 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.3 SPRS810 – APRIL 2012 Comparator Block 6.3.1 Comparator Block Device-Specific Information Figure 6-12 shows the interaction of the Comparator modules with the rest of the system. COMP x A COMP x B + COMP - GPIO MUX TZ1/2/3 COMP x + DAC x Wrapper AIO MUX ePWM COMPxOUT DAC Core 10-Bit Figure 6-12. Comparator Block Diagram 6.3.2 Comparator Block Register Descriptions Table 6-8 lists the Comparator Control Registers. Table 6-8. Comparator Control Registers COMP1 ADDRESS COMP2 ADDRESS (1) SIZE (x16) EALLOW PROTECTED COMPCTL 0x6400 0x6420 1 Yes Comparator Control Register COMPSTS 0x6402 0x6422 1 No Comparator Status Register DACCTL 0x6404 0x6424 1 Yes DAC Control Register DACVAL 0x6406 0x6426 1 No DAC Value Register RAMPMAXREF_ACTIVE 0x6408 0x6428 1 No Ramp Generator Maximum Reference (Active) Register RAMPMAXREF_SHDW 0x640A 0x642A 1 No Ramp Generator Maximum Reference (Shadow) Register RAMPDECVAL_ACTIVE 0x640C 0x642C 1 No Ramp Generator Decrement Value (Active) Register RAMPDECVAL_SHDW 0x640E 0x642E 1 No Ramp Generator Decrement Value (Shadow) Register RAMPSTS 0x6410 0x6430 1 No Ramp Generator Status Register REGISTER NAME (1) DESCRIPTION Comparator 2 is only available on the 48-pin PT package. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 71 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.3.3 www.ti.com On-Chip Comparator/DAC Electrical Data/Timing Table 6-9. Electrical Characteristics of the Comparator/DAC CHARACTERISTIC MIN TYP MAX UNITS Comparator Comparator Input Range VSSA – VDDA V Comparator response time to PWM Trip Zone (Async) 30 ns Input Offset ±5 mV 35 mV Input Hysteresis (1) DAC DAC Output Range VSSA – VDDA DAC resolution DAC settling time bits See Figure 613 DAC Gain DAC Offset Monotonic –1.5 % 10 mV Yes INL (1) V 10 ±3 LSB Hysteresis on the comparator inputs is achieved with a Schmidt trigger configuration. This results in an effective 100-kΩ feedback resistance between the output of the comparator and the non-inverting input of the comparator. There is an option to disable the hysteresis and, with it, the feedback resistance; see the TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide (literature number SPRUGE5) for more information on this option if needed in your system. 1100 1000 900 800 Settling Time (ns) 700 600 500 400 300 200 100 0 0 50 100 150 200 250 300 350 400 450 500 DAC Step Size (Codes) DAC Accuracy 15 Codes 7 Codes 3 Codes 1 Code Figure 6-13. DAC Settling Time 72 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.4 SPRS810 – APRIL 2012 Serial Peripheral Interface (SPI) 6.4.1 Serial Peripheral Interface Device-Specific Information The device includes the four-pin serial peripheral interface (SPI) module. One SPI module (SPI-A) is available. The SPI is a high-speed, synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmable bittransfer rate. Normally, the SPI is used for communications between the MCU and external peripherals or another processor. Typical applications include external I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice communications are supported by the master/slave operation of the SPI. The SPI module features include: • Four external pins: – SPISOMI: SPI slave-output/master-input pin – SPISIMO: SPI slave-input/master-output pin – SPISTE: SPI slave transmit-enable pin – SPICLK: SPI serial-clock pin NOTE: All four pins can be used as GPIO if the SPI module is not used. • Two operational modes: master and slave Baud rate: 125 different programmable rates. • • • • • Baud rate = LSPCLK (SPIBRR + 1) when SPIBRR = 3 to 127 Baud rate = LSPCLK 4 when SPIBRR = 0, 1, 2 Data word length: one to sixteen data bits Four clocking schemes (controlled by clock polarity and clock phase bits) include: – Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. – Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal. – Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. Simultaneous receive and transmit operation (transmit function can be disabled in software) Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms. Nine SPI module control registers: Located in control register frame beginning at address 7040h. NOTE All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 4-level transmit/receive FIFO • Delayed transmit control • Bi-directional 3 wire SPI mode support Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 73 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Figure 6-14 is a block diagram of the SPI in slave mode. SPIFFENA SPIFFTX.14 Receiver Overrun Flag RX FIFO Registers SPISTS.7 Overrun INT ENA SPICTL.4 SPIRXBUF RX FIFO _0 RX FIFO _1 ----- SPIINT RX FIFO Interrupt RX FIFO _3 RX Interrupt Logic 16 SPIRXBUF Buffer Register SPIFFOVF FLAG SPIFFRX.15 To CPU TX FIFO Registers SPITXBUF TX FIFO _3 SPITX 16 16 TX Interrupt Logic TX FIFO Interrupt ----TX FIFO _1 TX FIFO _0 SPI INT ENA SPI INT FLAG SPITXBUF Buffer Register SPISTS.6 SPICTL.0 TRIWIRE SPIPRI.0 16 M M SPIDAT Data Register TW S S SPIDAT.15 - 0 SW1 SPISIMO M TW M TW S S SPISOMI SW2 Talk SPICTL.1 SPISTE State Control Master/Slave SPICCR.3 - 0 SPI Char 3 2 M SPI Bit Rate SW3 S SPIBRR.6 - 0 LSPCLK 6 A. SPICTL.2 S 0 1 5 4 3 2 1 0 Clock Polarity Clock Phase SPICCR.6 SPICTL.3 SPICLK M SPISTE is driven low by the master for a slave device. Figure 6-14. SPI Module Block Diagram (Slave Mode) 74 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.4.2 SPRS810 – APRIL 2012 Serial Peripheral Interface Register Descriptions The SPI port operation is configured and controlled by the registers listed in Table 6-10. Table 6-10. SPI-A Registers (1) DESCRIPTION (1) NAME ADDRESS SIZE (x16) EALLOW PROTECTED SPICCR 0x7040 1 No SPI-A Configuration Control Register SPICTL 0x7041 1 No SPI-A Operation Control Register SPISTS 0x7042 1 No SPI-A Status Register SPIBRR 0x7044 1 No SPI-A Baud Rate Register SPIRXEMU 0x7046 1 No SPI-A Receive Emulation Buffer Register SPIRXBUF 0x7047 1 No SPI-A Serial Input Buffer Register SPITXBUF 0x7048 1 No SPI-A Serial Output Buffer Register SPIDAT 0x7049 1 No SPI-A Serial Data Register SPIFFTX 0x704A 1 No SPI-A FIFO Transmit Register SPIFFRX 0x704B 1 No SPI-A FIFO Receive Register SPIFFCT 0x704C 1 No SPI-A FIFO Control Register SPIPRI 0x704F 1 No SPI-A Priority Control Register Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. 6.4.3 Serial Peripheral Interface Master Mode Electrical Data/Timing Table 6-11 lists the master mode timing (clock phase = 0) and Table 6-12 lists the timing (clock phase = 1). Figure 6-15 and Figure 6-16 show the timing waveforms. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 75 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 6-11. SPI Master Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. MIN UNIT MAX tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc(LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) td(SPCH-SIMO)M Delay time, SPICLK high to SPISIMO valid (clock polarity = 0) 10 10 td(SPCL-SIMO)M Delay time, SPICLK low to SPISIMO valid (clock polarity = 1) 10 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M + 0.5tc(LCO) – 10 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 0) 26 26 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 1) 26 26 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 0.5tc(LCO) – 10 5 8 9 76 MIN 2 4 (5) MAX 1 3 (1) (2) (3) (4) SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1) tc(LCO) = LSPCLK cycle time Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 4 5 SPISIMO Master Out Data Is Valid 8 9 SPISOMI Master In Data Must Be Valid (A) SPISTE A. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-15. SPI Master Mode External Timing (Clock Phase = 0) Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 77 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 6-12. SPI Master Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) (5) SPI WHEN (SPIBRR + 1) IS EVEN OR SPIBRR = 0 OR 2 NO. MIN tc(SPC)M Cycle time, SPICLK 4tc(LCO) 128tc(LCO) 5tc(LCO) 127tc(LCO) ns tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO) ns tw(SPCL))M Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M – 0.5tc (LCO) – 10 0.5tc(SPC)M – 0.5tc(LCO tw(SPCL)M Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tw(SPCH)M Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M 0.5tc(SPC)M + 0.5tc(LCO) – 10 0.5tc(SPC)M + 0.5tc(LCO) tsu(SIMO-SPCH)M Setup time, SPISIMO data valid before SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tsu(SIMO-SPCL)M Setup time, SPISIMO data valid before SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCH-SIMO)M Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCL-SIMO)M Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)M – 10 0.5tc(SPC)M – 10 tsu(SOMI-SPCH)M Setup time, SPISOMI before SPICLK high (clock polarity = 0) 26 26 tsu(SOMI-SPCL)M Setup time, SPISOMI before SPICLK low (clock polarity = 1) 26 26 tv(SPCH-SOMI)M Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 tv(SPCL-SOMI)M Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.25tc(SPC)M – 10 0.5tc(SPC)M – 10 7 10 11 78 UNIT MAX 2 6 (4) (5) MIN 1 3 (1) (2) (3) MAX SPI WHEN (SPIBRR + 1) IS ODD AND SPIBRR > 3 ns ns ns ns ns The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is set. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. tc(LCO) = LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 1 SPICLK (clock polarity = 0) 2 3 SPICLK (clock polarity = 1) 6 7 Master out data Is valid SPISIMO Data Valid 10 11 Master in data must be valid SPISOMI SPISTE(A) B. In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-16. SPI Master Mode External Timing (Clock Phase = 1) Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 79 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.4.4 www.ti.com Serial Peripheral Interface Slave Mode Electrical Data/Timing Table 6-13 lists the slave mode external timing (clock phase = 0) and Table 6-14 (clock phase = 1). Figure 6-17 and Figure 6-18 show the timing waveforms. Table 6-13. SPI Slave Mode External Timing (Clock Phase = 0) (1) (2) (3) (4) (5) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S td(SPCH-SOMI)S Delay time, SPICLK high to SPISOMI valid (clock polarity = 0) 21 td(SPCL-SOMI)S Delay time, SPICLK low to SPISOMI valid (clock polarity = 1) 21 tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 0) 0.75tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 1) 0.75tc(SPC)S tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 0) 26 tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 1) 26 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 14 15 16 19 20 (1) (2) (3) (4) (5) 4tc(LCO) UNIT ns ns ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. tc(LCO) = LSPCLK cycle time The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 15 16 SPISOMI SPISOMI data Is valid 19 20 SPISIMO SPISIMO data must be valid SPISTE(A) C. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) (minimum) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-17. SPI Slave Mode External Timing (Clock Phase = 0) 80 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 6-14. SPI Slave Mode External Timing (Clock Phase = 1) (1) (2) (3) (4) NO. MIN MAX 12 tc(SPC)S Cycle time, SPICLK 13 tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC)S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC) S tw(SPCL)S Pulse duration, SPICLK low (clock polarity = 0) 0.5tc(SPC)S – 10 0.5tc(SPC) S tw(SPCH)S Pulse duration, SPICLK high (clock polarity = 1) 0.5tc(SPC)S – 10 0.5tc(SPC)S tsu(SOMI-SPCH)S Setup time, SPISOMI before SPICLK high (clock polarity = 0) 0.125tc(SPC)S tsu(SOMI-SPCL)S Setup time, SPISOMI before SPICLK low (clock polarity = 1) 0.125tc(SPC)S tv(SPCL-SOMI)S Valid time, SPISOMI data valid after SPICLK low (clock polarity = 1) 0.75tc(SPC)S tv(SPCH-SOMI)S Valid time, SPISOMI data valid after SPICLK high (clock polarity = 0) 0.75tc(SPC) S tsu(SIMO-SPCH)S Setup time, SPISIMO before SPICLK high (clock polarity = 0) 26 tsu(SIMO-SPCL)S Setup time, SPISIMO before SPICLK low (clock polarity = 1) 26 tv(SPCH-SIMO)S Valid time, SPISIMO data valid after SPICLK high (clock polarity = 0) 0.5tc(SPC)S – 10 tv(SPCL-SIMO)S Valid time, SPISIMO data valid after SPICLK low (clock polarity = 1) 0.5tc(SPC)S – 10 14 17 18 21 22 (1) (2) (3) (4) 8tc(LCO) UNIT ns ns ns ns ns ns ns The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared. tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1) Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 15-MHz MAX, master mode receive 10-MHz MAX Slave mode transmit 10-MHz MAX, slave mode receive 10-MHz MAX. The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). 12 SPICLK (clock polarity = 0) 13 14 SPICLK (clock polarity = 1) 17 18 SPISOMI SPISOMI data is valid Data Valid 21 22 SPISIMO SPISIMO data must be valid SPISTE(A) A. In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit. Figure 6-18. SPI Slave Mode External Timing (Clock Phase = 1) Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 81 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.5 www.ti.com Serial Communications Interface (SCI) 6.5.1 Serial Communications Interface Device-Specific Information The devices include one serial communications interface (SCI) module (SCI-A). The SCI module supports digital communications between the CPU and other asynchronous peripherals that use the standard nonreturn-to-zero (NRZ) format. The SCI receiver and transmitter are double-buffered, and each has its own separate enable and interrupt bits. Both can be operated independently or simultaneously in the fullduplex mode. To ensure data integrity, the SCI checks received data for break detection, parity, overrun, and framing errors. The bit rate is programmable to over 65000 different speeds through a 16-bit baudselect register. Features of each SCI module include: • Two external pins: – SCITXD: SCI transmit-output pin – SCIRXD: SCI receive-input pin NOTE: Both pins can be used as GPIO if not used for SCI. – Baud rate programmable to 64K different rates: • • • • • • • • Baud rate = LSPCLK (BRR + 1) * 8 when BRR ¹ 0 Baud rate = LSPCLK 16 when BRR = 0 Data-word format – One start bit – Data-word length programmable from one to eight bits – Optional even/odd/no parity bit – One or two stop bits Four error-detection flags: parity, overrun, framing, and break detection Two wake-up multiprocessor modes: idle-line and address bit Half- or full-duplex operation Double-buffered receive and transmit functions Transmitter and receiver operations can be accomplished through interrupt-driven or polled algorithms with status flags. – Transmitter: TXRDY flag (transmitter-buffer register is ready to receive another character) and TX EMPTY flag (transmitter-shift register is empty) – Receiver: RXRDY flag (receiver-buffer register is ready to receive another character), BRKDT flag (break condition occurred), and RX ERROR flag (monitoring four interrupt conditions) Separate enable bits for transmitter and receiver interrupts (except BRKDT) NRZ (non-return-to-zero) format NOTE All registers in this module are 8-bit registers that are connected to Peripheral Frame 2. When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced features: • Auto baud-detect hardware logic • 4-level transmit/receive FIFO 82 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Figure 6-19 shows the SCI module block diagram. SCICTL1.1 SCITXD Frame Format and Mode Parity Even/Odd Enable TXSHF Register TXENA 8 SCICCR.6 SCICCR.5 TXRDY TXWAKE SCICTL1.3 1 Transmitter-Data Buffer Register 8 TX INT ENA SCICTL2.7 SCICTL2.0 TX FIFO Interrupts TX FIFO _0 TX FIFO _1 TXINT TX Interrupt Logic To CPU ----- TX FIFO _3 WUT SCITXD TX EMPTY SCICTL2.6 SCI TX Interrupt select logic SCITXBUF.7-0 TX FIFO registers SCIFFENA AutoBaud Detect logic SCIFFTX.14 SCIHBAUD. 15 - 8 Baud Rate MSbyte Register SCIRXD RXSHF Register SCIRXD RXWAKE LSPCLK SCIRXST.1 SCILBAUD. 7 - 0 Baud Rate LSbyte Register RXENA 8 SCICTL1.0 SCICTL2.1 Receive Data Buffer register SCIRXBUF.7-0 RXRDY 8 BRKDT RX FIFO _3 ----- RX FIFO_1 RX FIFO _0 SCIRXBUF.7-0 RX/BK INT ENA SCIRXST.6 RX FIFO Interrupts SCIRXST.5 RX Interrupt Logic RX FIFO registers SCIRXST.7 SCIRXST.4 - 2 RX Error FE OE PE RXINT To CPU RXFFOVF SCIFFRX.15 RX Error RX ERR INT ENA SCICTL1.6 SCI RX Interrupt select logic Figure 6-19. Serial Communications Interface (SCI) Module Block Diagram Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 83 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.5.2 www.ti.com Serial Communications Interface Register Descriptions The SCI port operation is configured and controlled by the registers listed in Table 6-15. Table 6-15. SCI-A Registers (1) NAME ADDRESS SIZE (x16) EALLOW PROTECTED SCICCRA 0x7050 1 No SCI-A Communications Control Register SCICTL1A 0x7051 1 No SCI-A Control Register 1 SCIHBAUDA 0x7052 1 No SCI-A Baud Register, High Bits SCILBAUDA 0x7053 1 No SCI-A Baud Register, Low Bits SCICTL2A 0x7054 1 No SCI-A Control Register 2 SCIRXSTA 0x7055 1 No SCI-A Receive Status Register SCIRXEMUA 0x7056 1 No SCI-A Receive Emulation Data Buffer Register SCIRXBUFA 0x7057 1 No SCI-A Receive Data Buffer Register SCITXBUFA 0x7059 1 No SCI-A Transmit Data Buffer Register SCIFFTXA (2) 0x705A 1 No SCI-A FIFO Transmit Register SCIFFRXA (2) 0x705B 1 No SCI-A FIFO Receive Register (2) 0x705C 1 No SCI-A FIFO Control Register 0x705F 1 No SCI-A Priority Control Register SCIFFCTA SCIPRIA (1) (2) 84 DESCRIPTION Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. These registers are new registers for the FIFO mode. Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.6 6.6.1 SPRS810 – APRIL 2012 Inter-Integrated Circuit (I2C) Inter-Integrated Circuit Device-Specific Information The device contains one I2C Serial Port. Figure 6-20 shows how the I2C peripheral module interfaces within the device. The I2C module has the following features: • Compliance with the Philips Semiconductors I2C-bus specification (version 2.1): – Support for 1-bit to 8-bit format transfers – 7-bit and 10-bit addressing modes – General call – START byte mode – Support for multiple master-transmitters and slave-receivers – Support for multiple slave-transmitters and master-receivers – Combined master transmit/receive and receive/transmit mode – Data transfer rate of from 10 kbps up to 400 kbps (I2C Fast-mode rate) • One 4-word receive FIFO and one 4-word transmit FIFO • One interrupt that can be used by the CPU. This interrupt can be generated as a result of one of the following conditions: – Transmit-data ready – Receive-data ready – Register-access ready – No-acknowledgment received – Arbitration lost – Stop condition detected – Addressed as slave • An additional interrupt that can be used by the CPU when in FIFO mode • Module enable/disable capability • Free data format mode Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 85 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com I2C Module I2CXSR I2CDXR TX FIFO FIFO Interrupt to CPU/PIE SDA RX FIFO Peripheral Bus I2CRSR Clock Synchronizer SCL I2CDRR Control/Status Registers CPU Prescaler Noise Filters I2C INT Interrupt to CPU/PIE Arbitrator A. B. The I2C registers are accessed at the SYSCLKOUT rate. The internal timing and signal waveforms of the I2C port are also at the SYSCLKOUT rate. The clock enable bit (I2CAENCLK) in the PCLKCRO register turns off the clock to the I2C port for low power operation. Upon reset, I2CAENCLK is clear, which indicates the peripheral internal clocks are off. Figure 6-20. I2C Peripheral Module Interfaces 86 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.6.2 SPRS810 – APRIL 2012 Inter-Integrated Circuit Register Descriptions The registers in Table 6-16 configure and control the I2C port operation. Table 6-16. I2C-A Registers 6.6.3 NAME ADDRESS EALLOW PROTECTED I2COAR 0x7900 No I2C own address register DESCRIPTION I2CIER 0x7901 No I2C interrupt enable register I2CSTR 0x7902 No I2C status register I2CCLKL 0x7903 No I2C clock low-time divider register I2CCLKH 0x7904 No I2C clock high-time divider register I2CCNT 0x7905 No I2C data count register I2CDRR 0x7906 No I2C data receive register I2CSAR 0x7907 No I2C slave address register I2CDXR 0x7908 No I2C data transmit register I2CMDR 0x7909 No I2C mode register I2CISRC 0x790A No I2C interrupt source register I2CPSC 0x790C No I2C prescaler register I2CFFTX 0x7920 No I2C FIFO transmit register I2CFFRX 0x7921 No I2C FIFO receive register I2CRSR – No I2C receive shift register (not accessible to the CPU) I2CXSR – No I2C transmit shift register (not accessible to the CPU) Inter-Integrated Circuit Electrical Data/Timing Table 6-17. I2C Timing TEST CONDITIONS MIN I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately MAX UNIT 400 kHz fSCL SCL clock frequency vil Low level input voltage Vih High level input voltage Vhys Input hysteresis Vol Low level output voltage 3 mA sink current tLOW Low period of SCL clock I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately 1.3 μs tHIGH High period of SCL clock I2C clock module frequency is between 7 MHz and 12 MHz and I2C prescaler and clock divider registers are configured appropriately 0.6 μs lI Input current with an input voltage between 0.1 VDDIO and 0.9 VDDIO MAX 0.3 VDDIO 0.7 VDDIO V 0.05 VDDIO 0 –10 V 0.4 10 Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated V V μA 87 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.7 6.7.1 www.ti.com Enhanced Pulse Width Modulator (ePWM) Enhanced Pulse Width Modulator Device-Specific Information The devices contain up to three enhanced PWM Modules (ePWM1/2/3). Figure 6-21 shows a block diagram of multiple ePWM modules. Figure 6-22 shows the signal interconnections with the ePWM. See the TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRUGE9) for more details. EPWMSYNCI EPWM1SYNCI EPWM1B EPWM1TZINT ePWM1 Module EPWM1INT TZ1 to TZ3 EPWM2TZINT PIE EPWM2INT TZ5 EPWMxTZINT TZ6 EPWMxINT CLOCKFAIL EMUSTOP EPWM1ENCLK TBCLKSYNC eCAPI EPWM1SYNCO EPWM1SYNCO EPWM2SYNCI COMPOUT1 COMPOUT2 TZ1 to TZ3 EPWM2B ePWM2 Module COMP TZ5 TZ6 CLOCKFAIL EMUSTOP EPWM2ENCLK TBCLKSYNC EPWM1A H R P W M EPWM2A EPWMxA G P I O ADC Peripheral Bus EPWM2SYNCO SOCA1 SOCB1 SOCA2 M U X EPWMxB EPWMxSYNCI SOCB2 SOCAx TZ1 to TZ3 ePWMx Module SOCBx TZ5 TZ6 CLOCKFAIL EMUSTOP EPWMxENCLK TBCLKSYNC System Control C28x CPU SOCA1 SOCA2 SPCAx ADCSOCAO Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) SOCB1 SOCB2 SPCBx ADCSOCBO Pulse Stretch (32 SYSCLKOUT Cycles, Active-Low Output) Figure 6-21. ePWM 88 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Time-Base (TB) CTR=ZERO TBPRD Shadow (24) Sync In/Out Select Mux CTR=CMPB Disabled TBPRD Active (24) EPWMxSYNCO CTR=PRD TBCTL[SYNCOSEL] TBCTL[PHSEN] Counter Up/Down (16 Bit) TBCTL[SWFSYNC] (Software Forced Sync) CTR=ZERO TCBNT Active (16) CTR_Dir CTR=PRD CTR=ZERO CTR=PRD or ZERO CTR=CMPA TBPHSHR (8) 16 TBPHS Active (24) Phase Control CTR=CMPB CTR_Dir DCAEVT1.soc DCBEVT1.soc CTR=CMPA (A) EPWMxSYNCI DCAEVT1.sync DCBEVT1.sync EPWMxINT Event Trigger and Interrupt (ET) EPWMxSOCA EPWMxSOCB EPWMxSOCA (A) ADC EPWMxSOCB Action Qualifier (AQ) 16 CMPA Active (24) CMPA Shadow (24) EPWMxA EPWMA Dead Band (DB) CTR=CMPB PWM Chopper (PC) Trip Zone (TZ) 16 CMPB Active (16) EPWMxB EPWMB EPWMxTZINT CMPB Shadow (16) TZ1 to TZ3 CTR=ZERO DCAEVT1.inter DCBEVT1.inter DCAEVT2.inter DCBEVT2.inter EMUSTOP CLOCKFAIL DCAEVT1.force DCAEVT2.force DCBEVT1.force DCBEVT2.force A. (A) (A) (A) (A) These events are generated by the Type 1 ePWM digital compare (DC) submodule based on the levels of the COMPxOUT and TZ signals. Figure 6-22. ePWM Sub-Modules Showing Critical Internal Signal Interconnections Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 89 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.7.2 www.ti.com Enhanced Pulse Width Modulator Register Descriptions Table 6-18 shows the complete ePWM register set per module. Table 6-18. ePWM Control and Status Registers ePWM1 ePWM2 ePWM3 SIZE (x16) / #SHADOW TBCTL 0x6800 0x6840 0x6880 1/0 Time Base Control Register TBSTS 0x6801 0x6841 0x6881 1/0 Time Base Status Register Reserved 0x6802 0x6842 0x6882 1/0 Reserved TBPHS 0x6803 0x6843 0x6883 1/0 Time Base Phase Register TBCTR 0x6804 0x6844 0x6884 1/0 Time Base Counter Register TBPRD 0x6805 0x6845 0x6885 1/1 Time Base Period Register Set Reserved 0x6806 0x6846 0x6886 1/1 Reserved CMPCTL 0x6807 0x6847 0x6887 1/0 Counter Compare Control Register Reserved 0x6808 0x6848 0x6888 1/1 Reserved CMPA 0x6809 0x6849 0x6889 1/1 Counter Compare A Register Set CMPB 0x680A 0x684A 0x688A 1/1 Counter Compare B Register Set NAME DESCRIPTION AQCTLA 0x680B 0x684B 0x688B 1/0 Action Qualifier Control Register For Output A AQCTLB 0x680C 0x684C 0x688C 1/0 Action Qualifier Control Register For Output B AQSFRC 0x680D 0x684D 0x688D 1/0 Action Qualifier Software Force Register AQCSFRC 0x680E 0x684E 0x688E 1/1 Action Qualifier Continuous S/W Force Register Set DBCTL 0x680F 0x684F 0x688F 1/1 Dead-Band Generator Control Register DBRED 0x6810 0x6850 0x6890 1/0 Dead-Band Generator Rising Edge Delay Count Register DBFED 0x6811 0x6851 0x6891 1/0 Dead-Band Generator Falling Edge Delay Count Register TZSEL 0x6812 0x6852 0x6892 1/0 Trip Zone Select Register (1) TZDCSEL 0x6813 0x6853 0x6893 1/0 Trip Zone Digital Compare Register TZCTL 0x6814 0x6854 0x6894 1/0 Trip Zone Control Register (1) TZEINT 0x6815 0x6855 0x6895 1/0 Trip Zone Enable Interrupt Register (1) TZFLG 0x6816 0x6856 0x6896 1/0 Trip Zone Flag Register TZCLR 0x6817 0x6857 0x6897 1/0 Trip Zone Clear Register (1) TZFRC 0x6818 0x6858 0x6898 1/0 Trip Zone Force Register (1) ETSEL 0x6819 0x6859 0x6899 1/0 Event Trigger Selection Register ETPS 0x681A 0x685A 0x689A 1/0 Event Trigger Prescale Register ETFLG 0x681B 0x685B 0x689B 1/0 Event Trigger Flag Register ETCLR 0x681C 0x685C 0x689C 1/0 Event Trigger Clear Register ETFRC 0x681D 0x685D 0x689D 1/0 Event Trigger Force Register PCCTL 0x681E 0x685E 0x689E 1/0 PWM Chopper Control Register Reserved 0x6820 0x6860 0x68A0 1/0 Reserved Reserved 0x6821 - - 1/0 Reserved Reserved 0x6826 - - 1/0 Reserved Reserved 0x6828 0x6868 0x68A8 1/0 Reserved Reserved 0x682A 0x686A 0x68AA 1 / W (2) Reserved (2) (1) TBPRDM 0x682B 0x686B 0x68AB 1/W Reserved 0x682C 0x686C 0x68AC 1 / W (2) Reserved CMPAM 0x682D 0x686D 0x68AD 1 / W (2) Compare A Register Mirror DCTRIPSEL 0x6830 0x6870 0x68B0 1/0 (1) (2) Registers that are EALLOW protected. W = Write to shadow register 90 Peripheral Information and Timings Time Base Period Register Mirror Digital Compare Trip Select Register (1) Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 Table 6-18. ePWM Control and Status Registers (continued) ePWM1 ePWM2 ePWM3 SIZE (x16) / #SHADOW DCACTL 0x6831 0x6871 0x68B1 1/0 Digital Compare A Control Register (1) DCBCTL 0x6832 0x6872 0x68B2 1/0 Digital Compare B Control Register (1) DCFCTL 0x6833 0x6873 0x68B3 1/0 Digital Compare Filter Control Register (1) DCCAPCT 0x6834 0x6874 0x68B4 1/0 Digital Compare Capture Control Register (1) DCFOFFSET 0x6835 0x6875 0x68B5 1/1 Digital Compare Filter Offset Register DCFOFFSETCNT 0x6836 0x6876 0x68B6 1/0 Digital Compare Filter Offset Counter Register DCFWINDOW 0x6837 0x6877 0x68B7 1/0 Digital Compare Filter Window Register DCFWINDOWCNT 0x6838 0x6878 0x68B8 1/0 Digital Compare Filter Window Counter Register DCCAP 0x6839 0x6879 0x68B9 1/1 Digital Compare Counter Capture Register NAME 6.7.3 DESCRIPTION Enhanced Pulse Width Modulator Electrical Data/Timing PWM refers to PWM outputs on ePWM1–3. Table 6-19 shows the PWM timing requirements and Table 620, switching characteristics. Table 6-19. ePWM Timing Requirements (1) TEST CONDITIONS tw(SYCIN) Sync input pulse width MAX UNIT 2tc(SCO) cycles Synchronous 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles With input qualifier (1) MIN Asynchronous For an explanation of the input qualifier parameters, see Table 6-30. Table 6-20. ePWM Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tw(PWM) Pulse duration, PWMx output high/low tw(SYNCOUT) Sync output pulse width td(PWM)tza Delay time, trip input active to PWM forced high Delay time, trip input active to PWM forced low td(TZ-PWM)HZ Delay time, trip input active to PWM Hi-Z TEST CONDITIONS MIN MAX UNIT 33.33 ns 8tc(SCO) no pin load cycles 25 ns 20 ns Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 91 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.7.3.1 www.ti.com Trip-Zone Input Timing Table 6-21. Trip-Zone Input Timing Requirements (1) MIN tw(TZ) Pulse duration, TZx input low UNIT Asynchronous 2tc(TBCLK) cycles Synchronous 2tc(TBCLK) cycles 2tc(TBCLK) + tw(IQSW) cycles With input qualifier (1) MAX For an explanation of the input qualifier parameters, see Table 6-30. XCLKOUT(A) tw(TZ) TZ td(TZ-PWM)HZ PWM(B) A. B. TZ - TZ1, TZ2, TZ3 PWM refers to all the PWM pins in the device. The state of the PWM pins after TZ is taken high depends on the PWM recovery software. Figure 6-23. PWM Hi-Z Characteristics 92 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.8 SPRS810 – APRIL 2012 Enhanced Capture Module (eCAP) 6.8.1 Enhanced Capture Module Device-Specific Information SYNC The device contains an enhanced capture (eCAP) module. Figure 6-24 shows a functional block diagram of a module. SYNCIn SYNCOut CTRPHS (phase register−32 bit) TSCTR (counter−32 bit) APWM mode OVF RST CTR_OVF CTR [0−31] Delta−mode PRD [0−31] CMP [0−31] PWM compare logic 32 CTR=PRD CTR [0−31] CTR=CMP 32 32 CAP1 (APRD active) APRD shadow 32 32 LD LD1 MODE SELECT PRD [0−31] Polarity select 32 CMP [0−31] CAP2 (ACMP active) 32 LD LD2 32 CAP3 (APRD shadow) LD 32 CAP4 (ACMP shadow) LD Polarity select Event qualifier ACMP shadow eCAPx Event Pre-scale Polarity select LD3 LD4 Polarity select 4 Capture events 4 CEVT[1:4] to PIE Interrupt Trigger and Flag control CTR_OVF Continuous / Oneshot Capture Control CTR=PRD CTR=CMP Figure 6-24. eCAP Functional Block Diagram The eCAP module is clocked at the SYSCLKOUT rate. The clock enable bits (ECAP1 ENCLK) in the PCLKCR1 register turn off the eCAP module individually (for low power operation). Upon reset, ECAP1ENCLK is set to low, indicating that the peripheral clock is off. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 93 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.8.2 www.ti.com Enhanced Capture Module Register Descriptions Table 6-22 lists the eCAP Control and Status Registers. Table 6-22. eCAP Control and Status Registers NAME eCAP1 SIZE (x16) TSCTR 0x6A00 2 EALLOW PROTECTED Time-Stamp Counter DESCRIPTION CTRPHS 0x6A02 2 Counter Phase Offset Value Register CAP1 0x6A04 2 Capture 1 Register CAP2 0x6A06 2 Capture 2 Register CAP3 0x6A08 2 Capture 3 Register CAP4 0x6A0A 2 Capture 4 Register Reserved 0x6A0C – 0x6A12 8 Reserved ECCTL1 0x6A14 1 Capture Control Register 1 ECCTL2 0x6A15 1 Capture Control Register 2 ECEINT 0x6A16 1 Capture Interrupt Enable Register ECFLG 0x6A17 1 Capture Interrupt Flag Register ECCLR 0x6A18 1 Capture Interrupt Clear Register ECFRC 0x6A19 1 Capture Interrupt Force Register Reserved 0x6A1A – 0x6A1F 6 Reserved 6.8.3 Enhanced Capture Module Electrical Data/Timing Table 6-23 shows the eCAP timing requirement and Table 6-24 shows the eCAP switching characteristics. Table 6-23. Enhanced Capture (eCAP) Timing Requirement (1) TEST CONDITIONS tw(CAP) Capture input pulse width MIN Asynchronous Synchronous With input qualifier (1) MAX UNIT 2tc(SCO) cycles 2tc(SCO) cycles 1tc(SCO) + tw(IQSW) cycles For an explanation of the input qualifier parameters, see Table 6-30. Table 6-24. eCAP Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER tw(APWM) 94 Pulse duration, APWMx output high/low Peripheral Information and Timings TEST CONDITIONS MIN 20 MAX UNIT ns Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.9 6.9.1 SPRS810 – APRIL 2012 JTAG Port JTAG Port Device-Specific Information On the 2802x0 device, the JTAG port is reduced to 5 pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, TMS and TDO pins are also GPIO pins. The TRST signal selects either JTAG or GPIO operating mode for the pins in Figure 6-25. During emulation/debug, the GPIO function of these pins are not available. If the GPIO38/TCK/XCLKIN pin is used to provide an external clock, an alternate clock source should be used to clock the device during emulation/debug since this pin will be needed for the TCK function. NOTE In 2802x0 devices, the JTAG pins may also be used as GPIO pins. Care should be taken in the board design to ensure that the circuitry connected to these pins do not affect the emulation capabilities of the JTAG pin function. Any circuitry connected to these pins should not prevent the emulator from driving (or being driven by) the JTAG pins for successful debug. TRST = 0: JTAG Disabled (GPIO Mode) TRST = 1: JTAG Mode TRST TRST XCLKIN GPIO38_in TCK TCK/GPIO38 GPIO38_out C28x Core GPIO37_in TDO/GPIO37 1 0 TDO GPIO37_out GPIO36_in 1 TMS/GPIO36 GPIO36_out 1 TMS 0 GPIO35_in 1 TDI/GPIO35 GPIO35_out 1 TDI 0 Figure 6-25. JTAG/GPIO Multiplexing Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 95 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 6.9.1.1 www.ti.com Emulator Connection Without Signal Buffering for the MCU Figure 6-26 shows the connection between the MCU and JTAG header for a single-processor configuration. If the distance between the JTAG header and the MCU is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-26 shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see Section 3.2, Terminal Functions. 6 inches or less VDDIO VDDIO 13 14 2 TRST 1 TMS 3 TDI TDO TCK 7 11 9 EMU0 PD EMU1 TRST GND TMS GND TDI GND TDO GND TCK GND 5 4 6 8 10 12 TCK_RET MCU JTAG Header A. See Figure 6-25 for JTAG/GPIO multiplexing. Figure 6-26. Emulator Connection Without Signal Buffering for the MCU NOTE The 2802x0 devices do not have EMU0/EMU1 pins. For designs that have a JTAG Header on-board, the EMU0/EMU1 pins on the header must be tied to VDDIO through a 4.7-kΩ (typical) resistor. 96 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 6.10 General-Purpose Input/Output (GPIO) 6.10.1 General-Purpose Input/Output Device-Specific Information The GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging I/O capability. Table 6-25. GPIOA MUX (1) (2) DEFAULT AT RESET PRIMARY I/O FUNCTION PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3 GPAMUX1 REGISTER BITS (GPAMUX1 BITS = 00) (GPAMUX1 BITS = 01) (GPAMUX1 BITS = 10) (GPAMUX1 BITS = 11) 1-0 GPIO0 EPWM1A (O) Reserved Reserved 3-2 GPIO1 EPWM1B (O) Reserved COMP1OUT (O) 5-4 GPIO2 EPWM2A (O) Reserved Reserved 7-6 GPIO3 EPWM2B (O) Reserved COMP2OUT (3) (O) 9-8 GPIO4 EPWM3A (O) Reserved Reserved 11-10 GPIO5 EPWM3B (O) Reserved ECAP1 (I/O) 13-12 GPIO6 Reserved EPWMSYNCI (I) EPWMSYNCO (O) 15-14 GPIO7 Reserved SCIRXDA (I) Reserved 17-16 Reserved Reserved Reserved Reserved 19-18 Reserved Reserved Reserved Reserved 21-20 Reserved Reserved Reserved Reserved 23-22 Reserved Reserved Reserved Reserved 25-24 GPIO12 TZ1 (I) SCITXDA (O) Reserved 27-26 Reserved Reserved Reserved Reserved 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved GPAMUX2 REGISTER BITS (GPAMUX2 BITS = 00) (GPAMUX2 BITS = 01) (GPAMUX2 BITS = 10) (GPAMUX2 BITS = 11) 1-0 GPIO16 SPISIMOA (I/O) Reserved TZ2 (I) 3-2 GPIO17 SPISOMIA (I/O) Reserved TZ3 (I) 5-4 GPIO18 SPICLKA (I/O) SCITXDA (O) XCLKOUT (O) 7-6 GPIO19/XCLKIN SPISTEA (I/O) SCIRXDA (I) ECAP1 (I/O) 9-8 Reserved Reserved Reserved Reserved 11-10 Reserved Reserved Reserved Reserved 13-12 Reserved Reserved Reserved Reserved 15-14 Reserved Reserved Reserved Reserved 17-16 Reserved Reserved Reserved Reserved 19-18 Reserved Reserved Reserved Reserved 21-20 Reserved Reserved Reserved Reserved 23-22 Reserved Reserved Reserved Reserved 25-24 GPIO28 SCIRXDA (I) SDAA (I/OD) TZ2 (I) 27-26 GPIO29 SCITXDA (O) SCLA (I/OD) TZ3 (I) 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved (1) (2) (3) The word reserved means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. I = Input, O = Output, OD = Open Drain These functions are not available in the 38-pin package. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 97 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 6-26. GPIOB MUX (1) DEFAULT AT RESET PRIMARY I/O FUNCTION PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 PERIPHERAL SELECTION 3 GPBMUX1 REGISTER BITS (GPBMUX1 BITS = 00) (GPBMUX1 BITS = 01) (GPBMUX1 BITS = 10) (GPBMUX1 BITS = 11) 1-0 GPIO32 (2) SDAA (2) (I/OD) EPWMSYNCI (2) (I) 3-2 (2) GPIO33 5-4 (1) (2) SCLA (2) (I/OD) EPWMSYNCO (2) (O) ADCSOCAO (2) (O) ADCSOCBO (2) (O) GPIO34 COMP2OUT (O) Reserved Reserved 7-6 GPIO35 (TDI) Reserved Reserved Reserved 9-8 GPIO36 (TMS) Reserved Reserved Reserved 11-10 GPIO37 (TDO) Reserved Reserved Reserved 13-12 GPIO38/XCLKIN (TCK) Reserved Reserved Reserved 15-14 Reserved Reserved Reserved Reserved 17-16 Reserved Reserved Reserved Reserved 19-18 Reserved Reserved Reserved Reserved 21-20 Reserved Reserved Reserved Reserved 23-22 Reserved Reserved Reserved Reserved 25-24 Reserved Reserved Reserved Reserved 27-26 Reserved Reserved Reserved Reserved 29-28 Reserved Reserved Reserved Reserved 31-30 Reserved Reserved Reserved Reserved I = Input, O = Output, OD = Open Drain These pins are not available in the 38-pin package. Table 6-27. Analog MUX (1) DEFAULT AT RESET AIOx AND PERIPHERAL SELECTION 1 PERIPHERAL SELECTION 2 AND PERIPHERAL SELECTION 3 AIOMUX1 REGISTER BITS AIOMUX1 BITS = 0,x AIOMUX1 BITS = 1,x 1-0 ADCINA0 (I) 3-2 5-4 7-6 (I) AIO2 (I/O) ADCINA3 (2) 11-10 ADCINA5 (I) 13-12 AIO6 (I/O) 19-18 21-20 23-22 ADCINA7 (2) (2) (2) (I) ADCINA3 (2) (I) (I) (I) ADCINA7 (2) (I) ADCINB0 (I) ADCINB1 (2) (I) ADCINB2 (I), COMP1B (I) ADCINB3 (2) (I) AIO12 (I/O) 27-26 ADCINB5 (I) ADCINB5 (I) 29-28 AIO14 (I/O) ADCINB6 (I) 31-30 ADCINB7 (I) ADCINA5 (I) 25-24 (2) (3) ADCINA6 (I) (I) AIO10 (I/O) ADCINB3 (2) ADCINA4 (I), COMP2A ADCINB0 (I) ADCINB1 ADCINA0 (I) ADCINA1 ADCINA2 (I), COMP1A (I) (I) AIO4 (I/O) 17-16 98 (2) 9-8 15-14 (1) (2) (3) ADCINA1 (I) ADCINB4 (I), COMP2B ADCINB7 (2) (3) (I) (I) I = Input, O = Output These pins are not available in the 38-pin package. These functions are not available in the 38-pin package. Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 The user can select the type of input qualification for each GPIO pin via the GPxQSEL1/2 registers from four choices: • Synchronization To SYSCLKOUT Only (GPxQSEL1/2 = 0, 0): This is the default mode of all GPIO pins at reset and it simply synchronizes the input signal to the system clock (SYSCLKOUT). • Qualification Using Sampling Window (GPxQSEL1/2 = 0, 1 and 1, 0): In this mode the input signal, after synchronization to the system clock (SYSCLKOUT), is qualified by a specified number of cycles before the input is allowed to change. • The sampling period is specified by the QUALPRD bits in the GPxCTRL register and is configurable in groups of 8 signals. It specifies a multiple of SYSCLKOUT cycles for sampling the input signal. The sampling window is either 3-samples or 6-samples wide and the output is only changed when ALL samples are the same (all 0s or all 1s) as shown in Figure 4-18 (for 6 sample mode). • No Synchronization (GPxQSEL1/2 = 1,1): This mode is used for peripherals where synchronization is not required (synchronization is performed within the peripheral). Due to the multi-level multiplexing that is required on the device, there may be cases where a peripheral input signal can be mapped to more then one GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 99 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com GPIOXINT1SEL GPIOLMPSEL GPIOXINT2SEL LPMCR0 GPIOXINT3SEL External Interrupt MUX Low P ower Modes Block Asynchronous path PIE GPxDAT (read) GPxQSEL1/2 GPxCTRL GPxPUD Input Qualification Internal Pullup 00 N/C 01 Peripheral 1 Input 10 Peripheral 2 Input 11 Peripheral 3 Input GPxTOGGLE Asynchronous path GPIOx pin GPxCLEAR GPxSET 00 01 GPxDAT (latch) Peripheral 1 Output 10 Peripheral 2 Output 11 Peripheral 3 Output High Impedance Output Control 00 0 = Input, 1 = Output XRS = Default at Reset A. B. C. GPxDIR (latch) 01 Peripheral 1 Output Enable 10 Peripheral 2 Output Enable 11 Peripheral 3 Output Enable GPxMUX1/2 x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected. GPxDAT latch/read are accessed at the same memory location. This is a generic GPIO MUX block diagram. Not all options may be applicable for all GPIO pins. See the TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide (literature number SPRUFN3) for pin-specific variations. Figure 6-27. GPIO Multiplexing 100 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 6.10.2 General-Purpose Input/Output Register Descriptions The device supports 22 GPIO pins. The GPIO control and data registers are mapped to Peripheral Frame 1 to enable 32-bit operations on the registers (along with 16-bit operations). Table 6-28 shows the GPIO register mapping. Table 6-28. GPIO Registers NAME ADDRESS SIZE (x16) DESCRIPTION GPIO CONTROL REGISTERS (EALLOW PROTECTED) GPACTRL 0x6F80 2 GPIO A Control Register (GPIO0 to 31) GPAQSEL1 0x6F82 2 GPIO A Qualifier Select 1 Register (GPIO0 to 15) GPAQSEL2 0x6F84 2 GPIO A Qualifier Select 2 Register (GPIO16 to 31) GPAMUX1 0x6F86 2 GPIO A MUX 1 Register (GPIO0 to 15) GPAMUX2 0x6F88 2 GPIO A MUX 2 Register (GPIO16 to 31) GPADIR 0x6F8A 2 GPIO A Direction Register (GPIO0 to 31) GPAPUD 0x6F8C 2 GPIO A Pull Up Disable Register (GPIO0 to 31) GPBCTRL 0x6F90 2 GPIO B Control Register (GPIO32 to 38) GPBQSEL1 0x6F92 2 GPIO B Qualifier Select 1 Register (GPIO32 to 38) GPBMUX1 0x6F96 2 GPIO B MUX 1 Register (GPIO32 to 38) GPBDIR 0x6F9A 2 GPIO B Direction Register (GPIO32 to 38) GPBPUD 0x6F9C 2 GPIO B Pull Up Disable Register (GPIO32 to 38) AIOMUX1 0x6FB6 2 Analog, I/O mux 1 register (AIO0 to AIO15) AIODIR 0x6FBA 2 Analog, I/O Direction Register (AIO0 to AIO15) GPADAT 0x6FC0 2 GPIO A Data Register (GPIO0 to 31) GPASET 0x6FC2 2 GPIO A Data Set Register (GPIO0 to 31) GPACLEAR 0x6FC4 2 GPIO A Data Clear Register (GPIO0 to 31) GPATOGGLE 0x6FC6 2 GPIO A Data Toggle Register (GPIO0 to 31) GPBDAT 0x6FC8 2 GPIO B Data Register (GPIO32 to 38) GPBSET 0x6FCA 2 GPIO B Data Set Register (GPIO32 to 38) GPIO DATA REGISTERS (NOT EALLOW PROTECTED) GPBCLEAR 0x6FCC 2 GPIO B Data Clear Register (GPIO32 to 38) GPBTOGGLE 0x6FCE 2 GPIO B Data Toggle Register (GPIO32 to 38) AIODAT 0x6FD8 2 Analog I/O Data Register (AIO0 to AIO15) AIOSET 0x6FDA 2 Analog I/O Data Set Register (AIO0 to AIO15) AIOCLEAR 0x6FDC 2 Analog I/O Data Clear Register (AIO0 to AIO15) AIOTOGGLE 0x6FDE 2 Analog I/O Data Toggle Register (AIO0 to AIO15) GPIO INTERRUPT AND LOW POWER MODES SELECT REGISTERS (EALLOW PROTECTED) GPIOXINT1SEL 0x6FE0 1 XINT1 GPIO Input Select Register (GPIO0 to 31) GPIOXINT2SEL 0x6FE1 1 XINT2 GPIO Input Select Register (GPIO0 to 31) GPIOXINT3SEL 0x6FE2 1 XINT3 GPIO Input Select Register (GPIO0 to 31) GPIOLPMSEL 0x6FE8 2 LPM GPIO Select Register (GPIO0 to 31) NOTE There is a two-SYSCLKOUT cycle delay from when the write to the GPxMUXn/AIOMUXn and GPxQSELn registers occurs to when the action is valid. Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 101 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 6.10.3 General-Purpose Input/Output Electrical Data/Timing 6.10.3.1 GPIO - Output Timing Table 6-29. General-Purpose Output Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN MAX (1) tr(GPO) Rise time, GPIO switching low to high All GPIOs 13 tf(GPO) Fall time, GPIO switching high to low All GPIOs 13 (1) tfGPO Toggling frequency (1) 15 UNIT ns ns MHz Rise time and fall time vary with electrical loading on I/O pins. Values given in Table 6-29 are applicable for a 40-pF load on I/O pins. GPIO tf(GPO) tr(GPO) Figure 6-28. General-Purpose Output Timing 102 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 6.10.3.2 SPRS810 – APRIL 2012 GPIO - Input Timing Table 6-30. General-Purpose Input Timing Requirements MIN tw(SP) Sampling period tw(IQSW) Input qualifier sampling window tw(GPI) (1) (2) (2) UNIT QUALPRD = 0 1tc(SCO) cycles QUALPRD ≠ 0 2tc(SCO) * QUALPRD cycles tw(SP) * (n (1) – 1) cycles 2tc(SCO) cycles tw(IQSW) + tw(SP) + 1tc(SCO) cycles Synchronous mode Pulse duration, GPIO low/high MAX With input qualifier "n" represents the number of qualification samples as defined by GPxQSELn register. For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal. (A) GPIO Signal GPxQSELn = 1,0 (6 samples) 1 1 0 0 0 0 0 0 0 1 tw(SP) 0 0 0 1 1 1 1 1 Sampling Window 1 1 1 Sampling Period determined by GPxCTRL[QUALPRD] tw(IQSW) 1 [(SYSCLKOUT cycle * 2 * QUALPRD) * 5 (B) (C) ] SYSCLKOUT QUALPRD = 1 (SYSCLKOUT/2) (D) Output From Qualifier A. B. C. D. This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled). The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins. The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used. In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. Figure 6-29. Sampling Mode Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 103 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com 6.10.3.3 Sampling Window Width for Input Signals The following section summarizes the sampling window width for input signals for various input qualifier configurations. Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0 Sampling frequency = SYSCLKOUT, if QUALPRD = 0 Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0 In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT. Sampling period = SYSCLKOUT cycle, if QUALPRD = 0 In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register. Case 1: Qualification using 3 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0 Case 2: Qualification using 6 samples Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0 XCLKOUT GPIOxn tw(GPI) Figure 6-30. General-Purpose Input Timing VDDIO > 1 MS 2 pF VSS VSS Figure 6-31. Input Resistance Model for a GPIO Pin With an Internal Pull-up 104 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 6.10.3.4 Low-Power Mode Wakeup Timing Table 6-31 shows the timing requirements, Table 6-32 shows the switching characteristics, and Figure 632 shows the timing diagram for IDLE mode. Table 6-31. IDLE Mode Timing Requirements (1) MIN tw(WAKE-INT) (1) Pulse duration, external wake-up signal Without input qualifier NOM MAX 2tc(SCO) With input qualifier UNIT cycles 5tc(SCO) + tw(IQSW) For an explanation of the input qualifier parameters, see Table 6-30. Table 6-32. IDLE Mode Switching Characteristics (1) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS Delay time, external wake signal to program execution resume td(WAKE-IDLE) • Wake-up from Flash – Flash module in active state Without input qualifier • Wake-up from Flash – Flash module in sleep state Without input qualifier Wake-up from SARAM Without input qualifier • MIN With input qualifier With input qualifier With input qualifier (1) (2) TYP MAX (2) UNIT cycles 20tc(SCO) cycles 20tc(SCO) + tw(IQSW) 1050tc(SCO) cycles 1050tc(SCO) + tw(IQSW) 20tc(SCO) cycles 20tc(SCO) + tw(IQSW) For an explanation of the input qualifier parameters, see Table 6-30. This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake-up) signal involves additional latency. td(WAKE−IDLE) Address/Data (internal) XCLKOUT tw(WAKE−INT) WAKE INT A. B. (A)(B) WAKE INT can be any enabled interrupt, WDINT or XRS. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-32. IDLE Entry and Exit Timing Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 105 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Table 6-33. STANDBY Mode Timing Requirements tw(WAKE-INT) (1) Pulse duration, external wake-up signal TEST CONDITIONS MIN Without input qualification 3tc(OSCCLK) With input qualification (1) NOM MAX UNIT cycles (2 + QUALSTDBY) * tc(OSCCLK) QUALSTDBY is a 6-bit field in the LPMCR0 register. Table 6-34. STANDBY Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER td(IDLE-XCOL) TEST CONDITIONS Delay time, IDLE instruction executed to XCLKOUT low MIN TYP 32tc(SCO) MAX UNIT 45tc(SCO) cycles Delay time, external wake signal to program execution resume (1) • td(WAKE-STBY) • Wake up from flash – Flash module in active state Without input qualifier Wake up from flash – Flash module in sleep state Without input qualifier With input qualifier With input qualifier cycles 100tc(SCO) 100tc(SCO) + tw(WAKE-INT) 1125tc(SCO) 1125tc(SCO) + tw(WAKE-INT) Without input qualifier • (1) 106 Wake up from SARAM With input qualifier cycles 100tc(SCO) 100tc(SCO) + tw(WAKE-INT) cycles cycles This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. execution of an ISR (triggered by the wake up signal) involves additional latency. Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 (C) (A) (B) Device Status (F) (D)(E) STANDBY (G) STANDBY Normal Execution Flushing Pipeline Wake-up (H) Signal tw(WAKE-INT) td(WAKE-STBY) X1/X2 or XCLKIN XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. IDLE instruction is executed to put the device into STANDBY mode. The PLL block responds to the STANDBY signal. SYSCLKOUT is held for the number of cycles indicated below before being turned off: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. Clock to the peripherals are turned off. However, the PLL and watchdog are not shut down. The device is now in STANDBY mode. The external wake-up signal is driven active. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. After a latency period, the STANDBY mode is exited. Normal execution resumes. The device will respond to the interrupt (if enabled). From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-33. STANDBY Entry and Exit Timing Diagram Table 6-35. HALT Mode Timing Requirements MIN NOM MAX UNIT tw(WAKE-GPIO) Pulse duration, GPIO wake-up signal toscst + 2tc(OSCCLK) cycles tw(WAKE-XRS) Pulse duration, XRS wakeup signal toscst + 8tc(OSCCLK) cycles Table 6-36. HALT Mode Switching Characteristics over recommended operating conditions (unless otherwise noted) PARAMETER td(IDLE-XCOL) Delay time, IDLE instruction executed to XCLKOUT low tp PLL lock-up time td(WAKE-HALT) Delay time, PLL lock to program execution resume • Wake up from flash – Flash module in sleep state • Wake up from SARAM MIN 32tc(SCO) TYP MAX UNIT 45tc(SCO) cycles 1 ms 1125tc(SCO) cycles 35tc(SCO) cycles Peripheral Information and Timings Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 107 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com (C) (A) (F) (B) Device Status HALT Flushing Pipeline (H) (G) (D)(E) HALT PLL Lock-up Time Wake-up Latency Normal Execution (I) GPIOn td(WAKE−HALT ) tw(WAKE-GPIO) tp X1/X2 or XCLKIN Oscillator Start-up Time XCLKOUT td(IDLE−XCOL) A. B. C. D. E. F. G. H. I. IDLE instruction is executed to put the device into HALT mode. The PLL block responds to the HALT signal. SYSCLKOUT is held for the number of cycles indicated below before oscillator is turned off and the CLKIN to the core is stopped: • 16 cycles, when DIVSEL = 00 or 01 • 32 cycles, when DIVSEL = 10 • 64 cycles, when DIVSEL = 11 This delay enables the CPU pipeline and any other pending operations to flush properly. Clocks to the peripherals are turned off and the PLL is shut down. If a quartz crystal or ceramic resonator is used as the clock source, the internal oscillator is shut down as well. The device is now in HALT mode and consumes absolute minimum power. It is possible to keep the zero-pin internal oscillators (INTOSC1 and INTOSC2) and the watchdog alive in HALT mode. This is done by writing to the appropriate bits in the CLKCTL register. When the GPIOn pin (used to bring the device out of HALT) is driven low, the oscillator is turned on and the oscillator wake-up sequence is initiated. The GPIO pin should be driven high only after the oscillator has stabilized. This enables the provision of a clean clock signal during the PLL lock sequence. Since the falling edge of the GPIO pin asynchronously begins the wakeup procedure, care should be taken to maintain a low noise environment prior to entering and during HALT mode. The wake-up signal fed to a GPIO pin to wake up the device must meet the minimum pulse width requirement. Furthermore, this signal must be free of glitches. If a noisy signal is fed to a GPIO pin, the wake-up behavior of the device will not be deterministic and the device may not exit low-power mode for subsequent wake-up pulses. Once the oscillator has stabilized, the PLL lock sequence is initiated, which takes 1 ms. When CLKIN to the core is enabled, the device will respond to the interrupt (if enabled), after a latency. The HALT mode is now exited. Normal operation resumes. From the time the IDLE instruction is executed to place the device into low-power mode (LPM), wakeup should not be initiated until at least 4 OSCCLK cycles have elapsed. Figure 6-34. HALT Wake-Up Using GPIOn 108 Peripheral Information and Timings Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 7 Device and Documentation Support 7.1 7.1.1 Device Support Getting Started This section gives a brief overview of the steps to take when first developing for a C28x device. For more detail on each of these steps, see the following: • Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0). • C2000 Getting Started Website (http://www.ti.com/c2000getstarted) • TMS320F28x MCU Development and Experimenter's Kits (http://www.ti.com/f28xkits) 7.1.2 Development Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of MCUs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of 2802x0-based applications: Software Development Tools • Code Composer Studio™ Integrated Development Environment (IDE) – C/C++ Compiler – Code generation tools – Assembler/Linker – Cycle Accurate Simulator • Application algorithms • Sample applications code Hardware Development Tools • Development and evaluation boards • JTAG-based emulators - XDS510™ class, XDS560™ emulator, XDS100 • Flash programming tools • Power supply • Documentation and cables 7.1.3 Device and Development Support Tool Nomenclature To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320™ MCU devices and support tools. Each TMS320™ MCU commercial family member has one of three prefixes: TMX, TMP, or TMS (e.g., TMS320F280270). Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Device development evolutionary flow: TMX Experimental device that is not necessarily representative of the final device's electrical specifications TMP Final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification TMS Fully qualified production device Device and Documentation Support Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 109 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com Support tool development evolutionary flow: TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product TMX and TMP devices and TMDX development-support tools are shipped against the following disclaimer: "Developmental product is intended for internal evaluation purposes." TMS devices and TMDS development-support tools have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, PT) and temperature range (for example, S). Figure 7-1 provides a legend for reading the complete device name for any family member. TMS 320 F 280270 PT S PREFIX TMX = experimental device TMP = prototype device TMS = qualified device DEVICE FAMILY 320 = TMS320 MCU Family TECHNOLOGY F = Flash TEMPERATURE RANGE T = −40°C to 105°C S = −40°C to 125°C PACKAGE TYPE 48-Pin PT Low-Profile Quad Flatpack (LQFP) 38-Pin DA Thin Shrink Small-Outline Package (TSSOP) DEVICE 280270 280260 280230 280220 Figure 7-1. Device Nomenclature 110 Device and Documentation Support Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com 7.2 SPRS810 – APRIL 2012 Documentation Support Extensive documentation supports all of the TMS320™ MCU family generations of devices from product announcement through applications development. The types of documentation available include: data sheets and data manuals, with design specifications; and hardware and software applications. Table 7-1 shows the peripheral reference guides appropriate for use with the devices in this data manual. See the TMS320x28xx, 28xxx DSP Peripheral Reference Guide (literature number SPRU566) for more information on types of peripherals. Table 7-1. TMS320F2802x, TMS320F2802xx Peripheral Selection Guide PERIPHERAL LIT. NO. TYPE (1) 280270, 280260, 280230, 280220 TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide SPRUFN3 – X TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator SPRUGE5 3/0 (2) X TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) SPRUGH1 0 X TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) SPRUG71 1 X TMS320x2802x Piccolo Boot ROM SPRUFN6 – X TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module SPRUGE9 1 X TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module SPRUFZ8 0 X TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) SPRUFZ9 0 X (1) (2) A type change represents a major functional feature difference in a peripheral module. Within a peripheral type, there may be minor differences between devices that do not affect the basic functionality of the module. These device-specific differences are listed in the peripheral reference guides. The ADC module is Type 3 and the comparator module is Type 0. The following documents can be downloaded from the TI website (www.ti.com): Errata SPRZ292 TMS320F28027, TMS320F28026, TMS320F28023, TMS320F28022, TMS320F28021, TMS320F28020, TMS320F280200, TMS320F280270, TMS320F280260, TMS320F280230, TMS320F280220 Piccolo MCU Silicon Errata describes known advisories on silicon and provides workarounds. CPU User's Guides SPRU430 TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. Peripheral Guides SPRUFN3 TMS320x2802x/TMS320F2802xx Piccolo System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 2802x microcontrollers (MCUs). SPRU566 TMS320x28xx, 28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the 28x digital signal processors (DSPs). SPRUFN6 TMS320x2802x Piccolo Boot ROM Reference Guide describes the purpose and features of the boot loader (factory-programmed boot-loading software) and provides examples of code. It also describes other contents of the device on-chip boot ROM and identifies where all of the information is located within that memory. SPRUGE5 TMS320x2802x, 2803x Piccolo Analog-to-Digital Converter (ADC) and Comparator Reference Guide describes how to configure and use the on-chip ADC module, which is a 12-bit pipelined ADC. Device and Documentation Support Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 111 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 SPRS810 – APRIL 2012 www.ti.com SPRUGE9 TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motor control, switch mode power supply control, UPS (uninterruptible power supplies), and other forms of power conversion. SPRUGH1 TMS320x2802x, 2803x Piccolo Serial Communications Interface (SCI) Reference Guide describes how to use the SCI. SPRUFZ8 TMS320x2802x, 2803x Piccolo Enhanced Capture (eCAP) Module Reference Guide describes the enhanced capture module. It includes the module description and registers. SPRUG71 TMS320x2802x, 2803x Piccolo Serial Peripheral Interface (SPI) Reference Guide describes the SPI - a high-speed synchronous serial input/output (I/O) port - that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted into and out of the device at a programmed bit-transfer rate. SPRUFZ9 TMS320x2802x, 2803x Piccolo Inter-Integrated Circuit (I2C) Reference Guide describes the features and operation of the inter-integrated circuit (I2C) module. Tools Guides SPRU513 TMS320C28x Assembly Language Tools v5.0.0 User's Guide describes the assembly language tools (assembler and other tools used to develop assembly language code), assembler directives, macros, common object file format, and symbolic debugging directives for the TMS320C28x device. 7.3 SPRU514 TMS320C28x Optimizing C/C++ Compiler v5.0.0 User's Guide describes the TMS320C28x™ C/C++ compiler. This compiler accepts ANSI standard C/C++ source code and produces TMS320 DSP assembly language source code for the TMS320C28x device. SPRU608 TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000 IDE, that simulates the instruction set of the C28x™ core. Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 112 Device and Documentation Support Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 TMS320F280270, TMS320F280260 TMS320F280230, TMS320F280220 www.ti.com SPRS810 – APRIL 2012 8 Mechanical Packaging and Orderable Information 8.1 Thermal Data for Package Table 8-1 and Table 8-2 show the thermal data. See Section 2.9 for more information on thermal design considerations. Table 8-1. Thermal Model 38-Pin DA Results AIR FLOW PARAMETER 0 lfm 150 lfm 250 lfm 500 lfm θJA [°C/W] High k PCB 70.1 56.4 53.9 50.2 ΨJT [°C/W] 0.34 0.61 0.74 0.98 ΨJB 32.5 32.1 31.7 31.1 θJC 12.8 θJB 33 Table 8-2. Thermal Model 48-Pin PT Results AIR FLOW 8.2 PARAMETER 0 lfm 150 lfm 250 lfm θJA [°C/W] High k PCB 64 50.4 48.2 500 lfm 45 ΨJT [°C/W] 0.56 0.94 1.1 1.38 ΨJB 30.1 28.7 28.4 28 θJC 13.6 θJB 30.6 Packaging Information The following packaging information and addendum reflect the most current data available for the designated device(s). This data is subject to change without notice and without revision of this document. Mechanical Packaging and Orderable Information Submit Documentation Feedback Product Folder Link(s): TMS320F280270 TMS320F280260 TMS320F280230 TMS320F280220 Copyright © 2012, Texas Instruments Incorporated 113 PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2012 PACKAGING INFORMATION Orderable Device (1) Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TMS320F280220DAS ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280220DAT ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280220PTS ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280220PTT ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280230DAS ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280230DAT ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280230PTS ACTIVE LQFP PT 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280230PTT ACTIVE LQFP PT 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280260DAS ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280260DAT ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280260PTS ACTIVE LQFP PT 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280260PTT ACTIVE LQFP PT 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280270DAS ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280270DAT ACTIVE TSSOP DA 38 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280270PTS ACTIVE LQFP PT 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TMS320F280270PTT ACTIVE LQFP PT 48 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR The marketing status values are defined as follows: Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2012 ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 MECHANICAL DATA MTQF003A – OCTOBER 1994 – REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0°– 7° 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Falls within JEDEC MS-026 This may also be a thermally enhanced plastic package with leads conected to the die pads. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 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