CYPRESS CY8C20180

CY8C20180
CapSense Express™ -8 Configurable IOs
Features
Overview
■
The CapSense ExpressTM controller allows the control of 8 IOs
configurable as capacitive sensing buttons or as GPIOs for
driving LEDs or interrupt signals based on various button
conditions. The GPIOs are also configurable for waking up the
device from sleep based on an interrupt input.
8 configurable IOs supporting
❐ CapSense buttons
❐ LED Drive
❐ Interrupt outputs
❐ WAKE on interrupt input
❐ User defined input or output
■
2.4V to 5.25V operating voltage
■
Industrial temperature range: –40°C to +85°C
■
I2C slave interface for configuration
❐ Selectable to 50 kHz,100 kHz and 400 kHz
■
Reduce BOM cost
❐ Internal oscillator - no external oscillators or crystal
❐ Free development tool - no external tuning components
■
■
Low operating current
❐ Active current: continuous sensor scan:1.5 mA
❐ Sleep current: no scan, continuous sleep: 2.6 uA
Available in 16-pin COL and 16-pin SOIC packages
The user has the ability to configure buttons, outputs, and
parameters through specific commands sent to the I2C port. The
IOs have the flexibility in mapping to capacitive buttons and as
standard GPIO functions such as interrupt output or input, LED
drive and digital mapping of input to output using simple logical
operations. This enables easy PCB trace routing and reduces
the PCB size and stack up. CapSense Express products are
designed for easy integration into complex products.
Architecture
The logic block diagram illustrates the internal architecture of
CY8C20180.
The user can configure registers with parameters needed to
adjust the operation and sensitivity of the CapSense system.
CY8C20180 supports a standard I2C serial communications
interface that allows the host to configure the device and to read
sensor information in real time through easy register access.
The CapSense Express Core
The CapSense Express Core has a powerful configuration and
control block. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers. System
resources provide additional capability, such as a configurable
I2C slave communication interface and various system resets.
The Analog System is composed of the CapSense PSoC block
which supports capacitive sensing of up to eight inputs.
Cypress Semiconductor Corporation
Document Number: 001-17346 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised March 11, 2008
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CY8C20180
Logic Block Diagram
External
Vcc
2.4 - 5.25V
8 Configurable IOs
CapSense ExpressTM
Core
2KB Flash
512B
SRAM
Document Number: 001-17346 Rev. *C
Page 2 of 12
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CY8C20180
Pinouts
Figure 1. Pin Diagram - 16 Pin COL
Table 1. Pin Definitions - 16 Pin COL
Pin Number
Name
1
GP0[0]
Configurable as CapSense or GPIO
2
GP0[1]
Configurable as CapSense or GPIO
3
I2C SCL
I2C clock
4
I2C SDA
I2C data
5
GP1[0]
Configurable as CapSense or GPIO
6
GP1[1]
Configurable as CapSense or GPIO
7
VSS
8
GP1[2]
Configurable as CapSense or GPIO
9
GP1[3]
Configurable as CapSense or GPIO
10
GP1[4]
Configurable as CapSense or GPIO
11
XRES
Active HIGH external reset with internal pull down
12
GP0[2]
Configurable as CapSense or GPIO
13
VDD
14
GP0[3]
15
CSInt
16
GP0[4]
Document Number: 001-17346 Rev. *C
Description
Ground connection
Supply voltage
Configurable as CapSense or GPIO
Integrating Input.The external capacitance is required only if 5:1 SNR
cannot be achieved. Typical range is 10-100 nF.
Configurable as CapSense or GPIO
Page 3 of 12
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CY8C20180
Figure 2. Pin Diagram - 16 Pin SOIC
GP0[3]
1
16
VDD
CSInt
2
15
GP0[2]
GP0[4]
3
14
XRES
GP0[0]
4
13
GP1[4]
GP0[1]
5
12
GP1[3]
I2CSCL
6
11
GP1[2]
I2CSDA
7
10
VSS
GP1[0]
8
9
SOIC
(Top View)
GP1[1]
Table 2. Pin Definitions - 16 Pin SOIC
Pin Number
Name
1
GP0[3]
2
CSInt
3
GP0[4]
Configurable as CapSense or GPIO
4
GP0[0]
Configurable as CapSense or GPIO
5
GP0[1]
Configurable as CapSense or GPIO
6
I2C SCL
I2C clock
7
I2C SDA
I2C data
8
GP1[0]
Configurable as CapSense or GPIO
9
GP1[1]
Configurable as CapSense or GPIO
10
VSS
11
GP1[2]
Configurable as CapSense or GPIO
12
GP1[3]
Configurable as CapSense or GPIO
13
GP1[4]
Configurable as CapSense or GPIO
14
XRES
Active HIGH external reset with internal pull down.
15
GP0[2]
Configurable as CapSense or GPIO
16
VDD
Document Number: 001-17346 Rev. *C
Description
Configurable as CapSense or GPIO
Integrating Input.The external capacitance is required only if 5:1 SNR
cannot be achieved. Typical range is 10-100 nF.
Ground connection
Supply voltage
Page 4 of 12
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CY8C20180
The CapSense Analog System
I2C Interface
The CapSense analog system contains the capacitive sensing
hardware. which supports CapSense Successive Approximation
(CSA) algorithm.This hardware performs capacitive sensing and
scanning without external components. Capacitive sensing is
configurable on each pin.
The two modes of operation for the I2C interface are:
Additional System Resources
The I2C address is programmable during configuration. It can be
locked to prevent accidental change by setting a flag in a configuration register.
System resources provide additional capability useful to
complete systems. Additional resources are low voltage
detection and power on reset (POR).
The I C slave provides 50, 100, or 400 kHz communication
over two wires.
■
Low Voltage Detection (LVD) interrupts signal the application
of falling voltage levels and the advanced POR circuit eliminates the need for a system supervisor.
Device register configuration and status read or write for
controller.
■
Command execution.
CapSense Express Software Tool
2
■
■
An easy to use software tool integrated with PSoC Express is
available for configuring and tuning CapSense Express devices.
Refer to the Application Note AN42137 for details of the software
tool.
CapSense Express Register Map
An internal 1.8V reference provides a stable internal reference
so that capacitive sensing functionality is not affected by minor
VDD changes.
CapSense Express supports user configurable registers through
which the device functionality and parameters are configured.
For details, refer to CY8C201xx Register Reference document.
Electrical Specifications
Absolute Maximum Ratings
Min
Typ
Max
Unit
TSTG
Parameter
Storage temperature
Description
–55
25
+100
°C
TA
Ambient temperature with power
applied
–40
–
+85
ºC
VDD
Supply voltage on VDD relative to VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tri-state
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any GPIO pin
–25
–
+50
mA
ESD
Electro static discharge voltage
2000
–
–
V
LU
Latch up current
–
–
200
mA
Min
Typ
Max
Unit
Notes
Higher storage temperatures reduce
data retention time. Recommended
storage temperature is +25°C ± 25°C
(0°C to 50°C). Extended duration
storage temperatures above 65°C
degrade reliability.
Human body model ESD
Operating Temperature
Parameter
Description
TA
Ambient temperature
–40
–
+85
°C
TJ
Junction temperature
–40
–
+100
°C
Document Number: 001-17346 Rev. *C
Notes
Page 5 of 12
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CY8C20180
DC Electrical Characteristics
DC Chip-Level Specifications
Min
Typ
Max
Unit
VDD
Parameter
Supply voltage
Description
2.40
–
5.25
V
Notes
IDD
Supply current
–
1.5
2.5
mA
Conditions are VDD = 3.0V, TA = 25°C
ISB
Sleep mode current with POR and
LVD active. Mid temperature range
–
2.6
4
µA
VDD = 2.55V, 0°C < TA < 40°C
ISB
Sleep mode current with POR and
LVD active.
–
2.8
5
µA
VDD = 3.3V, –40°C < TA < 85°C
ISB
Sleep mode current with POR and
LVD active.
–
5.2
6.4
µA
VDD = 5.25V, –40°C < TA < 85°C
ri
5 and 3.3V DC General Purpose IO Specifications
This Table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C<
TA<85°C, 3.0V to 3.6V and -40°C<TA<85°C respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for design
guidance only.
Parameter
Description
Min
Typ
Max
Unit
Notes
RPU
Pull up resistor
4
5.6
8
kΩ
VOH1
High output voltage
Port 0 pins
VDD – 0.2
–
–
V
IOH = 10 µA, VDD > 3.0V, maximum of
20 mA source current in all IOs.
VOH2
High output voltage
Port 0 pins
VDD – 0.9
–
–
V
IOH = 1 mA, VDD > 3.0V, maximum of
20 mA source current in all IOs.
VOH3
High output voltage
Port 1 pins
VDD – 0.2
–
–
V
IOH < 10 µA, VDD> 3.0V, maximum of
10 mA source current in all IOs.
VOH
High output voltage
Port 1 pins
VDD – 0.9
–
–
V
IOH = 5 mA, VDD> 3.0V, maximum of
20 mA source current in all IOs.
VOH5
High output voltage.
Port 1 pins with 3.0V LDO regulator
enabled
2.75
3.0
3.2
V
IOH < 10 µA, VDD> 3.1V, maximum of
4 IOs all sourcing 5mA.
VOH6
High Output Voltage
2.2
–
–
V
IOH = 5 mA, VDD> 3.1V, maximum of
20 mA source current in all IOs.
2.1
2.4
2.5
V
IOH < 10 µA, VDD> 3.0V, maximum of
20 mA source current in all IOs.
2
–
–
V
IOH < 200 µA, VDD > 3.0V, maximum
of 20 mA source current in all IOs.
Port 1 pins with 3.0V LDO regulator
enabled
VOH7
High Output Voltage.
Port 1 pins with 2.4V LDO regulator
enabled
VOH8
High Output Voltage.
Port 1 pins with 2.4V LDO regulator
enabled
VOL
Low output voltage
–
–
0.75
V
IOL = 20 mA, VDD > 3V, maximum of 60
mA sink current on even port pins and
60 mA sink current on odd port pins
VIL
Input low voltage
–
–
0.75
V
VDD = 3 to 3.6V
VIH
Input high voltage
1.6
–
–
V
VDD = 3 to 3.6V
VIL
Input low voltage
–
–
0.8
V
VDD = 3.6 to 5.25V.
VIH
Input high voltage
2.0
–
–
V
VDD = 3.6 to 5.25V.
VH
Input hysteresis voltage
–
140
–
mV
Document Number: 001-17346 Rev. *C
Page 6 of 12
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CY8C20180
5 and 3.3V DC General Purpose IO Specifications (continued)
This Table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C<
TA<85°C, 3.0V to 3.6V and -40°C<TA<85°C respectively. Typical parameters apply to 5V and 3.3V at 25°C. These are for design
guidance only.
Parameter
Description
Min
Typ
Max
Unit
–
1
–
nA
Gross tested to 1 µA.
Capacitive load on pins as input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C
IL
Input leakage
CIN
COUT
Notes
2.7 V DC General Purpose IO Specifications
This Table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C<.
TA <85°C, respectively. Typical parameters apply to 2.7V at 25°C. These are for design guidance only.
Parameter
Description
Min
Typ
Max
Unit
Notes
RPU
Pull up resistor
4
5.6
8
kΩ
VOH1
High output voltage
Port 0 pins
VDD – 0.2
–
–
V
IOH < 10 µA, maximum of 10 mA
source current in all IOs.
VOH2
High output voltage
Port 0 pins
VDD – 0.5
–
–
V
IOH = 0.2 mA, maximum of 10 mA
source current in all IOs.
VOH3
High output voltage
Port 1 pins
VDD – 0.2
–
–
V
IOH < 10 µA, maximum of 10 mA
source current in all IOs.
VOH4
High output voltage
Port 1 pins
VDD – 0.5
–
–
V
IOH = 2 mA, maximum of 10 mA source
current in all IOs.
VOL
Low output voltage
–
–
0.75
V
IOL = 10 mA, maximum of 30 mA sink
current on even port pins and 30 mA
sink current on odd port pins
VOLP1
Low output voltage port 1 pins
–
–
0.4
V
IOL=5mA Maximum of 50mA sink
current on even port pins and 50mA
sink current on odd port pins
2.4<Vdd<3.6V
VIL
Input low voltage
–
–
0.75
V
VDD = 2.4 to 3.6V.
VIH1
Input high voltage
1.4
–
–
V
VDD = 2.4 to 2.7V.
VIH2
Input high voltage
1.6
V
VDD = 2.7 to 3.6V.
VH
Input hysteresis voltage
–
60
–
mV
IIL
Input leakage
–
1
–
nA
Gross tested to 1 µA.
CIN
Capacitive Load On Pins As Input
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
COUT
Capacitive load on pins as output
0.5
1.7
5
pF
Package and pin dependent.
Temp = 25°C.
Document Number: 001-17346 Rev. *C
Page 7 of 12
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CY8C20180
DC POR and LVD Specifications
Parameter
Description
Min
Typ
Max
Unit
VPPOR0
VPPOR1
VDD Value PPOR Trip
VDD= 2.7V
VDD= 3.3V,5V
–
–
2.36
2.60
2.40
2.65
V
V
VLVD0
VLVD2
VLVD6
VDD Value for LVD trip
VDD= 2.7V
VDD= 3.3V
VDD= 5V
2.39
2.75
3.98
2.45
2.92
4.05
2.51
2.99
4.12
V
V
V
Notes
VDD must be greater than or equal to
2.5V during startup, reset from the
XRES pin, or reset from Watchdog.
AC Electrical Characteristics
5.0V and 3.3V AC General Purpose IO Specifications
Parameter
Description
Min
Max
Unit
Notes
TRise0
Rise time, strong mode,
Cload = 50pF, Port 0
15
80
ns
VDD = 3.0V to 3.6V and 4.75V to 5.25V,
10% - 90%
TRise1
Rise time, strong mode,
Cload = 50pF, Port 1
10
50
ns
VDD = 3.0V to 3.6V, 10% - 90%
TFall
Fall time, strong mode,
Cload = 50pF, all ports
10
50
ns
VDD = 3.0V to 3.6V and 4.75V to 5.25V,
10% - 90%
2.7V AC General Purpose IO Specifications
Min
Max
Unit
TRise0
Parameter
Rise time, strong mode,
Cload = 50pF, Port 0
Description
15
100
ns
VDD = 2.4V to 3.0V, 10% - 90%
Notes
TRise1
Rise time, strong mode,
Cload = 50pF, Port 1
10
70
ns
VDD = 2.4V to 3.0V, 10% - 90%
TFall
Fall time, strong mode,
Cload = 50pF, all ports
10
70
ns
VDD = 2.4V to 3.0V, 10% - 90%
AC I2C Specifications
Parameter
Description
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
0
100
0
400
KHz
THDSTAI2C Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
µs
TLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
µs
THIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
µs
TSUSTAI2C
Setup time for a repeated START
condition
4.7
–
0.6
–
µs
THDDATI2C Data hold time
0
–
0
–
µs
TSUDATI2C Data setup time
250
–
100
–
ns
FSCLI2C
SCL clock frequency
TSUSTOI2C Setup time for STOP condition
4.0
–
0.6
–
µs
TBUFI2C
BUS free time between a STOP
and START condition
4.7
–
1.3
–
µs
TSPI2C
Pulse width of spikes suppressed
by the input filter
–
–
0
50
ns
Document Number: 001-17346 Rev. *C
Notes
Fast mode not supported for
VDD < 3.0V
Page 8 of 12
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CY8C20180
Figure 3. Definition for Timing for Fast/Standard Mode on the I2C Bus
Document Number: 001-17346 Rev. *C
Page 9 of 12
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CY8C20180
Ordering Information
Ordering Code
Package Diagram
Package Type
Operating
Temperature
CY8C20180-LDX2I
001-09116
16 COL[3]
Industrial
CY8C20180-SX2I
51-85068
16 SOIC
Industrial
Thermal Impedances by Package
Typical θJA[1]
Package
16 COL[3]
46 °C
16 SOIC
79.96 °C
Solder Reflow Peak Temperature
Minimum Peak Temperature[2]
Maximum Peak Temperature
COL[3]
240 °C
260 °C
16 SOIC
240 °C
260 °C
Package
16
.
Notes
1. TJ = TA + Power x θJA.
2. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste.
Refer to the solder manufacturer specifications.
3. Earlier termed as QFN package.
Document Number: 001-17346 Rev. *C
Page 10 of 12
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CY8C20180
Package Diagram
Figure 4. 16L Chip On Lead 3 X 3 mm Package Outline (SAWN) - 001-09116 - (Pb-Free)
DIMENSIONS IN mm MIN.
MAX.
2.9
3.1
0.20 min
0.45
0.55
1.5 (NOM)
1
2
2
2.9
3.1
1
0.152 REF.
0.20 DIA TYP.
0.05 MAX
0.60 MAX
PIN #1 ID
0.30
0.18
0.50
SEATING PLANE
TOP VIEW
PART NO.
LG16A
LD16A
SIDE VIEW
1.5
BOTTOM VIEW
JEDEC # MO-220
Package Weight: 0.014g
DESCRIPTION
LEAD-FREE
STANDARD
001-09116-*C
Figure 5. 16 - Pin (150-Mil) SOIC (51-85068)
51-85068-*B
Document Number: 001-17346 Rev. *C
Page 11 of 12
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CY8C20180
Document History Page
Document Title: CY8C20180 CapSense Express™ -8 Configurable IOs
Document Number: 001-17346
REV.
ECN.
Orig. of
Change
**
1341766
TUP/FSU
*A
1494145
TUP/AESA
Changed to FINAL Datasheet
Removed table - 2.7V DC General Purpose IO Specifications - Open Drain with a pull up to
1.8V
Updated Logic Block Diagram
*B
1773608
TUP/AESA
Removed table - 3V DC General Purpose IO Specifications
Updated Logic Block Diagram
Updated table - DC POR and LVD Specifications
Updated table - DC Chip Level Specifications
Updated table - 5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Updated table - AC GPIO Specifications and split it into two tables for 5V/3.3V and 2.7V
Added section on CapSense ExpressTM Software tool
Updated 16-QFN Package Diagram
*C
2091026
DZU/MOHD
/AESA
Updated table-DC Chip Level Specifications
Updated table-Pin Definitions 16 pin COL
Updated table-Pin Definitions 16 pin SOIC
Updated table-5V and 3.3V DC General Purpose IO Specifications
Updated table - 2.7V DC General Purpose IO Specifications
Changed definition for Timing for Fast/Standard Mode on the I2C Bus diagram
Description of Change
New Data Sheet
© Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
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critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
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and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
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the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-17346 Rev. *C
Revised March 11, 2008
Page 12 of 12
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names
mentioned in this document may be the trademarks of their respective holders.
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