CY7C1024DV33 PRELIMINARY 3-Mbit (128K X 24) Static RAM Features Functional Description • High speed The CY7C1024DV33 is a high-performance CMOS static RAM organized as 128K words by 24 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. — tAA = 8 ns • Low active power — ICC = 185 mA @ 8 ns To write to the device, enable the chip (CE1 LOW, CE2 HIGH and CE3 LOW) while forcing the Write Enable (WE) input LOW. • Low CMOS standby power — ISB2 = 25 mA To read from the device, enable the chip by taking CE1 LOW CE2 HIGH and CE3 LOW while forcing the Output Enable (OE) LOW and the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs The 24 I/O pins (I/O0–I/O23) are placed in a high-impedance state when all the chip selects are HIGH or when the output enable (OE) is HIGH during a READ mode. For further details, refer to the truth table of this data sheet. • Easy memory expansion with CE1, CE2 and CE3 features • Available in Pb-Free Standard 119-ball PBGA Functional Block Diagram 128K x 24 ARRAY I/O0–I/O23 CONTROL LOGIC CE1, CE2, CE3 WE OE A10 A11 A 12 A 13 A 14 A15 A16 COLUMN DECODER SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER Selection Guide Maximum Access Time –8 Unit 8 ns Maximum Operating Current 185 mA Maximum CMOS Standby Current 25 mA Cypress Semiconductor Corporation Document #: 001-08353 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 4, 2006 [+] Feedback CY7C1024DV33 PRELIMINARY Pin Configurations[1] 119 PBGA Top View 1 2 3 4 5 6 7 A NC A A A A A NC B NC A A CE1 A A NC C I/O12 NC CE2 NC CE3 NC I/O0 D I/O13 VDD VSS VSS VSS VDD I/O1 E I/O14 VSS VDD VSS VDD VSS I/O2 F I/O15 VDD VSS VSS VSS VDD I/O3 G I/O16 VSS VDD VSS VDD VSS I/O4 H I/O17 VDD VSS VSS VSS VDD I/O5 J NC VSS VDD VSS VDD VSS NC K I/O18 VDD VSS VSS VSS VDD I/O6 L I/O19 VSS VDD VSS VDD VSS I/O7 M I/O20 VDD VSS VSS VSS VDD I/O8 N I/O21 VSS VDD VSS VDD VSS I/O9 P I/O22 VDD VSS VSS VSS VDD I/O10 R I/O23 NC NC NC NC NC I/O11 T NC A A WE A A NC U NC A A OE A A NC Note: 1. NC pins are not connected on the die Document #: 001-08353 Rev. *A Page 2 of 8 [+] Feedback CY7C1024DV33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC Relative to GND[2] .... –0.5V to +4.6V DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V Range Ambient Temperature VCC Commercial 0°C to +70°C 3.3V ± 0.3V DC Input Voltage[2] .................................–0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range –8 Parameter Description Test Conditions[7] VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VCC = Min., IOL = 8.0 mA Min. Max. Unit 2.4 V VOL Output LOW Voltage 0.4 V VIH Input HIGH Voltage 2.0 VCC + 0.3 V VIL[2] Input LOW Voltage –0.3 0.8 V IIX Input Leakage Current GND < VI < VCC –1 +1 µA –1 IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled +1 µA ICC VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC IOUT = 0 mA CMOS levels 185 mA ISB1 Automatic CE Power-down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 30 mA ISB2 Automatic CE Power-down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 25 mA Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions Max. Unit TA = 25°C, f = 1 MHz, VCC = 3.3V 8 pF 10 pF Thermal Resistance[3] Parameter ΘJA ΘJC Description Test Conditions PBGA Unit TBD °C/W TBD °C/W Thermal Resistance (Junction to Ambient) Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board Thermal Resistance (Junction to Case) AC Test Loads and Waveforms[4] 50Ω OUTPUT 30 pF* * Capacitive Load consists of all components of the test environment. Z0 = 50Ω (a) 3.0V GND R2 351Ω 5 pF ALL INPUT PULSES 90% Rise time > 1 V/ns R1 317Ω 3.3V VTH = 1.5V OUTPUT 90% INCLUDING JIG AND SCOPE (b) 10% 10% (c) Fall time: > 1 V/ns Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100 µs (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 001-08353 Rev. *A Page 3 of 8 [+] Feedback CY7C1024DV33 PRELIMINARY AC Switching Characteristics Over the Operating Range [5] –8 Parameter Description Min. Max. Unit Read Cycle tpower[6] VCC(typical) to the first access tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE tDOE tLZOE 8 ns ns CE active LOW to Data Valid[7] 8 ns OE LOW to Data Valid 5 ns OE LOW to Low-Z [8] 3 OE HIGH to High-Z CE active LOW to Low-Z[7, 8] tHZCE CE deselect HIGH to High-Z[7, 8] CE active LOW to ns 5 Power-up[7, 9] CE deselect HIGH to ns 1 [8] tHZOE tPD µs 8 tLZCE tPU 100 3 5 0 Power-down[7, 9] ns ns ns ns 8 ns Write Cycle[10, 11] tWC Write Cycle Time tSCE CE active LOW to Write End[7] 8 ns 6 ns tAW Address Set-up to Write End 6 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 6 ns tSD Data Set-up to Write End 5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE WE HIGH to Low-Z[8] WE LOW to High-Z[8] 5 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the read cycle use output loading as shown in part a) of the AC test loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access is performed. 7. CE refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 is LOW and CE2 is HIGH and CE3 is LOW. CE is deselect HIGH when CE1 is HIGH or CE2 is LOW or CE3 is HIGH 8. tHZOE, tHZCE, tHZWE, and tLZOE, tLZCE, tLZWE, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 9. These parameters are guaranteed by design and are not tested. 10. The internal write time of the memory is defined by the overlap of CE1 and CE2 and CE3 LOW and WE LOW. The chip enables must be active and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. 11. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 001-08353 Rev. *A Page 4 of 8 [+] Feedback CY7C1024DV33 PRELIMINARY Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[12] Operation Recovery Time Min. Typ. Max. 2 Unit V 25 VCC = 2V , CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3V VCC 3V VDR > 2V tR tCDR CE Switching Waveforms Read Cycle No. 1[13, 15] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled)[14, 15, 16] ADDRESS tRC CE tACE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE tHZCE DATA VALID tLZCE VCC SUPPLY CURRENT HIGH IMPEDANCE tPD tPU 50% ICC 50% ISB Notes: 12. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 13. Device is continuously selected. OE, CE = VIL. 14. CE refers to a combination of CE1, CE2, and CE3. CE is active LOW when CE1 LOW and CE2 HIGH and CE3 LOW. 15. WE is HIGH for read cycle. 16. Address valid prior to or coincident with CE transition LOW. Document #: 001-08353 Rev. *A Page 5 of 8 [+] Feedback CY7C1024DV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)[14, 17, 18] tWC ADDRESS tSCE CE tSA tSCE tAW tHA tPWE WE tSD DATA I/O tHD DATA VALID Write Cycle No. 2 (WE Controlled, OE HIGH During Write)[14, 17, 18] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE OE tSD DATA I/O tHD DATAIN VALID NOTE 19 tHZOE Write Cycle No. 3 (WE Controlled, OE LOW)[14, 18] tWC ADDRESS tSCE CE tAW tSA tHA tPWE WE tSD DATA I/O NOTE 19 tHD DATA VALID tHZWE tLZWE Notes: 17. Data I/O is high impedance if OE = VIH. 18. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state. 19. During this period the I/Os are in the output state and input signals should not be applied. Document #: 001-08353 Rev. *A Page 6 of 8 [+] Feedback CY7C1024DV33 PRELIMINARY Truth Table CE1 CE2 CE3 OE WE I/O0–I/O23 Mode Power H X X X X High-Z Power-down Standby (ISB) X L X X X High-Z Power-down Standby (ISB) X X H X X High-Z Power-down Standby (ISB) L H L L H Full Data Out Read Active (ICC) L H L X L Full Data In Write Active (ICC) L H L H H High-Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) Ordering Code Package Name 8 CY7C1024DV33-8BGXC 51-85115 Operating Range Package Type 119-ball Plastic Ball Grid Array (14 x 22 x 2.4 mm) (Pb-free) Commercial Package Diagram 119-ball PBGA (14 x 22 x 2.4 mm) (51-85115) 51-85115-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-08353 Rev. *A Page 7 of 8 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback PRELIMINARY CY7C1024DV33 Document History Page Document Title: CY7C1024DV33 3-Mbit (128K X 24) Static RAM Document Number: 001-08353 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 469517 See ECN NXR New Data Sheet *A 499604 See ECN NXR Added note# 1 for NC pins Changed ICC spec from 150 mA to 185 mA Updated Test Condition for ICC in DC Electrical Characteristics table Added note for tACE, tLZCE, tHZCE, tPU, tPD, tSCE in AC Switching Characteristics Table on page# 4 Document #: 001-08353 Rev. *A Page 8 of 8 [+] Feedback