CY7C1069DV33 PRELIMINARY 16-Mbit (2M x 8) Static RAM Features Functional Description • High speed The CY7C1069DV33 is a high-performance CMOS Static RAM organized as 2,097,152 words by 8 bits. Writing to the device is accomplished by enabling the chip (by taking CE1 LOW and CE2 HIGH) and Write Enable (WE) inputs LOW. — tAA = 10 ns • Low active power — ICC = 125 mA @ 10 ns Reading from the device is accomplished by enabling the chip (CE1 LOW and CE2 HIGH) as well as forcing the Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. See the truth table at the back of this data sheet for a complete description of Read and Write modes. • Low CMOS standby power — ISB2 = 25 mA • Operating voltages of 3.3 ± 0.3V • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE1 and CE2 features • Available in Pb-free 54-pin TSOP II package and 48-ball VFBGA packages The input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a Write operation (CE1 LOW, CE2 HIGH, and WE LOW). The CY7C1069DV33 is available in a 54-pin TSOP II package with center power and ground (revolutionary) pinout, and a 48-ball very fine-pitch ball grid array (VFBGA) package. Logic Block Diagram Pin Configuration TSOP II Top View 2M x 8 ARRAY SENSE AMPS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER INPUT BUFFER I/O0–I/O7 WE CE2 OE COLUMN DECODER A 10 A11 A 12 A 13 A 14 A 15 A 16 A 17 A18 A19 A20 CE1 NC VCC NC I/O6 VSS I/O7 A4 A3 A2 A1 A0 NC CE1 VCC WE CE2 A19 A18 A17 A16 A15 I/O0 VCC I/O1 NC VSS NC 1 2 3 54 53 4 52 51 5 6 50 49 7 8 9 10 11 12 48 47 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 NC VSS NC I/O5 VCC I/O4 A5 A6 A7 A8 A9 NC OE VSS NC A20 A10 A11 A12 A13 A14 I/O3 VSS I/O2 NC VCC NC Selection Guide –10 Unit Maximum Access Time 10 ns Maximum Operating Current 125 mA Maximum CMOS Standby Current 25 mA Cypress Semiconductor Corporation Document #: 38-05478 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 14, 2006 [+] Feedback CY7C1069DV33 PRELIMINARY Pin Configurations[1] 48-ball VFBGA (Top View) 4 3 5 6 OE A0 A1 A2 CE2 A NC NC A3 A4 CE1 NC B I/O0 NC A5 A6 NC I/O4 C VSS I/O1 A17 A7 I/O5 V CC D 1 2 NC VCC I/O2 A18 A16 I/O6 VSS E I/O3 NC A14 A15 NC I/O7 F NC NC A12 A13 WE NC G A8 A9 A10 A11 A19 A20 H Note: 1. NC pins are not connected on the die Document #: 38-05478 Rev. *C Page 2 of 9 [+] Feedback CY7C1069DV33 PRELIMINARY Maximum Ratings Current into Outputs (LOW)......................................... 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage............. ...............................>2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. –65°C to +150°C Latch-up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................. –55°C to +125°C Operating Range Supply Voltage on VCC to Relative GND[2] .... –0.5V to +4.6V Ambient Temperature VCC –40°C to +85°C 3.3V ± 0.3V Range DC Voltage Applied to Outputs in High-Z State[2] ....................................–0.5V to VCC + 0.5V Industrial DC Input Voltage[2] .................................–0.5V to VCC + 0.5V DC Electrical Characteristics Over the Operating Range –10 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. Max. Unit 2.4 Voltage[2] V 0.4 V 2.0 VCC + 0.3 V –0.3 0.8 V +1 µA VIL Input LOW IIX Input Leakage Current GND < VI < VCC –1 IOZ Output Leakage Current GND < VOUT < VCC, Output Disabled –1 +1 µA ICC 125 mA ISB1 VCC Operating Supply Current VCC = Max., f = fMAX = 1/tRC, IOUT = 0 mA CMOS levels Automatic CE Power-down CE2 < VIL, Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX Current —TTL Inputs 30 mA ISB2 Automatic CE Power-down Current —CMOS Inputs 25 mA CE2 < 0.3V, Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f = 0 Capacitance[3] Parameter Description CIN Input Capacitance COUT I/O Capacitance Test Conditions TSOP II TA = 25°C, f = 1 MHz, VCC = 3.3V VFBGA Unit 6 8 pF 8 10 pF Thermal Resistance[3] Parameter Description ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Test Conditions All-Packages Unit Still Air, soldered on a 3 × 4.5 inch, four-layer printed circuit board TBD °C/W TBD °C/W AC Test Loads and Waveforms[4] 50Ω VTH = 1.5V OUTPUT Z0 = 50Ω R1 317 Ω 3.3V 30 pF* *Capacitive Load consists of all OUTPUT R2 351Ω 5 pF* components of the test environment (a) All input pulses 3.0V GND 90% 10% 90% 10% Rise time > 1V/ns (c) (b) *Including jig and scope Fall time: > 1V/ns Notes: 2. VIL (min.) = –2.0V and VIH(max) = VCC + 2V for pulse durations of less than 20 ns. 3. Tested initially and after any design or process changes that may affect these parameters. 4. Valid SRAM operation does not occur until the power supplies have reached the minimum operating VDD (3.0V). 100µs (tpower) after reaching the minimum operating VDD, normal SRAM operation can begin including reduction in VDD to the data retention (VCCDR, 2.0V) voltage. Document #: 38-05478 Rev. *C Page 3 of 9 [+] Feedback CY7C1069DV33 PRELIMINARY AC Switching Characteristics Over the Operating Range [5] –10 Parameter Description Min. Max. Unit Read Cycle tpower VCC(typical) to the First Access[6] 100 µs tRC Read Cycle Time 10 ns tAA Address to Data Valid tOHA Data Hold from Address Change tACE tDOE tLZOE 10 ns CE1 LOW/CE2 HIGH to Data Valid 10 ns OE LOW to Data Valid 5 ns [7] OE LOW to Low-Z OE HIGH to High-Z tLZCE CE1 LOW/CE2 HIGH to Low-Z[7] tHZCE CE1 HIGH/CE2 LOW to High-Z[7] tPD ns 1 [7] tHZOE tPU 3 ns 5 CE1 LOW/CE2 HIGH to Power-up[8] CE1 HIGH/CE2 LOW to Power-down[8] 3 ns ns 5 0 ns ns 10 ns Write Cycle[9, 10] tWC Write Cycle Time 10 ns tSCE CE1 LOW/CE2 HIGH to Write End 7 ns tAW Address Set-up to Write End 7 ns tHA Address Hold from Write End 0 ns tSA Address Set-up to Write Start 0 ns tPWE WE Pulse Width 7 ns tSD Data Set-up to Write End 5.5 ns tHD Data Hold from Write End 0 ns 3 ns tLZWE tHZWE WE HIGH to Low-Z[7] WE LOW to High-Z[7] 5 ns Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V. Test conditions for the Read cycle use output loading shown in part a) of the AC test loads, unless specified otherwise. 6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed. 7. tHZOE, tHZSCE, tHZWE and tLZOE, tLZCE, and tLZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage. 8. These parameters are guaranteed by design and are not tested. 9. The internal Write time of the memory is defined by the overlap of CE1 LOW/CE2 HIGH, and WE LOW. CE1 and WE must be LOW along with CE2 HIGH to initiate a Write, and the transition of any of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write. 10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD. Document #: 38-05478 Rev. *C Page 4 of 9 [+] Feedback CY7C1069DV33 PRELIMINARY Data Retention Characteristics (Over the Operating Range) Parameter Description Conditions VDR VCC for Data Retention ICCDR Data Retention Current tCDR[3] Chip Deselect to Data Retention Time tR[11] Operation Recovery Time Min. Typ. Max. 2 Unit V 25 VCC = 2V , CE1 > VCC – 0.2V, CE2 < 0.2V, VIN > VCC – 0.2V or VIN < 0.2V mA 0 ns tRC ns Data Retention Waveform DATA RETENTION MODE 3V VCC VDR > 2V 3V tR tCDR CE Switching Waveforms Read Cycle No. 1[12,13] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2(OE Controlled)[13,14] ADDRESS tRC CE1 CE2 tASCE OE tHZOE tDOE tHZSCE tLZOE DATA OUT HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZSCE VCC SUPPLY CURRENT tPD tPU 50% ICC 50% ISB Notes: 11. Full device operation requires linear VCC ramp from VDR to VCC(min.) > 50 µs or stable at VCC(min.) > 50 µs 12. Device is continuously selected. CE1 = VIL, CE2 = VIH. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. Document #: 38-05478 Rev. *C Page 5 of 9 [+] Feedback CY7C1069DV33 PRELIMINARY Switching Waveforms (continued) Write Cycle No. 1(CE1 Controlled)[15,16,17] tWC ADDRESS tSA CE tSCE tAW tHA tPWE WE tBW tSD tHD DATAI/O Write Cycle No.2(WE Controlled, OE LOW)[15,16,17] OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tHZWE tSD tHD DATA I/O tLZWE Truth Table CE1 CE2 OE WE H X X X High-Z I/O0–I/O7 Power-down Mode Standby (ISB) Power X L X X High-Z Power-down Standby (ISB) L H L H Data Out Read All Bits Active (ICC) L H X L Data In Write All Bits Active (ICC) L H H H High-Z Selected, Outputs Disabled Active (ICC) Notes: 15. Data I/O is high-impedance if OE = VIH. 16. If CE1 goes HIGH/CE2 LOW simultaneously with WE going HIGH, the output remains in a high–impedance state. 17. CE above is defined as a combination of CE1 and CE2. It is active low. Document #: 38-05478 Rev. *C Page 6 of 9 [+] Feedback PRELIMINARY CY7C1069DV33 Ordering Information Speed (ns) 10 Ordering Code CY7C1069DV33-10ZXI Package Diagram Package Type 51-85160 54-pin TSOP II (Pb-Free) Operating Range Industrial CY7C1069DV33-10BVXI 51-85178 48-ball Very Fine Pitch Ball Grid Array (8 × 9.5 × 1 mm) (Pb-Free) Package Diagrams 54-pin TSOP Type II (51-85160) 51-85160-** Document #: 38-05478 Rev. *C Page 7 of 9 [+] Feedback CY7C1069DV33 PRELIMINARY Package Diagrams 48-ball FBGA (8 x 9.5 x 1 mm) (51-85178) BOTTOM VIEW TOP VIEW A1 CORNER C Ø0.05 M Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 3 4 5 6 6 5 4 3 2 1 A B C B F G D E 2.625 E C 0.75 D 5.25 A 9.50±0.10 9.50±0.10 1 2 F G H H A 1.875 A B 8.00±0.10 0.75 B 0.10 C 0.21±0.05 0.25 C 0.55 MAX. 3.75 0.15(4X) 51-85178. ** SEATING PLANE C Document #: 38-05478 Rev. *C 1.00 MAX 0.26 MAX. 8.00±0.10 Page 8 of 9 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1069DV33 PRELIMINARY Document History Page Document Title: CY7C1069DV33 16-Mbit (2M x 8) Static RAM Document Number: 38-05478 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 201560 See ECN SWI Advance Data sheet for C9 IPP *A 233748 See ECN RKF 1.AC, DC parameters are modified as per EROS (Spec # 01-2165) 2.Pb-free Offering in the ‘Ordering Information *B 469420 See ECN NXR Converted from Advance Information to Preliminary Removed –8 and –12 speed bins from product offering Removed Commercial Operating Range Changed 2G ball of FBGA and pin #40 of TSOPII from DNU to NC Included the Maximum ratings for Static Discharge Voltage and Latch Up Current on page #3 Changed ICC(Max) from 220 mA to 100 mA Changed ISB1(Max) from 70 mA to 30 mA Changed ISB2(Max) from 40 mA to 25 mA Specified the Overshoot spec in footnote # 1 Added Data Retention Characteristics table on page #5 Updated the 48-pin FBGA package Updated the ordering Information table. *C 499604 See ECN NXR Added note# 1 for NC pins Updated Test Condition for ICC in DC Electrical Characteristics table Updated the 48-ball FBGA Package Document #: 38-05478 Rev. *C Page 9 of 9 [+] Feedback