TI AFE8405

AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212 – OCTOBER 2008
1 Introduction
1.1 FEATURES
•
•
•
•
•
•
•
•
14-Bit 85-MSPS High-Performance Single ADC
At fin = 140 MHz, SNR ≥ 71 dBFS,
SFDR ≥ 79 dBc
At fin = 70 MHz, SNR ≥ 73 dBFS,
SFDR ≥ 85 dBc
Independent Clocks for ADC and DDC With
Built-In FIFO
Programmable Closed-Loop VGA Control With
6-Bit Outputs for ADC
Received Total Wideband Power (RTWP)
Measurement for the Composite Power Across
Carriers With Programmable Time Window for
Measurement
8 UMTS Digital Downconverter (DDC)
Channels or 16 CDMA/TD-SCDMA DDC
Channels With Programmable 18-Bit Filter
Coefficients
Each DDC Channel Provides:
– Real or Complex DDC Inputs
– UMTS Mode Rx Filtering: 6-Stage CIC (m =
1 or 2), up to 40-Tap CFIR, up to 64-Tap
PFIR
– CDMA Mode Rx Filtering: 6-Stage CIC (m =
1 or 2), up to 64-Tap CFIR, up to 64-Tap
PFIR
•
•
•
•
– Individual Channel-Specific Power
Measurements
– A Dedicated Final AGC
Test Bus to Monitor Data at Different Stages of
the DDC Signal Path
3.3-V Analog Supplies, 1.5-V Digital Core
Supply, 3.3-V Digital I/O Supply
484-Ball Plastic BGA (23 mm × 23 mm) With
1,0-mm Pitch
Power Dissipation (Eight Active DDC
Channels): 2.3 W
1.2 APPLICATIONS
•
•
•
•
•
•
•
•
•
•
Wireless Base Station Receiver
Multi-Carrier Digital Receiver
UMTS (8 Carriers-1 Sector)
CDMA (16 Carriers-1 Sector)
TD-SCDMA (16 Carriers-1 Sector)
Digital Radio Receivers
Wideband Receivers
Software Radios
Wireless Local Loop
Intelligent Antenna Systems
Contents
1
2
3
4
Introduction ............................................... 1
4.5
Factory Test and No-Connect Signals .............. 15
1.1
FEATURES ........................................... 1
4.6
Power and Ground Signals.......................... 15
1.2
APPLICATIONS ...................................... 1
4.7
Digital Supply Monitoring ............................ 16
General Description ..................................... 3
SPECIFICATIONS ........................................ 4
4.8
JTAG ................................................ 16
5
6
Typical Characteristics ................................ 17
ANALOG-TO-DIGITAL CONVERTERS .............. 24
3.1
PACKAGE ORDERING INFORMATION ............. 4
3.2
ABSOLUTE MAXIMUM RATINGS ................... 4
6.1
ADC Operation ...................................... 24
3.3
RECOMMENDED OPERATING CONDITIONS ...... 4
6.2
ADC Input Configuration
3.4
THERMAL CHARACTERISTICS ..................... 5
6.3
ADC Input Voltage Overstress ...................... 28
3.5
POWER DISSIPATION ............................... 5
6.4
ADC Reference Circuit .............................. 28
3.6
ANALOG ELECTRICAL CHARACTERISTICS ....... 6
6.5
ADC Clock Input..................................... 28
............ 8
... 9
AFE8405 PINS ........................................... 10
4.1
Analog Section Signals .............................. 10
4.2
Digital Receive Section Signals ..................... 11
4.3
Microprocessor Signals ............................. 14
4.4
JTAG Signals ........................................ 15
3.7
DIGITAL CHIP DC CHARACTERISTICS
3.8
DIGITAL CHIP AC TIMING CHARACTERISTICS
7
8
............................
24
RECEIVE DIGITAL SIGNAL PROCESSING ........ 30
7.1
Receive Input Interface .............................. 30
7.2
DDC Organization ................................... 43
AFE8405 GENERAL CONTROL ...................... 73
8.1
Microprocessor Interface Control Data, Address,
and Strobes ......................................... 73
8.2
Synchronization Signals ............................. 76
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this document.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
8.3
2
Interrupt Handling ................................... 77
Contents
www.ti.com
8.4
AFE8405 Programming
.............................
77
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212 – OCTOBER 2008
2 General Description
The AFE8405 is a multichannel communications signal processor that provides analog-to-digital
conversion and digital downconversion optimized for cellular base transceiver systems. The device
supports UMTS, CDMA-1X, and TD-SCDMA air-interface cellular standards.
The AFE8405 provides up to 8 UMTS digital downconverter channels (DDC), 16 CDMA DDCs or 16
TD-SCDMA DDCs. The DDC channels are independent and operate simultaneously.
The AFE8405 DDCs have three input ports; one is hardwired to the internal 14-bit analog-to-digital
converter (rxin_a) and two are 16-bit digital inputs (rxin_c, rxin_d). Each DDC channel can be
programmed to accept data from any one of the three input ports; rxin_b is not used.
dvga_b dvga_d
refpa
refma
Dual 14-Bit 85-MSPS ADC
Internal
Reference
dvga_a dvga_c
6
inpa
S&H
inma
14-Bit
Pipelined
ADC Core
Digital
Error
Correction
Output
Control
da(13:0)
6
6
6
rxin_a
Q
sync
I
clkouta
clkpa
Timing Circuitry
clkma
I
DDC0
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
adcclk_a
DDC1
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
adcclk_b
Q
sync
I
DDC2
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
Q
sync
rxin_b
I
Receive Input
Interface
trst_n
tck
tdi
tms
16
tdo
JTAG
rx_synca–rx_syncd
reset_n
Digital Receive
Data Ports
Power
Measurements
and Wideband
AGC
rxin_c
adcclk_c
16
rxin_d
adcclk_d
interrrupt
rx_sysnc_out
Control and Sync
DDC3
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
rd_n
Q
32
Output
Format
Parallel
or
Serial
rxout_X_X
8
rx_sync_out_X
rxclk_out
sync
I
DDC5
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
Q
sync
I
DDC6
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
6
d(15:0)
sync
I
DDC4
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
rxclk
16
Q
Q
sync
ce_n
I
a(5:0)
wr_n
DDC7
2 CDMA2000-1X,
2 TD-SCMA or 1 UMTS
Q
sync
B0104-02
Figure 2-1. Functional Block Diagram
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General Description
3
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
www.ti.com
3 SPECIFICATIONS
3.1 PACKAGE ORDERING INFORMATION
PRODUCT
PACKAGE–LEADS
PACKAGE
DESIGNATOR
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER
TRANSPORT
MEDIA,
QUANTITY
AFE8405
Plastic BGA–484
ZDQ
–40°C to 85°C
AFE8405I
AFE8405IZDQ
Tray, 60
3.2 ABSOLUTE MAXIMUM RATINGS (1)
UNIT
Analog Chip
AVDD
Analog supply voltage
–0.3 V to 3.7 V
DRVDD
I/O ring supply voltage
–0.3 V to 3.7 V
Ground difference DRVSS to AVSS
–0.1 V to 0.1 V
Analog input voltage
–0.15 V to 3.6 V
Digital input voltage
–0.3 V to DRVDD + 0.3 V
Digital Chip
VDDS
Pad ring supply voltage
–0.3 V to 3.7 V
DVDD
Core supply voltage
–0.3 V to 1.8 V
Digital input voltage
–0.3 V to VDDS + 0.3 V
Entire Chip
Clamp current for an input or output
–20 mA to 20 mA
TSTG
Storage temperature
–65°Cto 140°C
TJ
Junction temperature
105°C
Lead soldering temperature (10 seconds)
300°C
ESD classification (tested to EIA/JESD22-A114-B)
Class 2
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3.3
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Analog Chip
AVDD
Analog supply voltage
3
3.3
3.6
V
DRVDD
I/O ring supply voltage
3
3.3
3.6
V
VID
Differential input voltage range
VCM
Common-mode input voltage
2.3
1.5
Differential clock inputs
V
1.6
3
Clock input duty cycle
V
VPP
50%
Digital Chip
VDDS
I/O ring supply voltage
DVDD
Core supply voltage
3
3.6
V
1.425
1.575
V
2
V
85
°C
105
°C
Supply voltage difference, VDDS – DVDD
Entire Chip
TA
TJ
(1)
4
Temperature ambient, no air flow
(1)
Junction temperature
–40
Thermal management is required for full-rate operation. The circuit is designed for junction temperatures up to 125°C. Sustained
operation at elevated temperatures reduces long-term reliability. Lifetime calculations based on maximum junction temperature of
105°C.
SPECIFICATIONS
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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3.4
SLWS212 – OCTOBER 2008
THERMAL CHARACTERISTICS
THERMAL CONDUCTIVITY (1)
RθJA
RθJC
(1)
MIN
TYP MAX
UNIT
Theta junction-to-ambient (0 LFPM)
14
°C/W
Theta junction-to-ambient (100 LFPM)
13
°C/W
Theta junction-to-ambient (250 LFPM)
12.2
°C/W
Theta junction-to-ambient (500 LFPM)
11.6
°C/W
2.8
°C/W
Theta junction-to-case
Air flow reduces RθJA and is highly recommended.
3.5
POWER DISSIPATION
Typical values at TA = 25°C, UMTS mode, sampling rate = 61.44 MSPS, and rxclk = 122.88 MHz (unless otherwise noted)
PARAMETER
IAVDD
Analog supply current
TEST CONDITIONS
Six active DDC channels
MIN
TYP
MAX
UNIT
123
mA
IDRVDD Analog I/O supply current
21.5
mA
IDVDD
Digital core supply current
959
mA
IVDDS
Digital I/O supply current
(1)
100
mA
477
mW
(2)
1.439
W
1.9
W
Analog power dissipation
Digital power dissipation
Total power dissipation
IAVDD
(2)
Analog supply current
Eight active DDC channels
IDRVDD Analog I/O supply current
IDVDD
IVDDS
Digital core supply current
Digital I/O supply current
(1)
Analog power dissipation
Digital power dissipation
Total power dissipation
(1)
(2)
(2)
(2)
123
mA
21.5
mA
1.198
A
115
mA
477
mW
1.797
W
2.3
W
Current consumption on the digital I/O supply is primarily due to the external loads and follows C × V × F. Internal loads are estimated at
2 pF per terminal. Data outputs transition once every four clocks, whereas clock outputs transition every cycle. In general,
IVDDS = Σ (DataPad/4) × C × V × F + Σ ClockPad × C × V × F.
Excluding current consumption from the digital I/O supply, which is dependent on external loads
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SPECIFICATIONS
5
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
3.6
www.ti.com
ANALOG ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, minimum and maximum values over temperature range of TA = –40°C to 85°C, sampling rate =
80 MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3 V, –1-dBFS differential input, internal reference, and 3-VPP
differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP MAX
UNIT
14
Bits
VPP
Analog Inputs
VID
Differential input voltage range
2.3
CID
Differential input capacitance
3.2
pF
IIC
Common-mode input current
2 mA per input, 4 mA total
4
mA
Analog input bandwidth
Source impedance = 50 Ω
750
MHz
Conversion Characteristics
fADC
ADC clock rate (fclkpa = fclkma = fADC)
frxclk = 1 × fADC ch_rate_sel = rate_sel =
00
85
frxclk = 2 × fADC ch_rate_sel = rate_sel =
01
80
frxclk = 4 × fADC ch_rate_sel = rate_sel =
10
40
frxclk = 8 × fADC ch_rate_sel = rate_sel =
11
20
Data latency – ADC input to FIFO input
16.5
MSPS
Clock
Cycles
Internal Reference Voltages
refma
Lower reference voltages
1
refpa
Upper reference voltages
2.15
V
Reference error
±3.5
% of FS
1.55
±0.05
V
cma
Common-mode output voltages
V
Dynamic DC Characteristics and Accuracy
No missing codes
tested
DNL
Differential linearity error
fin = 1 MHz
±0.65
LSBs
INL
Integral linearity error
fin = 1 MHz
±4
LSBs
Offset error
Offset temperature coefficient
±4
mV
7
µV/°C
±0.5
Gain error
Gain temperature coefficient
0.0015
% of FS
Δ%/°C
Dynamic AC Characteristics
fin = 10 MHz, TA = 25°C
SNR
Signal-to-noise ratio
RMS output noise
6
SPECIFICATIONS
74.5
fin = 30 MHz
74
fin = 50 MHz
73.5
fin = 70 MHz, TA = 25°C
73.5
fin = 70 MHz, TA =25°C to 85°C
70
73
fin = 70 MHz, TA –40°C
69
73
fin = 130 MHz
71.5
fin = 170 MHz
70.5
fin = 230 MHz
69
INPA and INMA tied to CMA
1.1
dBFS
LSBs
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212 – OCTOBER 2008
ANALOG ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over temperature range of TA = –40°C to 85°C, sampling rate =
80 MSPS, 50% clock duty cycle, AVDD = DRVDD = 3.3 V, –1-dBFS differential input, internal reference, and 3-VPP
differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP MAX
UNIT
Dynamic AC Characteristics (Continued)
fin = 10 MHz, TA = 25°C
SFDR
Spurious free dynamic range
84
fin = 30 MHz
83.5
fin = 50 MHz
84
fin = 70 MHz, TA = 25°C
fin = 70 MHz, TA = –40°C to 85°C
85
77
fin = 130 MHz
HD2
Second harmonic
76
fin = 230 MHz
68.5
fin = 10 MHz, TA = 25°C
95.8
fin = 30 MHz
95
fin = 50 MHz
97.5
fin = 70 MHz, TA = 25°C
95
Worst harmonic/spur other than HD2 or HD3
76
fin = 230 MHz
68.5
84
fin = 30 MHz
83.5
fin = 50 MHz
82.5
fin = 70 MHz, TA = 25°C
85
fin = 130 MHz
92
fin = 170 MHz
79
fin = 230 MHz
83
fin = 10 MHz, TA = 25°C
95.5
fin = 70 MHz, TA = 25°C
95
fin = 10 MHz, TA = 25°C
74
fin = 30 MHz
73.5
fin = 50 MHz
73.5
fin = 70 MHz, TA = 25°C
SINAD
Signal-to-noise plus distortion
70
72
fin = 70 MHz, TA = –40°C
69
72
fin = 130 MHz
71
fin = 170 MHz
69
fin = 10 MHz, TA = 25°C
fin = 30 MHz
fin = 50 MHz
THD
Total harmonic distortion
Channel-to-channel crosstalk
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fin = 70 MHz, TA = 25°C
dBc
dBc
73
fin = 70 MHz, TA = 25°C to 85°C
fin = 230 MHz
dBc
81.5
fin = 170 MHz
fin = 10 MHz, TA = 25°C
Third harmonic
dBc
81
fin = 170 MHz
fin = 130 MHz
HD3
82
dBFS
66
82.5
82
82
83.5
fin = 130 MHz
80
fin = 170 MHz
74
fin = 230 MHz
68
fin = 225 MHz
95
SPECIFICATIONS
dBc
dBc
7
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
3.7
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DIGITAL CHIP DC CHARACTERISTICS
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER (1)
VIL
Voltage input, low
VIH
Voltage input, high
(2) (3)
TEST CONDITIONS
(4)
Voltage output, low
Voltage output high (4)
IOH = –2 mA
|IPU|
Pullup current (tdi, tms, trst_n, ce_n, wr_n, rd_n,
reset_n ) (4)
|IPD|
|IIN|
UNIT
V
0.5
V
2.4
VDDS
V
VIN = 0 V, nominal 20 A
5
35
µA
Pulldown current (all other inputs and bidirectionals) (4)
VIN = VDDS, nominal 20 µA
5
35
µA
Leakage current (4)
VIN = 0V or VDDS, outputs in
high-impedance state
20
µA
Quiescent supply current, IDVDD or IVDDS
(4)
VIN = 0 for pads with pulldowns,
VIN = VDDS for inputs with pullups
(5)
Capacitance for inputs
CBI
Capacitance for bidirectionals (5)
8
MAX
V
IOL = 2 mA
CIN
(4)
(5)
TYP
0.8
VOH
(1)
(2)
(3)
MIN
2
VOL
IDDQ
VDDS = 3 V to 3.6 V
8
mA
5
pF
5
pF
Voltages are measured at low speed. Output voltages are measured with the indicated current load.
Currents are measured at nominal voltages, high temperature.
reset_n and interrupt have no timing specifications because they are asynchronous signals.
die_id pins fa002_out, fa002_clk, and fa002_scan are not specified and are for factory use only.
fuse pin fuse_out is not specified and is for factory use only.
test pins zero, scanen, testmode0 and testmode1 are not specified and are for factory use only.
Each part is tested at high temperature for the given specification. Lots are sample tested at –40°C.
Controlled by design and process and not directly tested.
SPECIFICATIONS
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
www.ti.com
SLWS212 – OCTOBER 2008
3.8 DIGITAL CHIP AC TIMING CHARACTERISTICS (1)
TA = –40°C to 85°C (unless otherwise noted)
PARAMETER
MIN
(2)
TYP MAX
UNIT
160
MHz
fCK
Clock frequency (adcclk_a/b/c/d, rxclk)
tCKL
Clock low period (below VIL) (adcclk_a/b/c/d, rxclk) (2)
2
ns
tCKH
Clock high period (above VIH) (adcclk_a/b/c/d, rxclk) (2)
2
ns
tRF
Clock rise and fall times (VIL to VIH) (adcclk_a/b/c/d, rxclk)
(3)
2
Input setup (rx_sync[a–d]) before rxclk rises (2)
Input setup (rxin_a/b/c/d_[0-15] ) before rxclk rises (ADC FIFO blocks bypassed) (2)
tSU
Input setup (rxin_a/b/c/d_[0-15] ) before adcclk_a/b/c/d rises (ADC FIFO blocks enabled)
Input hold (rx_sync[a–d]) after rxclk rises (2)
2
(2)
ns
2
1
Input hold (rxin_a/b/c/d_[0-15] ) after rxclk rises (adc fifo blocks bypassed) (2)
tHD
ns
2
2.5
Input hold (rxin_ a/b/c/d_[0-15] ) after adcclk_a/b/c/d rises (adc fifo blocks enabled) (2)
ns
1
tDLY
Data output delay (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out,
dvga_[a-d]_[5-0]) after rxclk rises. (2)
tOHD
Data output hold (rx_sync_out_[0-7], rxout_[0-7]_a/b/c/d, rxclk_out, rx_sync_out,
dvga_[a-d]_[5-0]) after rxclk rises. (2)
fJCK
JTAG clock frequency (tck) (2)
tJCKL
JTAG clock low period (below VIL) (tck) (2)
10
ns
tJCKH
JTAG clock high period (above VIH) (tck) (2)
10
ns
2
ns
(2)
JTAG input (tdi or tms) setup before tck goes high
tJHD
JTAG input (tdi or tms) hold time after tck goes high (2)
tJDLY
JTAG output (tdo) delay from falling edge of tck. (2)
tCSU
Control setup during reads or writes
3 pin mode: a[5:0] valid before rd_n, wr_n or ce_n falling edge
2 pin mode: a[5:0] and wr_n valid before ce_n falling edge (2)
tEWCSU
Control setup during writes
3 pin mode: d[15:0] valid before wr_n and ce_n rising edge
2 pin mode: d[15:0] valid before ce_n rising edge (2)
tCHD
Control hold during writes.
3 pin mode: a[5:0] and d[15:0] valid after wr_n and ce_n rise
2 pin mode: a[5:0], d[15:0] and wr_n valid after ce_n rise (2)
tCSPW
Control strobe (ce_n and wr_n low) pulse duration during write.
tCDLY
Control output delay ce_n and rd_n low and a[5:0] stable to d[15:0] during read.
Control recovery time between reads or writes.
Control end of read to Hi-Z. rd_n and ce_n rise to d[15:0] 3-state
tCOH
Control read d[15:0] output hold time
ns
6
ns
10
ns
6
ns
25
(2)
(2)
tHIZ
MHz
ns
10
(2)
ns
ns
10
tREC
(2)
(3)
(4)
0.5
40
tJSU
(1)
7
(4)
ns
25
ns
6
ns
10
ns
1
ns
Timing is measured from the respective clock at VDDS/2 to input or output at VDDS/2. Output loading is a 50-Ω transmission line whose
delay is calibrated out.
Each part is tested at 90°C case temperature for the given specification. Lots are sample tested at –40°C.
Recommended practice
Controlled by design and process and not directly tested.
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SPECIFICATIONS
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
www.ti.com
4 AFE8405 PINS
4.1 Analog Section Signals
Signal Name
Ball
Type
inpa
F3
Input
ADCA analog positive input
inma
F4
Input
ADCA analog negative input
NC
V4
—
NC
V3
—
clkpa
H1
Input
ADCA clock positive input
clkma
J1
Input
ADCA clock negative input
NC
R1
—
NC
T1
—
refpa
L3
Input
ADCA positive reference input. connect 0.1 µF to AVSS.
refma
K3
Input
ADCA negative reference input; connect 0.1 µF to AVSS.
NC
P3
—
NC
N3
—
cma
H3
Output
NC
T3
—
iref
M3
Input
clkouta
n/a
Output
ADCA output clock; internally connected to adcclka
da(13:0)
n/a
Output
ADCA output data; internally connected to rxin_a_15:2
fuse_sel
H5
Input
Connect to AVSS; factory use only
pdwn
L9
Input
Connect to AVDD, ADCA output enable; AVDD = enabled, AVSS = disabled
GND
N9
Input
ovra
G6
Output
NC
N8
—
pin_configure
Description
ADCA common-mode output reference
Current set; connect 56 kΩ to AVSS
ADCA over range indicator bit
T5
Input
Connect to AVDD, factory use only
dll_disable
N10
Input
Connect to AVDD, factory use only
AVDD
M9
Input
ext_ref
M10
Input
10
AFE8405 PINS
Connect to AVSS, AVDD = external reference, AVSS = internal reference
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4.2 Digital Receive Section Signals
Ball
Type
rxclk
Signal Name
R22
Input
Receive digital section clock input
adcclk_a
n/a
Input
rxin_a_x input clock; connected to ADCA output clock
adcclk_b
n/a
Input
Not used, not connected internally
adcclk_c
AA11
Input
rxin_c_x input clock
adcclk_d
AB11
Input
rxin_d_x input clock
rxin_c_ovr
AB6
Input
ADC overflow/overrange bit for rxin_c
rxin_d_ovr
V12
Input
ADC overflow/overrange bit for rxin_d
dvga_a_5
D7
Output
Digital VGA control output for ADC0 MSB
dvga_a_4
D8
Output
Digital VGA control output for ADC0
dvga_a_3
C7
Output
Digital VGA control output for ADC0
dvga_a_2
B7
Output
Digital VGA control output for ADC0
dvga_a_1
A7
Output
Digital VGA control output for ADC0
dvga_a_0
C8
Output
Digital VGA control output for ADC0 LSB
dvga_b_5
B8
Output
Not used
dvga_b_4
A8
Output
Not used
dvga_b_3
D9
Output
Not used
dvga_b_2
D10
Output
Not used
dvga_b_1
C9
Output
Not used
dvga_b_0
B9
Output
Not used
dvga_c_5
AA15
Output
Digital VGA control output for rxin_c MSB, test bus bit 1
dvga_c_4
AB15
Output
Digital VGA control output for rxin_c, test bus bit 0
dvga_c_3
V16
Output
Digital VGA control output for rxin_c, test bus bit 19
dvga_c_2
W16
Output
Digital VGA control output for rxin_c, test bus bit 18
dvga_c_1
Y16
Output
Digital VGA control output for rxin_c, test bus CLK
dvga_c_0
AA16
Output
Digital VGA control output for rxin_c LSB, test bus SYNC
dvga_d_5
AB16
Output
Digital VGA control output for rxin_d MSB, test bus AFLAG
dvga_d_4
V17
Output
Digital VGA control output for rxin_d
dvga_d_3
W17
Output
Digital VGA control output for rxin_d
dvga_d_2
AA17
Output
Digital VGA control output for rxin_d
dvga_d_1
AB17
Output
Digital VGA control output for rxin_d
dvga_d_0
V18
Output
Digital VGA control Output for rxin_d LSB
rxin_c_15
Y7
Input/output
Receive input data bus c bit 15 (MSB), test bus bit 17
rxin_c_14
AA7
Input/output
Receive input data bus c bit 14, test bus bit 16
rxin_c_13
AB7
Input/output
Receive input data bus c bit 13, test bus bit 15
rxin_c_12
Y8
Input/output
Receive input data bus c bit 12, test bus bit 14
rxin_c_11
V10
Input/output
Receive input data bus c bit 11, test bus bit 13
rxin_c_10
AA8
Input/output
Receive input data bus c bit 10, test bus bit 12
rxin_c_9
AB8
Input/output
Receive input data bus c bit 9, test bus bit 11
rxin_c_8
W9
Input/output
Receive input data bus c bit 8, test bus bit 10
rxin_c_7
Y9
Input/output
Receive input data bus c bit 7, test bus bit 9
rxin_c_6
AA9
Input/output
Receive input data bus c bit 6, test bus bit 8
rxin_c_5
AB9
Input/output
Receive input data bus c bit 5, test bus bit 7
rxin_c_4
W10
Input/output
Receive input data bus c bit 4, test bus bit 6
rxin_c_3
Y10
Input/output
Receive input data bus c bit 3, test bus bit 5
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AFE8405 PINS
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
Signal Name
www.ti.com
Ball
Type
rxin_c_2
AA10
Input/output
Receive input data bus c bit 2, test bus bit 4
rxin_c_1
AB10
Input/output
Receive input data bus c bit 1, test bus bit 3
rxin_c_0
W11
Input/output
Receive input data bus c bit 0 (LSB), test bus bit 2
rxin_d_15
W12
Input/output
Receive input data bus d bit 15 (MSB), test bus bit 35
rxin_d_14
Y12
Input/output
Receive input data bus d bit 14, test bus bit 34
rxin_d_13
AA12
Input/output
Receive input data bus d bit 13, test bus bit 33
rxin_d_12
AB12
Input/output
Receive input data bus d bit 12, test bus bit 32
rxin_d_11
V13
Input/output
Receive input data bus d bit 11, test bus bit 31
rxin_d_10
W13
Input/output
Receive input data bus d bit 10, test bus bit 30
rxin_d_9
Y13
Input/output
Receive input data bus d bit 9, test bus bit 29
rxin_d_8
AA13
Input/output
Receive input data bus d bit 8, test bus bit 28
rxin_d_7
AB13
Input/output
Receive input data bus d bit 7, test bus bit 27
rxin_d_6
V14
Input/output
Receive input data bus d bit 6, test bus bit 26
rxin_d_5
W14
Input/output
Receive input data bus d bit 5, test bus bit 25
rxin_d_4
AA14
Input/output
Receive input data bus d bit 4, test bus bit 24
rxin_d_3
AB14
Input/output
Receive input data bus d bit 3, test bus bit 23
rxin_d_2
V15
Input/output
Receive input data bus d bit 2, test bus bit 22
rxin_d_1
W15
Input/output
Receive input data bus d bit 1, test bus bit 21
rxin_d_0
Y15
Input/output
Receive input data bus d bit 0 (LSB), test bus bit 20
rx_synca
P21
Input
Receive sync input
rx_syncb
P22
Input
Receive sync input
rx_syncc
N20
Input
Receive sync input
rx_syncd
N21
Input
Receive sync input
rx_sync_out
E22
Output
Receive general purpose output sync
rxclk_out
E21
Output
Receive clock output
rx_sync_out_7
A20
Output
Receive serial interface frame strobe for rxout_7_x
rx_sync_out_6
C19
Output
Receive serial interface frame strobe for rxout_6_x, frame strobe (rx_sync_out signal) for
parallel interface
rx_sync_out_5
C17
Output
Receive serial interface frame strobe for rxout_5_x
rx_sync_out_4
C16
Output
Receive serial interface frame strobe for rxout_4_x
rx_sync_out_3
D15
Output
Receive serial interface frame strobe for rxout_3_x
rx_sync_out_2
B13
Output
Receive serial interface frame strobe for rxout_2_x
rx_sync_out_1
C12
Output
Receive serial interface frame strobe for rxout_1_x
rx_sync_out_0
A10
Output
Receive serial interface frame strobe for rxout_0_x
rxout_7_a
D20
Output
DDC 7 serial out data. CDMA A: I data UMTS: Imsb DDC parallel interface I(12)
rxout_7_b
C21
Output
DDC 7 serial out data. CDMA B: I data UMTS: Imsb – 1 DDC parallel interface I(13)
rxout_7_c
B20
Output
DDC 7 serial out data. CDMA A: Q data UMTS: Qmsb DDC parallel interface I(14)
rxout_7_d
C20
Output
DDC 7 serial out data. CDMA B: Q data UMTS: Qmsb –1 DDC parallel interface I(15)
rxout_6_a
A19
Output
DDC 6 serial out data. CDMA A: I data UMTS: Imsb DDC parallel interface I(8)
rxout_6_b
B19
Output
DDC 6 serial out data. CDMA B: I data UMTS: Imsb – 1 DDC parallel interface I(9)
rxout_6_c
A18
Output
DDC 6 serial out data. CDMA A: Q data UMTS: Qmsb DDC parallel interface I(10)
rxout_6_d
B18
Output
DDC 6 serial out data. CDMA B: Q data UMTS: Qmsb –1 DDC parallel interface I(11)
rxout_5_a
D18
Output
DDC 5 serial out data. CDMA A: I data UMTS: Imsbparallel interface I(4)
rxout_5_b
B17
Output
DDC 5 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface I(5)
rxout_5_c
D17
Output
DDC 5 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface I(6)
rxout_5_d
A17
Output
DDC 5 serial out data. CDMA B: Q data UMTS: Qmsb –1parallel interface I(7)
12
AFE8405 PINS
Description
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14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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Signal Name
SLWS212 – OCTOBER 2008
Ball
Type
A16
Output
DDC 4 serial out data. CDMA A: I data UMTS: Imsb parallel interface I(0)
rxout_4_b
B16
Output
DDC 4 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface I(1)
rxout_4_c
D16
Output
DDC 4 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface I(2)
rxout_4_d
A15
Output
DDC 4 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface I(3)
rxout_3_a
B15
Output
DDC 3 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(12)
rxout_3_b
C15
Output
DDC 3 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(13)
rxout_3_c
A14
Output
DDC 3 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(14)
rxout_3_d
B14
Output
DDC 3 serial out data. CDMA B: Q data UMTS: Qmsb –1 parallel interface Q(15)
rxout_2_a
D14
Output
DDC 2 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(8)
rxout_2_b
A13
Output
DDC 2 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(9)
rxout_2_c
C13
Output
DDC 2 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(10)
rxout_2_d
D13
Output
DDC 2 serial out data. CDMA B: Q data UMTS: Qmsb –1 parallel interface Q(11)
rxout_1_a
A12
Output
DDC 1 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(4)
rxout_1_b
B12
Output
DDC 1 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(5)
rxout_1_c
D12
Output
DDC 1 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(6)
rxout_1_d
A11
Output
DDC 1 serial out data. CDMA B: Q data UMTS: Qmsb –1 parallel interface Q(7)
rxout_0_a
B11
Output
DDC 0 serial out data. CDMA A: I data UMTS: Imsb parallel interface Q(0)
rxout_0_b
C11
Output
DDC 0 serial out data. CDMA B: I data UMTS: Imsb – 1 parallel interface Q(1)
rxout_0_c
B10
Output
DDC 0 serial out data. CDMA A: Q data UMTS: Qmsb parallel interface Q(2)
rxout_0_d
A9
Output
DDC 0 serial out data. CDMA B: Q data UMTS: Qmsb – 1 parallel interface Q(3)
rxout_4_a
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Description
AFE8405 PINS
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
www.ti.com
4.3 Microprocessor Signals
Ball
Type
d0
Signal Name
Y22
Input/output
MPU register interface data bus bit 0 (LSB)
d1
Y21
Input/output
MPU register interface data bus
d2
AB20
Input/output
MPU register interface data bus
d3
AA20
Input/output
MPU register interface data bus
d4
Y20
Input/output
MPU register interface data bus
d5
W20
Input/output
MPU register interface data bus
d6
V20
Input/output
MPU register interface data bus
d7
AB19
Input/output
MPU register interface data bus
d8
AA19
Input/output
MPU register interface data bus
d9
Y19
Input/output
MPU register interface data bus
d10
W19
Input/output
MPU register interface data bus
d11
V19
Input/output
MPU register interface data bus
d12
AB18
Input/output
MPU register interface data bus
d13
AA18
Input/output
MPU register interface data bus
d14
Y18
Input/output
MPU register interface data bus
d15
W18
Input/output
MPU register interface data bus bit 15 (MSB)
a0
T20
Input
MPU register interface address bus bit 0 (LSB)
a1
U22
Input
MPU register interface address bus
a2
U21
Input
MPU register interface address bus
a3
W22
Input
MPU register interface address bus
a4
V21
Input
MPU register interface address bus
a5
W21
Input
MPU register interface address bus bit 5 (MSB)
rd_n
T22
Input
MPU register interface read – active low
wr_n
R20
Input
MPU register interface write – active low
ce_n
T21
Input
MPU register interface chip enable – active low
Chip reset – active low
reset_n
R21
Input
interrupt
M21
Output
14
AFE8405 PINS
Description
Chip interrupt
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14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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4.4 JTAG Signals
Ball
Type
tdi
Signal Name
K22
Input
JTAG test data in
Description
tms
K21
Input
JTAG test mode select
trst_n
J22
Input
JTAG test reset
Note: the trst_n pin should be asserted low after power up to insure the JTAG logic is
properly initialized.
tck
L20
Input
tdo
L21
Output
JTAG test clock
JTAG test data out
4.5 Factory Test and No-Connect Signals
Ball
Type
testmode0
Signal Name
G21
Input
Do not connect; internal pulldown
Description
testmode1
G22
Input
Do not connect; internal pulldown
scanen
H21
Input
Do not connect; internal pulldown
fa002_scan
J20
Input
Do not connect; internal pulldown
fa002_clk
H22
Input
Do not connect; internal pulldown
fa002_out
J21
Output
zero
H20
Input
fuse_out
F20
Output
fuse_ena
D21
Input
Do not connect; internal pulldown
fuse_bias
F21
Input
Do not connect; internal pulldown
Do not connect
Do not connect; internal pulldown
Do not connect
4.6 Power and Ground Signals
Signal Name
Ball
Description
AVDD
H4, J3, L1, L2, M1, M2, M9, N1, N2, R3, T4
Analog power (3.3 V)
DRVDD
H6, H7, J8, K8, L8, P8, R8, T6, T7
Analog I/O power (3.3 V)
AVSS
A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C1, C2,
C3, C4, C5, D1, D2, D3, D4, D5, E1, E2, E3, E4,
E5, F1, F2, F5, F6, F7, F8, F9, G1, G2, G3, G4,
G5, G7, G8, G9, H2, J2, J4, J5, J6, K1, K2, K4, K5,
K6, L4, L5, L6, L7, M4, M5, M6, M7, N4, N5, N6,
N7, N9, P1, P2, P4, P5, P6, R2, R4, R5, R6, T2,
U1, U2, U3, U4, U5, U6, U7, U8, U9, V1, V2, V5,
V6, V7, V8, W1, W2, W3, W4, W5, Y1, Y2, Y3, Y4,
AA1, AA2, AA3, AA4, AB1, AB2, AB3, AB4
Analog ground
DRVSS
H8, H9, J7, J9, K7, K9, M8, P7, P9, R7, R9, T8, T9
Analog I/O ground
VDDS
B6, B21, D6, D11, D19, D22, E10, E11, E12, E13,
E14, E15, E16, E17, E18, E19, K20, M20, P20,
U11, U12, U13, U14, U15, U16, U17, U18, U19,
V11, W7, AA6, AA21
Digital I/O power (3.3 V), also called Vpad
DVDD
F22, G10, G19, H10, H19, J10, J19, K10, K19, L10, Digital core power (1.5 V), also called Vcore
L19, M19, N19, P10, P19, R10, R19, V22
DVSS
A6, A21, A22, B22, C6, C10, C14, C18, C22, E6,
Digital ground
E7, E8, E9, E20, F10, F11, F12, F13, F14, F15,
F16, F17, F18, F19, G11, G12, G13, G14, G15,
G16, G17, G18, G20, H11, H12, H13, H14, H15,
H16, H17, H18, J11, J12, J13, J14, J15, J16, J17,
J18, K11, K12, K13, K14, K15, K16, K17, K18, L11,
L12, L13, L14, L15, L16, L17, L18, M11, M12, M13,
M14, M15, M16, M17, M18, N11, N12, N13, N14,
N15, N16, N17, N18, N22, P11, P12, P13, P14,
P15, P16, P17, P18, R11, R12, R13, R14, R15,
R16, R17, R18, T10, T11, T12, T13, T14, T15, T16,
T17, T18, T19, U10, U20, V9, W6, W8, Y5, Y6,
Y11, Y14, Y17, AA5, AA22, AB5, AB21, AB22
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
www.ti.com
4.7 Digital Supply Monitoring
Signal Name
Ball
Description
dvddmon
L22
It is recommended that this pin be brought to a probe point for monitoring and debugging purposes.
dvssmon
M22
It is recommended that this pin be brought to a probe point for monitoring and debugging purposes.
4.8 JTAG
The JTAG standard for boundary scan testing is implemented for board testing purposes. Internal scan
test is not supported. Five device pins are dedicated for JTAG support: tdi, tdo, tms, tck, and trst_n. The
JTAG bsdl configuration file is available at www.ti.com.
NOTE
The trst_n pin should be asserted after power up to insure the JTAG logic is properly
initialized.
16
AFE8405 PINS
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5 Typical Characteristics
DIFFERENTIAL NONLINEARITY ERROR (DNL)
DNL − Differential Nonlinearity Error − LSB
1.00
0.75
0.50
0.25
0.00
−0.25
−0.50
−0.75
−1.00
0
2048
4096
6144
8192
10240
12288
14336
16384
Digital Output Codes
G001
Figure 5-1.
INTEGRAL NONLINEARITY ERROR (INL)
3.0
INL − Integral Nonlinearity Error − LSB
2.5
2.0
1.5
1.0
0.5
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
0
2048
4096
6144
8192
10240
12288
14336
16384
Digital Output Codes
G002
Figure 5-2.
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Typical Characteristics
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AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
www.ti.com
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 80 MSPS
fIN = 10.1 MHz
SFDR = 83.69 dBc
SINAD = 74.19 dBFS
SNR = 74.81 dBFS
THD = 81.56 dBc
−40
−20
Amplitude − dBFS
Amplitude − dBFS
−20
−60
−80
−100
−120
0.00
fS = 80 MSPS
fIN = 30.1 MHz
SFDR = 83.04 dBc
SINAD = 74.36 dBFS
SNR = 74.95 dBFS
THD = 81.99 dBc
−40
−60
−80
−100
0.25
0.50
0.75
1.00
−120
0.00
1.25
0.25
f − Frequency − MHz
0.50
0.75
1.00
G003
G004
Figure 5-3.
Figure 5-4.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 80 MSPS
fIN = 50.1 MHz
SFDR = 83.10 dBc
SINAD = 73.70 dBFS
SNR = 74.33 dBFS
THD = 80.99 dBc
−40
fS = 80 MSPS
fIN = 70.1 MHz
SFDR = 87.54 dBc
SINAD = 73.50 dBFS
SNR = 73.66 dBFS
THD = 85.66 dBc
−20
Amplitude − dBFS
Amplitude − dBFS
−20
−60
−80
−100
−120
0.00
−40
−60
−80
−100
0.25
0.50
0.75
1.00
1.25
f − Frequency − MHz
−120
0.00
0.25
0.50
0.75
Figure 5-5.
Typical Characteristics
1.00
1.25
f − Frequency − MHz
G005
18
1.25
f − Frequency − MHz
G006
Figure 5-6.
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14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
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SLWS212 – OCTOBER 2008
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 80 MSPS
fIN = 90.1 MHz
SFDR = 83.93 dBc
SINAD = 72.96 dBFS
SNR = 73.3 dBFS
THD = 82.54 dBc
−40
−20
Amplitude − dBFS
Amplitude − dBFS
−20
−60
−80
−100
−120
0.00
fS = 80 MSPS
fIN = 130.1 MHz
SFDR = 80.69 dBc
SINAD = 72.02 dBFS
SNR = 72.6 dBFS
THD = 79.65 dBc
−40
−60
−80
−100
0.25
0.50
0.75
1.00
−120
0.00
1.25
0.25
f − Frequency − MHz
0.50
0.75
1.00
G007
G008
Figure 5-7.
Figure 5-8.
SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 80 MSPS
fIN = 170.1 MHz
SFDR = 78 dBc
SINAD = 70.41 dBFS
SNR = 71.55 dBFS
THD = 75.55 dBc
−40
fS = 80 MSPS
fIN = 230.1 MHz
SFDR = 71.47 dBc
SINAD = 68.43 dBFS
SNR = 70.53 dBFS
THD = 70.92 dBc
−20
Amplitude − dBFS
Amplitude − dBFS
−20
−60
−80
−100
−120
0.00
1.25
f − Frequency − MHz
−40
−60
−80
−100
0.25
0.50
0.75
1.00
1.25
f − Frequency − MHz
−120
0.00
0.25
0.50
0.75
1.00
G009
Figure 5-9.
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1.25
f − Frequency − MHz
G010
Figure 5-10.
Typical Characteristics
19
AFE8405
14-BIT, 85-MSPS, SINGLE-ADC, 8-CHANNEL WIDEBAND RECEIVER
SLWS212 – OCTOBER 2008
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SPECTRAL PERFORMANCE
SPECTRAL PERFORMANCE
0
0
fS = 80 MSPS
fIN1 = 70.15 MHz, –7 dBFS
fIN2 = 70.25 MHz, –7 dBFS
IMD3 = −85 dBFS
−20
−20
−40
Amplitude − dBFS
Amplitude − dBFS
−40
−60
−80
−60
−80
−100
−100
−120
−120
−140
0.00
fS = 80 MSPS
fIN1 = 150.13 MHz, –7 dBFS
fIN2 = 150.23 MHz, –7 dBFS
IMD3 = −87 dBFS
0.25
0.50
0.75
1.00
−140
0.00
1.25
f − Frequency − MHz
0.25
0.50
0.75
1.00
1.25
f − Frequency − MHz
G011
G012
Figure 5-11.
Figure 5-12.
AC PERFORMANCE
vs
INPUT AMPLITUDE
AC PERFORMANCE
vs
INPUT AMPLITUDE
120
80
SFDR (dBFS)
100
SNR (dBFS)
AC Performance − dB
AC Performance − dB
100
120
60
SFDR (dBc)
40
SNR (dBc)
20
0
80
SFDR (dBFS)
SNR (dBFS)
60
SFDR (dBc)
40
SNR (dBc)
20
0
fS = 80 MSPS
fIN = 69.5 MHz
−20
−90 −80 −70 −60 −50 −40 −30 −20 −10
fS = 80 MSPS
fIN = 150.5 MHz
−20
−90 −80 −70 −60 −50 −40 −30 −20 −10
0
Input Amplitude − dBFS
G013
Figure 5-13.
20
Typical Characteristics
0
Input Amplitude − dBFS
G014
Figure 5-14.
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DDC PERFORMANCE WITH WCDMA CARRIER
0
0
−20
−20
Normalized Amplitude − dB
Normalized Amplitude − dB
DDC PERFORMANCE WITH WCDMA CARRIER
−40
−60
−80
−100
fDATA = 61.44 MSPS
IF = 70 MHz, 0 dBm
DDC Rate = 122.88 MSPS
−120
−140
−4
−3
−2
−1
0
1
−40
−60
−80
−100
fDATA = 61.44 MSPS
IF = 140 MHz, 0 dBm
DDC Rate = 122.88 MSPS
−120
2
3
−140
−4
4
−3
f − Frequency − MHz
−2
−1
0
1
2
3
G016
Figure 5-15.
Figure 5-16.
DDC Performance With CDMA2000 Carrier
DDC Performance With CDMA2000 Carrier
0
0
−20
−20
Normalized Amplitude − dB
Normalized Amplitude − dB
G015
−40
−60
−80
fDATA = 78.6432 MSPS
IF = 70 MHz, 0 dBm
DDC Rate = 78.6432 MSPS
−100
−120
−1.5
−1.0
−0.5
0.0
0.5
4
f − Frequency − MHz
−40
−60
−80
fDATA = 78.6432 MSPS
IF = 140 MHz, 0 dBm
DDC Rate = 78.6432 MSPS
−100
1.0
−120
−1.5
1.5
f − Frequency − MHz
−1.0
−0.5
0.0
0.5
1.0
1.5
f − Frequency − MHz
G017
G018
Figure 5-17.
Figure 5-18.
A
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Typical Characteristics
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DDC Performance (WCDMA Carrier With Tone Blocker)
fDATA = 61.44 MSPS, DDC rate = 122.88 MSPS, WCDMA carrier at 70 MHz and –71 dBFS, tone blocker at 73 MHz and
–1 dBFS.
ADC OUTPUT
DDC OUTPUT
0
0
−20
−40
P − Power − dBm
Normalized Amplitude − dB
−20
−60
−80
−40
−60
−100
−80
−120
−100
−4
−140
0
5
10
15
20
25
30
−3
−2
−1
0
1
2
3
4
f − Frequency − MHz
f − Frequency − MHz
G020
Figure 5-19.
DDC Performance (CDMA Carrier With Two-Tone Blocker)
fDATA = 78.6432 MSPS, DDC rate = 78.6432 MSPS, CDMA2000 carrier at 70 MHz and –84 dBFS, tone 1 at 70.9 MHz and
–12 dBFS, tone 2 at 71.7 MHz and –12 dBFS.
ADC OUTPUT
DDC OUTPUT
0
0
−20
−40
P − Power − dBm
Normalized Amplitude − dB
−20
−60
−80
−40
−60
−100
−80
−120
−140
0
5
10
15
20
25
30
−100
−1.5
−1.0
−0.5
0.0
0.5
1.0
1.5
f − Frequency − MHz
f − Frequency − MHz
G022
Figure 5-20.
22
Typical Characteristics
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Typical values are at TA = 25°C, differential input amplitude = –1 dBFS, test bus output
73
71
72
100
69
fS - Sampling Frequency - MHz
74
90
73
80
74
72
73
71
70
60
72
74
75
73
50
71
72
40
20
40
80
60
100
70
71
140
120
180
160
200
220
fIN - Input Frequency - MHz
69
72
71
70
73
75
74
SNR - dBc
M0048-03
Figure 5-21.
80
82
100
80
78
80
82
fS - Sampling Frequency - MHz
90
84
84
80
70
82
86
84
90
88
86
84
72
78
76
80
88
72
74
82
88
86
70
76
74
84
60
86
90
50
82
88
40
20
84
86
88
40
60
80
80
100
78
76
120
140
74
180
160
72
70
200
220
fIN - Input Frequency - MHz
68
72
80
76
SFDR - dBc
84
88
M0049-03
Figure 5-22.
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6 ANALOG-TO-DIGITAL CONVERTERS
The AFE8405 includes a high-performance, single-channel, 14-bit, 85-MSPS analog-to-digital converter
(ADC). To provide a complete solution, the ADC channel includes a high-bandwidth linear
sample-and-hold stage (S&H) and internal reference. An internal reference is provided, simplifying system
design requirements, yet an external reference can be used optionally to suit the accuracy and low-drift
requirements of the application.
refpa
refma
Internal
Reference
inpa
S&H
inma
clkpa
clkma
Dual 14-Bit 85-MSPS ADC
14-Bit
Pipelined
ADC Core
Digital
Error
Correction
da(13:0)
Output
Control
Timing Circuitry
ovra
clkouta
B0105-02
Figure 6-1. ADC Block Diagram
The ADC digital output data and output clocks are connected directly to the rxin_a port of the AFE8405
digital section. The ovra output connects directly to the AFE8405 digital section and also to a package
ball. The ADC outputs can be accessed through the test bus in decimate-by-32× mode only.
6.1 ADC Operation
The conversion process is initiated by a falling edge of the external input clocks. Once the signal is
captured by the input S&H, the input sample is sequentially converted by a series of small resolution
stages, with the outputs combined in a digital correction logic block. Both the rising and the falling clock
edges are used to propagate the sample through the pipeline every half clock cycle. This process results
in data latency of 16.5 clock cycles, after which the output data is available as a 14-bit parallel word,
coded in binary 2s-complement format to the AFE8405 receive section.
6.2 ADC Input Configuration
The analog input for the ADC consists of a differential sample-and-hold architecture implemented using a
switched-capacitor technique shown in Figure 6-2.
24
ANALOG-TO-DIGITAL CONVERTERS
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S3a
L1
C1a
R1a
inp
CP3
S1a
CP1
L2
R1b
R3
S2
CA
S1b
+
C1b
inm
CP4
CP2
–
VINCM
1V
S3b
L1, L2, : 6 nH to 10 nH effective
R1a, R1b : 5 W to 8 W
C1a, C1b : 2.2 pF to 2.6 pF
CP1, CP2 : 1.8 pF to 2.2 pF
CP3, CP4 : 1.2 pF to 1.8 pF
CA : 0.8 pF to 1.2 pF
R3 : 80 W to 120 W
Switches : S1a, S1b : On Resistance : 35 W to 50 W
S2 : On Resistance : 7.5 W to 15 W
S3a, S3b : On Resistance : 40 W to 60 W
All switches Off Resistance : 10 GW
All switches are on in sampling phase which is approximately one half of a clock period.
S0175-01
Figure 6-2. Analog Input Stage
This differential input topology produces a high level of ac performance for high sampling rates. It also
results in a high usable input bandwidth, especially important for high intermediate-frequency (IF) or
undersampling applications. The ADC requires each of the analog inputs (inp, inm) to be externally biased
around the common-mode level of the internal circuitry (cmx). For a full-scale differential input, each of the
differential lines of the input signal swings symmetrically between cm + 0.575 V and cm – 0.575 V. This
means that each input is driven with a signal of up to cm ± 0.575 V, so that each input has a maximum
differential signal of 1.15 VPP for a total differential input signal swing of 2.3 VPP. The maximum swing is
determined by the two reference voltages, the top reference (refpa) and the bottom reference (refma).
The ADC obtains optimum performance when the analog inputs are driven differentially. The circuit shown
in Figure 6-3 shows one possible configuration using an RF transformer.
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Z0
50 W
R0
50 W
25 W
inp
1:1
25 W
AC
Signal
Source
100 nF
AFE8405
25 W
ADT1-1WT
inm
cm
25 W
10 W
100 nF
0.1 mF
S0176-06
Figure 6-3. Transformer Input to Convert Single-Ended Signal to Differential Signal
The single-ended signal is fed to the primary winding of an RF transformer. Because the input signal must
be biased around the common-mode voltage of the internal circuitry, the common-mode voltage (VCM)
from the ADC is connected to the center-tap of the secondary winding. To ensure a steady low-noise VCM
reference, best performance is obtained when the common-mode output is filtered to ground with a 10-Ω
series resistor and parallel 0.1-µF and 0.001-µF low-inductance capacitors.
Output VCM is designed to drive the ADC input directly. When providing a custom common-mode level, be
aware that the input structure of the ADC sinks a common-mode current in the order of 200 µA (100 µA
per input). Equation 6-1 describes the dependency of the common-mode current and the sampling
frequency:
400mA f s(in MSPS)
20 )
125 MSPS
(6-1)
This equation helps to design the output capability and impedance of the driving circuit accordingly.
When it is necessary to buffer or apply a gain to the incoming analog signal, it is possible to combine
single-ended operational amplifiers with an RF transformer, or to use a differential input/output amplifier
without a transformer, to drive the input of the AFE8405 ADC. Texas Instruments offers a wide selection of
single-ended operational amplifiers (including the THS3201, THS3202, OPA847, and OPA695) that can
be selected depending on the application. An RF gain block amplifier, such as Texas Instruments
THS9001, can also be used with an RF transformer for high-input-frequency applications. The
THS4503/6/9 are recommended differential input/output amplifiers. Table 6-1 lists the recommended
amplifiers.
Table 6-1. Recommended Amplifiers to Drive the Input of the AFE8405
INPUT SIGNAL FREQUENCY
RECOMMENDED AMPLIFIER
TYPE OF AMPLIFIER
DC to 20 MHz
THS4503/6/9
Differential in/out amplifier
No
DC to 50 MHz
OPA847
Operational amplifier
Yes
10 MHz to 120 MHz
OPA695
Operational amplifier
Yes
THS3201
Operational amplifier
Yes
THS3202
Operational amplifier
Yes
THS9001
RF gain block
Yes
Over 100 MHz
26
ANALOG-TO-DIGITAL CONVERTERS
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When using single-ended operational amplifiers (such as the THS3201, THS3202, OPA847, or OPA695)
to provide gain, a three-amplifier circuit is recommended with one amplifier driving the primary of an RF
transformer and one amplifier in each of the legs of the secondary driving the two differential inputs of the
ADC. These three amplifier circuits minimize even-order harmonics. For high-frequency inputs, an RF gain
block amplifier can be used to drive a transformer primary; in this case, the transformer secondary
connections can drive the input of the ADC directly, as shown in Figure 6-3, or with the addition of the
filter circuit shown in Figure 6-4.
Figure 6-4 illustrates how RIN and CIN can be placed to isolate the signal source from the switching inputs
of the ADC and to implement a low-pass RC filter to limit the input noise in the ADC. It is recommended
that these components be included in the AFE8405 circuit layout when any of the amplifier circuits
discussed previously are used. The components allow fine-tuning of the circuit performance. Any
mismatch between the differential lines of the ADC input produces a degradation in performance at high
input frequencies, mainly characterized by an increase in the even-order harmonics. In this case, special
care should be taken to keep as much electrical symmetry as possible between both inputs.
Another possible configuration for lower-frequency signals is the use of differential input/output amplifiers
that can simplify the driver circuit for applications requiring dc coupling of the input. Flexible in their
configurations (see Figure 6-5), such amplifiers can be used for single-ended-to-differential conversion
and signal amplification.
5V
VIN
–5 V
+
OPA695
–
RS
100 W
0.1 mF
RIN
1:1
RT
100 W
1000 pF
imp
AFE8405
imm
cm
CIN
RIN
R1
400 W
10 W
AV = 8V/V
(18 dB)
R2
57.5 W
0.1 mF
S0177-05
Figure 6-4. Converting a Single-Ended Input Signal to a Differential Signal Using an RF Transformer
RS
RG
RF
5V
RT
3.3 V
10 mF
0.1 mF
RIN
inp
VOCM
1 mF
RIN
10 mF
RG
inm
THS4503
–5 V
AFE8405
14-Bit/85-MSPS
cm
0.1 mF
10 W
RF
0.1 mF
S0178-02
Figure 6-5. Using the THS4503 With the AFE8405
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6.3 ADC Input Voltage Overstress
The AFE8405 ADC can handle absolute maximum voltages of 3.6 V dc on the input pins inp and inm. For
dc inputs between 3.6 V and 3.8 V, a 25-Ω resistor is required in series with the input pins. For inputs
above 3.8 V, the device can handle only transients, which must have less than 5% duty cycle of
overstress. The input pins connect internally to an ESD diode to AVDD, as well as a switched capacitor
circuit. The sampling capacitor of the switched capacitor circuit connects to the input pins through a switch
in the sample phase. In this phase, an input larger than 2.65 V would cause the switched capacitor circuit
to present an equivalent load of a forward biased diode to 2.65 V in series with a 60-Ω impedance. Also,
beyond the voltage on AVDD, the ESD diode to AVDD starts to become forward biased.
In the phase where the sampling switch is off, the diode loading from the input switched capacitor circuit is
disconnected from the pin, while the ESD loading to AVDD is still present.
CAUTION
A violation of any of the previously stated conditions could damage the device (or
reduce its lifetime) either due to electromigration or gate oxide integrity. Care should
be taken not to expose the device to input overvoltage for extended periods of time,
as it may degrade device reliability.
6.4 ADC Reference Circuit
The AFE8405 ADC has built-in internal reference generation, requiring no external circuitry on the printed
circuit board (PCB). For optimum performance, it is best to connect both refp and refm to ground with a
1-µF decoupling capacitor in series with a 20-Ω resistor, as shown in the Figure 6-6. In addition, an
external 56.2-kΩ resistor should be connected from iref to AVSS to set the proper current for the operation
of the ADC, as shown in Figure 6-6. No capacitor should be connected between these pins; only the
56.2-kΩ resistor should be used.
20 W
29 refp
1 mF
20 W
30 refm
1 mF
31 iref
56.2 kW
S0179-01
Figure 6-6. REFP, REFM, and IREF Connections for Optimum Performance
6.5 ADC Clock Input
The AFE8405 ADC clock input can be driven with either a differential clock signal or a single-ended clock
input, with little or no difference in performance between the configurations. The common-mode voltage of
the clock inputs is set internally to cm using internal 5-kΩ resistors that connect clkp and clkm to cm, as
shown in Figure 6-7.
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cm
cm
5 kW
5 kW
clkp
clkm
6 pF
3 pF
3 pF
S0180-01
Figure 6-7. Clock Inputs
When driven with a single-ended CMOS clock input, it is best to connect clkm to ground with a 0.01-µF
capacitor, while clkp is ac-coupled with a 0.01-µF capacitor to the clock source, as shown in Figure 6-8.
Square Wave or
Sine Wave
clkp
0.01 mF
AFE8405
clkm
0.01 mF
S0168-15
Figure 6-8. AC-Coupled, Single-Ended Clock Input
The ADC clock input can also be driven differentially, reducing susceptibility to common-mode noise. In
this case, it is best to connect both clock inputs to the differential input clock signal with 0.01-µF
capacitors, as shown in Figure 6-9.
clkp
Differential Square Wave or
Sine Wave
(3 VP-P)
0.01 mF
AFE8405
clkm
0.01 mF
S0167-11
Figure 6-9. AC-Coupled, Differential Clock Input
For high-input-frequency sampling, it is recommended to use a clock source with low jitter. Additionally,
the internal ADC core uses both edges of the clock for the conversion process. This means that, ideally, a
50% duty cycle should be provided.
Bandpass filtering of the source can help produce a 50% duty-cycle clock and reduce the effect of jitter.
When using a sinusoidal clock, the clock jitter further improves as the amplitude is increased. In that
sense, using a differential clock allows for the use of larger amplitudes without exceeding the supply rails
and absolute maximum ratings of the ADC clock input.
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7 RECEIVE DIGITAL SIGNAL PROCESSING
The downconversion section of the AFE8405 consists of the receive input interface, the rx_distribution
bus, and eight digital downconverter blocks.
The purpose of the receive input interface is to accept signal data from three 16-bit input ports, measure
the input signal power, control the digital VGA, and distribute the data to the DDC blocks. The input
interface also has a user-controlled test generator and noise source.
The rx_distribution bus distributes the three channels of signal data to each of the eight DDC blocks.
Each DDC block selects one of the three channels (or two for complex input data) from the rx_distribution
bus and then performs downconversion tuning, programmable delay, channel filtering with decimation,
power measurement, fixed gain adjust, and/or automatic gain control. Each DDC block can support one
UMTS channel, two CDMA channels, or two TD-SCDMA channels. An optional mode permits stacking two
DDC blocks in UMTS mode to provide double-length final pulse-shape filtering.
Tuned, filtered, and decimated signal data is output in bit-serial or parallel format.
7.1 Receive Input Interface
6
dvga_a
rxin_a
(1)
16
Test & Noise
Signal
Generator
16
18
16
FIFO
Dual Real or
Single Complex
Power Meter
To Testbus
Dual Real or
Single Complex
AGC
1 to 64
Sample
Delay
Line
delay_a
rxin_b
(2)
16
Test & Noise
Signal
Generator
16
16
6
dvga_b
6
dvga_c
rxin_c
16
Test & Noise
Signal
Generator
16
rxin_d
16
Test & Noise
Signal
Generator
18
16
Dual Real or
Single Complex
Power Meter
Testbus
Sources
16
Dual Real or
Single Complex
AGC
1 to 64
Sample
Delay
Line
delay_c
16
FIFO
6
dvga_d
rx_distribution
Bus to DDC
Channels
delay_b
FIFO
Test Bus Select
and Decimation
18
1 to 64
Sample
Delay
Line
FIFO
18
1 to 64
Sample
Delay
Line
delay_d
B0106-01
(1)
Hard-wired to internal ADCA
(2)
The rxin_b port is not used and not connected internally.
Figure 7-1. Receive Data Input Interface
The AFE8405 receive input data interface accepts data from several sources:
• Signal data from the integrated 14-bit ADC (rxin_a)
• Signal data presented at the two 16-bit digital data input ports (rxin_c and rxin_d)
• An LFSR test signal generator allows the AFE8405 to be tested using a known repetitive data
sequence.
30
RECEIVE DIGITAL SIGNAL PROCESSING
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For the rxin_c and rxin_d input ports, signal data can be provided in binary or 2s-complement form. The
location of the ADC's MSB can be programmed to allow additional AGC headroom if desired. For
example, a 14-bit ADC may be connected with the MSBs aligned or shifited down to allow the AGC
additional gain range before clipping the signal.
Signal data can be accepted at rates up to rxclk in UMTS mode for either eight normal channels or four
double-length final pulse-shaping filter channels. In CDMA mode, the maximum input rate is rxclk for real
inputs, or rxclk/2 for complex inputs. For maximum filter performance, higher clock rates generally allow
longer filters.
Complex signal data is input with I data driving one input port and Q data driving another. This means that
there is only one signal data port available when using complex input mode (rxin_c and rxin_d).
Signal input data is clocked into eight-stage FIFOs using a matching external clock signal, adcclk_a/b/c/d.
Signal data is clocked out of the FIFO from a gated rxclk (the AFE8405 receive section clock). The FIFO
allows an arbitrary phase relationship between adcclk_a/c/d and rxclk. The frequency relationship is
mandated by the programmed configuration.
The test and noise generator can supply test sequences or add noise to the input signal data. The test
sequences, when combined with the checksum generators, are useful for initial board debug or power-on
self-test.
For applications that require receiver desensitization, the noise generator can add noise to input data
streams.
The ADC input port, rxin_a, can be passed to the test-bus control block, decimated by 32×, and routed
directly to the AFE8405 test-bus output pins. The key requirement of this function is to be able to verifiy
the performance of the ADC by reconstructing the samples, while limiting the output sample rate to less
than 5 MHz using an 85-MHz ADC sample rate.
Many other internal chip signals can be routed to the test bus for evaluation and debug purposes. When
the test bus is enabled, the rxin_c and rxin_d ports are driven as digital outputs.
Each of the four outputs to the DDC channels includes a 1- to 64-sample delay line.
A
PROGRAMMING
VARIABLE
DESCRIPTION
ssel_ddc(2:0)
Selects the sync source for the DDC data input multiplexer and mixer. This sets the sync source for DDC input clock
generation and synchronization for all DDC channels.
offset_bin_X
Selects offset binary input when set, 2s complement input when cleared. X = {a, b, c, d}. Note that the internal ADCs
use 2s complement format, so offset_bin_a must be set.
msb_pos_X(2:0)
Identifies the connection location of the ADC’s MSB. Programmed values of {0..7} correspond to msb at {rxin_x_15..
rxin_x_8}. X = {a, b, c, d}
7.1.1
Receive FIFO
The receive FIFO consists of an eight-stage memory and two counters generating the input write pointer
and output read pointer. When the FIFO receives a sync signal, the input and output pointers are
initialized with a write-to-read pointer offset of four samples. Input samples from rxin_X (writes) are
clocked with the adcclk_X input clock rising edges, and the input pointer advances on each clock rising
edge. Output samples (reads) and the output pointer are clocked with the rxclk input signal rising edges,
divided by the programmed sample rate loaded into the rate_sel(1:0) control register.
A
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PROGRAMMING
VARIABLE
DESCRIPTION
adc_fifo_bypass
When set, bypasses the input FIFOs and input data is latched directly using the rxclk. When cleared, input data is
latched using the adcclk_a/b/c/d inputs.
ssel_adc_fifo(2:0)
Selects the sync source for the FIFO state machines. This sync signal initializes the FIFO input and output
pointers.
rate_sel(1:0)
This selects the FIFO input and output rate; {rxclk, rxclk/2, rxclk/4 or rxclk/8}. For example, with rxclk at 153.6
MHz, set rate_sel to 0, 1, 2, or 3, respectively, for adcclk_a/b/c/d 153.6, 76.8, 38.4, or 19.2 MHz. Must be set the
same as DDCCONFIG1 register ch_rate_sel(1:0).
adc_fifo_strap_ab
When set, the rxin_a and rxin_b FIFO input and output pointers are synchronized to support complex input
signals. (Note: rxin_b is not used.)
adc_fifo_strap_cd
When set, the rxin_c and rxin_d FIFO input and output pointers are synchronized to support complex input
signals.
7.1.2
Receive Input Power Meters
From rxin_a FIFO Output
I
Power Meter 0
Power Meter 0 Results
Power Meter 1
Power Meter 1 Results
Power Meter 2
Power Meter 2 Results
Power Meter 3
Power Meter 3 Results
pmeter_iq0
Q
From rxin_b FIFO Output
I
Q
pmeter_iq1
From rxin_c FIFO Output
I
pmeter_iq2
Q
From rxin_d FIFO Output
I
Q
pmeter_iq3
B0107-01
Figure 7-2. Receive Input Power Meters
Four receive input RMS power meters are provided by design. For real inputs, three power meters (power
meter 0/2/3) can be used to measure the RMS power of the combined carriers in each of the three input
signals from rxin_a/c/d (the Q input is held at zero). For complex inputs from rxin_c and rxin_d, one power
meter can be use to measure the combined complex power and the other can be disabled (rxin_b is not
used in the AFE8405).
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32
16
I
33
58-Bit
Integrator
58-Bit
Register
32
16
Q
Transfer
Clear
9-Bit
Sync Delay
Counter
Sync
RMS Power
21-Bit
Integration
Counter
21-Bit
Interval
Counter
9
21
Delay
(in 8 Sample
Increments)
Interrupt
21
Interval
(in 8 Sample
Increments)
Integration
(in 8 Sample
Increments)
B0108-01
Figure 7-3. Detailed Functionality of Receive Input Power Meter
Sync
Delay
Interrupt
Integration Time
Interrupt
Integration Time
Interval Time
Sync
Event
Integration
Start
Interrupt
Integration Time
Interval Time
Integration
Start
Integration
Start
T0116-01
Figure 7-4. Receive Input Power Meter Timing
Power is calculated by squaring each 16-bit I (I and Q for complex inputs) sample, summing, and then
integrating the summed-squared results into a 58-bit accumulator over a programmable integration period.
The integration period is programmed into the 21-bit counter, in eight-sample increments. The power read
is:
Power = [ (I2) × (N × 8 + 1) ] for real inputs, where N is the integration count.
Power = [ (I2 + Q2) × (N × 8 + 1) ] for complex inputs, where N is the integration count.
A programmable 21-bit interval counter sets the power measurement interval (how often power is
measured) in eight-sample increments. A measurement integration period is started at the beginning of
each interval period.
The process begins with a sync event starting the 9-bit delay counter. After (8 × sync_delay + 2) samples,
the integration interval is started. Integration continues until the integration count is met, at which point the
58-bit integrator results are transferred to the read-only register and an interrupt is generated. A new
measurement period starts at the end of the interval period.
The 21-bit counters in eight-sample increments allow up to 104.8-mS interval times at 160-MHz clock.
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NOTE
Each of the four composite RMS power meter blocks has its own delay sync, interval, and
integration period counters, as well as separate sync source registers.
PROGRAMMING
VARIABLE
DESCRIPTION
recv_pmeterX (57:0)
58-bit power measurement result. X = {0, 1, 2, 3}.
recv_pmeterX_sqr_sum(20:0)
21-bit integration (square and sum) period. X = {0, 1, 2, 3}.
recv_pmeterX_sync_delay(8:0)
Power meter delay sync period. X = {0, 1, 2, 3}.
recv_pmeterX_strt_intrvl(20:0)
21-bit measurement interval. X = {0, 1, 2, 3}. The strt_intrvl value must be greater than the sqr_sum
value.
ssel_recv_pmeter_X(2:0)
Sync source. X = {0, 1, 2, 3}.
pmeterX_iq
Selects complex power measurement input mode when set. X = {0, 1, 2, 3}.
recv_pmeterX_ena
Enables power meter when set. X = {0, 1, 2, 3}.
7.1.3
Receive Input AGC (RAGC)
Input signals from the ADCs can be used to create a front-end composite AGC loop when combined with
a digitally controlled variable-gain amplifier (DVGA) connected before the ADCs. The AGC system
operates by integrating the square of the ADC samples over a programmable interval and applying a
table-driven error signal to a loop integrator based on the squared integration output. The error table maps
the signal power to a user-programmed error value. The loop integrator output is used to drive map tables
to control the DVGA output pins and a gain adjustment multiplier. Fast updates can be enabled if desired,
to cause the loop integrator to adjust quickly to interfering signals. The ADC input signals can also be
passed through a high-pass filter to remove dc offset before squaring the input.
The programmable error table, integrator mapping tables, and clip thresholds, when combined with the
user-programmable interval timers, provide a highly flexible AGC function.
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Integrate and Dump Signal Power Measurement
enable corner
55
acc_offset
acc_shift
6
Samples 16
From
ADC FIFO
5
31
Highpass
Filter
2
X
Shift
and
Limit
128w x 8b RAM
7
7
7
0
1
+
Limit
{127..0}
{127..0}
Map
Error
Table
Map
Table
8
Update
5
Error
Shift
err_shift
sd_thresh
Signal
Level
Detect
Signal Detect
Mode Controls
64w x 22b RAM
Map
6 MSBs DVGA
6
Table
Map
Table
Gain
Map
Gain
16
Table
Map
Table
Loop Accumulator
no_signal
Freeze Control Register Bit
Freeze From Sync Source
Clear Control Register Bit
Clear Sync Source
Clip
Detect
Mag
clip_error
32
16
16
Delay Adjust
16
clip_hi_thresh
clip_low_thresh
Clip Detect Controls
to DVGA
Pins
5
Delay
To DDC
Channels
16
Sync
Update
Sync
Delay
Update Interval
B0109-01
Figure 7-5. Receive Input AGC
The AGC measurement interval timer is a 24-bit timer initialized by a sync after a programmable 8-bit
delay. During the integration interval, the squared input signal is shifted by the programmed value and
accumulated. At the end of the interval time, an update pulse is generated, and the selected 7 bits of the
55-bit accumulated power is upper-limit checked and transferred to the power holding register. A
programmable offset is applied, and the following limit check produces a 7-bit address value for the RAM
error map table. The user-programmable error map table and following gain-shift setting are used to
determine the loop error signal to be added to the 32-bit AGC loop accumulator. The error value is only
added to the loop accumulator once per update. The loop accumulator upper 6 MSBs are used as the
address for the programmable DVGA map table and gain map table. The gain map table address can be
delayed from 0 to 31 clock cycles to align DVGA changes to signal level changes at the output of the
AGC.
The AGC includes four sources for freezing the loop and holding the loop accumulator constant. A general
sync source can be used to control the freeze directly; when the selected sync source is high, the AGC is
held, and when low, the AGC operates. A control register bit freezes the AGC in the same fashion; when
the bit is set, the AGC is held, and when cleared, the AGC operates. A signal level detector is provided
that can be used to freeze the AGC loop automatically in the event of input signal loss. A programmable
signal detection threshold value, number of samples below the signal detection threshold, and window
timer are used to determine when no signal is present. Finally, a programmable number of AGC updates
after sync can be programmed, and the AGC is held until the next sync event. Freeze holds the loop
accumulator constant, the integrate-and-dump accumulator constant, and the interval timer constant.
When freeze is released, the interval timer resumes counting.
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A sync event always reinitializes the integrate-and-dump interval timer and terminates the pending update
to the loop accumulator from the current integrate-and-dump measurement interval. For example, if a sync
event occurs during an integrate-and-dump interval, that interval is terminated without updating the loop,
and the integrate-and-dump accumulator is cleared. After the programmed sync delay, a new interval
starts.
The AGC includes a dual-threshold clip-detect function, using two programmable 16-bit thresholds and
programmable counters. The clip detector causes immediate loop accumulator updates while the clip
event is active. The 16-bit clip error value is aligned at the MSBs of the loop accumulator. Clip events are
qualified when a programmed number of samples are above the clip-high threshold during the
programmable clip window time. For example, a clip event can be defined as eight samples above the
clip-high threshold in a 256-sample window; the clip-high threshold, the number of samples above the
clip-high threshold, and the sample window time are programmable. Once the clip event has occurred, the
clip duration is controlled by the clip-low threshold value, clip-low samples value, and clip-low timer. The
clip event is cleared when the number of samples below the clip-low threshold exceeds the programmed
value within the clip-low timer window. The clip-low threshold, number of clip-low samples, and the clip-low
window timer are programmable.
The AGC blocks can be paired together, rxin_a with rxin_b, and rxin_c with rxin_d, to produce a complex
input AGC mode. The clip detector output from the rxin_b/d AGCs is logically ORed with the rxin_a/c clip
detect outputs. The squared input function before the integrate-and-dump and signal-level detector is
replaced with an I2 + Q2 power calculation. The accumulator MSBs from the rxin_a/c AGCs are connected
to the rxin_c/d DVGA map table and gain map table inputs. This arrangement allows the AGCs to operate
in a direct-conversion receiver system by controlling the I2 + Q2 complex signal level.
The high-pass filter is a 32-bit accumulator followed by an adjustable shift to control the corner frequency,
a subtractor to remove the accumulated offset, and a final limiter to produce a 16-bit result. The high-pass
filter function is enabled by setting hp_ena; clearing hp_ena holds the accumulator reset.
32
Samples
From
ADC FIFO
–
16
hp_corner
3
17
Shift
and
Limit
+
hp_ena
16
17
16
Limit
Samples to
2
X Block
B0110-01
Figure 7-6. High-Pass Filter in Receive Input AGC
PROGRAMMING
VARIABLE
DESCRIPTION
ragc_bypass_X
Bypasses the entire receive AGC circuit when set. X = {0, 1, 2, 3}
hp_ena_X
Enables high pass filter when set
hp_corner_X(2:0)
Adjusts the corner frequency of the high-pass filter
integ_interval_X(23:0)
Integrate-and-dump signal-power measurement interval in samples.
acc_shift_X(4:0)
Shift-down amount following the integrate-and-dump accumulator.
acc_offset_X(5:0)
Offset value applied to the shifted integrate-and-dump output.
ragc_sync_delay_X(7:0)
AGC sync delay interval, from 1 to 256 samples
ssel_ragc_interval_X(2:0)
Sync source selection for the interval timer
ssel_ragc_freeze_X(2:0)
Sync source selection for AGC freeze
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PROGRAMMING
VARIABLE
DESCRIPTION
ssel_ragc_clear_X(2:0)
Sync source selection for the AGC loop accumulator clear
ragc_freeze_X
Register bit to freeze the AGC when set
ragc_clear_X
Register bit to clear the AGC accumulator when set
ragc_update_X(7:0)
Sets the number of updates per sync event, after which no further updates occur until the next sync
event. Program to 0x00 to update continually.
sd_ena_X
Enables freezing the AGC with the signal detector when set
sd_thresh_X(15:0)
Signal-detection threshold for AGC channel X. This 16-bit word is lined up with bits 23 down to 8 of the
square output. The smallest signal level that can be programmed is therefore 16 LSBs on the ADC
input, and the largest is 4095 LSBs at the ADC input.
sd_samples_X(15:0)
The number of samples below the signal detect threshold within the signal detect sample timer window
required to freeze on the AGC.
sd _timer_X(15:0)
Window timer to qualify signal detection.
clip_hi_thresh_X(15:0)
Clip detector high threshold
clip_lo_thresh_X(15:0)
Clip detector low threshold
clip_hi_samples_X(7:0)
A clip event is detected when the number of samples above the clip-high threshold within the clip-high
sample timer window exceeds this value.
clip_lo_samples_X(7:0)
A clip event ends when the number of samples below the clip-low threshold within the clip-low sample
timer window exceeds this value.
clip_hi_timer_X(15:0)
Window timer to qualify clip events
clip_lo_timer_X(15:0)
Window timer to determine when the clip event ends.
clip_error_X(15:0)
Error signal applied to the AGC accumulator when a clip event is active. This data is MSB aligned, and
therefore can cause immediate changes to the accumulator.
ragc_error_map_X
128-word × 8-bit memory holding the log to error look up table
dvga_map_X
64-word × 6-bit memory holding the accumulator to DVGA look-up table
gain_map_X
64-word × 16-bit memory holding the accumulator to GAIN look-up table (256 decibels is unity gain).
delay_adj_X(4:0)
Delay between DVGA output updates and gain map updates to compensate for ADC pipeline delays,
etc.
err_shift_X(4:0)
Error map table shift-up output before adding to loop accumulator
complex_01
Enables complex AGC mode on inputs rxin_a and rxin_b when set
complex_23
Enables complex AGC mode on inputs rxin_c and rxin_d when set
ragc_accum_X(31:0)
32-bit read-only register holding the current contents of the loop accumulator.
3-state(10:7)
3-state controls for the dvga_d/c/b/a output pins; pins are in the high-impedance state when the 3-state
bits are set.
ragc_mpu_ram_read
When set, the receive AGC map RAMs are readable via the MPU control interface. The AFE8405 signal
path is not operational when this bit is set, it is intended for debug purposes only.
7.1.4
Test and Noise Signal Generator
The test and noise generator can generate test signals to replace the rxin_a/b/c/d inputs as a tool for
debug, evaluation, and self-test. Checksum generators included in the individual DDC channels at the
outputs can be used in conjunction with the noise generator and the internal sync timer block to create the
built-in self-test function.
The test and noise signal source included in this block is a 23-bit linear feedback shift register (LFSR) with
a fixed polynomial and fixed initialization state. A sync input is required to initialize the LFSR, and the sync
source is connected to the ddc_counter output signal.
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sync
LFSR
lfsr(22:0)
adcclk_X
Initialized On Sync Event - Each of the Four Generators Has a Different Seed
5
22
0
B0111-01
Figure 7-7. Noise Signal Generator
Receive Input Port
38
LFSR Seed Value, MSB to LSB
rxin_a
100 0000 0000 0000 0001 0000 (0x40 0010)
rxin_b
010 0110 1110 0110 1100 1110 (0x26 E6CE)
rxin_c
110 1110 1010 0010 1001 1000 (0x6E A298)
rxin_d
000 1011 0001 1110 1011 0111 (0x0B 1EB7)
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The 23-bit LFSR output signal if used to create a 16-bit dout(15:0) test signal using XOR combinations of
the LFSR bits.
lfsr22
lfsr20
dout9
lfsr19
lfsr22
dout8
dout15
lfsr16
lfsr18
dout7
lfsr22
dout14
lfsr17
lfsr15
dout6
lfsr16
lfsr22
dout13
lfsr14
dout5
lfsr15
lfsr22
dout12
lfsr13
dout4
lfsr14
lfsr22
dout11
lfsr12
dout3
lfsr13
lfsr22
dout10
lfsr11
dout2
lfsr12
dout1
lfsr11
dout0
lfsr10
B0112-01
Figure 7-8. Mapping of LFSR Values to Output Bits
To enable the test signal generator, the slf_tst_ena control bit is set. The rxin_a/b/c/d signals are then
replaced by the four generator output streams. To use this test signal generator as a signal source for
self-test, the user must also set the adc_fifo_bypass control bit. Setting the adc_fifo_bypass control bit
causes the adcclk_a/b/c/d input clocks to be internally replaced with rxclk/N, where N is programmed with
the rate_sel(1:0) control bits to {1, 2, 4, or 8}.
The test signal generators can also output a programmable constant value. All four test signal generators
output the same programmable constant value.
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16
rxin_a
16
Data to FIFO for rxin_a
16
Test and
Noise
Generator
sync
16
rxin_b
16
Data to FIFO for rxin_b
16
Test and
Noise
Generator
16
rxin_c
16
Data to FIFO for rxin_c
16
Test and
Noise
Generator
16
rxin_d
16
Data to FIFO for rxin_d
16
Test and
Noise
Generator
rduz_sens_ena
slf_tst_ena
B0113-01
Figure 7-9. Block Diagram of Noise Generator Input Options
The LFSR circuits can also be used to add noise to the rxin_a/b/c/d input signals by setting the
rduz_sens_ena control register bit. The magnitude of the noise added can be adjusted by programming
the nz_pwr_mask(15:0) control register. In Figure 7-10, X = {a ,b, c, or d}.
16
16
rxin_X(15:0)
To FIFO for rxin_X
16
16
lfsr(15:0)
nz_pwr_mask(15:0)
16 XORs
16
16 ANDs
lfsr17
lfsr16
rduz_sens_ena
B0114-01
Figure 7-10. Detail Circuit for Adding Noise Generator Signal to rxin Signal
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PROGRAMMING
VARIABLE
DESCRIPTION
slf_tst_ena
When set, the test signal generators replace the rxin_a/b/c/d input signals with internally generated
pseudorandom sequences. The fifo_bypass bit must be set when this bit is set.
rduz_sens_ena
Enables the LFSR, adding noise to the ADC input data when set.
nz_pwr_mask(15:0)
Selects the power of the noise added to the ADC input data.
adc_fifo_bypass
When set, the FIFO is essentially bypassed, and the adcclk_a/b/c/d clock input ports are ignored.
ddc_counter(31:0)
32-bit general-purpose counter interval
ddc_counter_width(7:0)
8-bit general-purpose counter timeout pulse counter
ssel_ddc_counter(2:0)
Sync source selection for the general purpose counter
self_test_constant(17:0)
18-bit self-test constant value applied to all four rxin_a/b/c/d inputs when self_test_const_ena is set.
self_test_const_ena
Enables the self-test constant value for rxin_a/b/c/d
7.1.5
Sample Delay Lines
The four sample delay line blocks each consist of a 64-register memory and a state machine. The state
machine uses a counter to control the write (input) pointer, and the programmed read offset register data
to create the read (output) pointer. Programming larger read offset register values increases the effective
delay at a resolution equal to the sample rate.
The read offset registers, delay_line_X, are double-buffered. Writes to these registers may occur anytime,
but the actual values used by the circuit are not updated until a delay line sync event occurs.
A
PROGRAMMING
VARIABLE
DESCRIPTION
delay_line_X(5:0)
Read offset into the 64-element memory for each delay line. X = {0, 1, 2, 3}.
ssel_delay_line_X(2:0)
Selects the sync source used to update the double-buffered delay line register.
7.1.6
Test Bus
When the test bus is enabled, the rxin_c(15:0) and rxin_d(15:0) ports become outputs, and the dvga_c
and dvga_d pins are combined with the rxin_c(15:0) and rxin_d(15:0) pins to allow 36-bit wide signals
from the DDC channels and the receive input interface to be multiplexed to this test output port. Many of
these sources can be decimated to reduce the output sample rates.
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MUX
ddc_tst_sel(5:0)
DDC0
zeros
pfiroutput
cfiroutput
tadjchannel A
tadjchannel B
ncosin
ncocos
cicoutput
mixer i * cos & i * sin
mixer q * cos & q * sin
ddc mux channel A
ddc mux channel B
MUX
tst_select(3:0)
DECIMATE
(35:20)
tst_decim17
(19:18)
tst_decim_delay
(17:2)
(1:0)
tst_clk
tst_aflag
tst_sync
rxin_d(15:0)
dvga_c(3:2)
rxin_c(15:0)
dvga_c(5:4)
dvga_c(1)
dvga_d(5)
dvga_c(0)
DDC1
Sync
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
Receive Interface
rxin_a FIFO Outputs
B0115-02
Figure 7-11. Test Bus Output Circuit Showing Options for Selecting Signal
PROGRAMMING
VARIABLE
DESCRIPTION
ssel_tst_decim(2:0)
Selects the sync source for the testbus decimator
tst_decim_delay(3:0)
Sets the test-bus decimator delay from sync
tst_decim17
Must be cleared
tst_on
Enables the test bus; rxin_c(15:0) and rxin_d(15:0) are changed from inputs to outputs, dvga_c(5:0) and
dvga_d(5) are used as part of the test bus.
tst_select(3:0)
Selects the source block for the testbus output: DDC0–DDC7 or receive interface.
ddc_tst_sel(5:0)
Selects the signal to be output from the DDC block
tst_rate_sel(4:0)
Sets the test-bus output clock period to (tst_rate_sel + 1) rxclk cycles. When the testbus source is set to
the ADC FIFO, tst_rate_sel(4:0) must be set to 0 for an output.
tst_clk_pol
Selects the polarity of the test clock output at dvga_c(1) when the test bus is enabled; 0 for rising edge
in the center of valid data, 1 for falling edge in the center of valid data. No effect when tst_rate_sel is
0 0000.
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7.2 DDC Organization
18
18
18
18
4 to 2 (Complex) or
4 to 1 (Real) Switch
CDMA DDC A
Output
Interface
or 1 UMTS DDC
4 to 2 (Complex) or
4 to 1 (Real) Switch
CDMA DDC B
DDC0
DDC1
DDC2
DDC3
DDC4
DDC5
DDC6
DDC7
B0116-01
Figure 7-12. DDC Organization for Single-Length Filter Mode
The AFE8405 provides downconversion for up to eight UMTS receive channels, 16 CDMA2000 receive
channels or 16 TD-SCDMA receive channels. Downconversion channels are organized into 8 DDC blocks.
Each individual DDC block provides two CDMA2000 or two TD-SCDMA DDC channels, A and B, or one
UMTS channel.
Both CDMA DDC channels in a DDC block can be independently tuned, though they would likely be used
as diversity pairs and tuned to the same frequency. Filter coefficients are shared between the two CDMA
DDC channels within a block.
Two adjacent DDC blocks (for example, DDC0 and DDC1) can be strapped together to form a single
UMTS DDC channel with double-length final pulse shaping filtering. The AFE8405 can therefore provide
four UMTS DDC channels with double-length final PFIR filtering as shown in the following diagram.
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18
18
18
18
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4 to 2 (Complex) or
4 to 1 (Real) Switch
CDMA DDC A
Output
Interface
4 to 2 (Complex) or
4 to 1 (Real) Switch
CDMA DDC B
DDC0
DDC1
4 to 2 (Complex) or
4 to 1 (Real) Switch
CDMA DDC A
or 1 UMTS DDC
4 to 2 (Complex) or
4 to 1 (Real) Switch
Output
Interface
CDMA DDC B
DDC0 Plus DDC1
DDC2 Plus DDC3
DDC4 Plus DDC5
DDC6 Plus DDC7
B0117-01
Figure 7-13. DDC Organization for Double-Length Filter Mode
PROGRAMMING
VARIABLE
DESCRIPTION
ddc_ena
When set, turns on the DDC.
cdma_mode
When set, puts the DDC block in dual-channel CDMA mode.
gbl_ddc_write
When set, all subsequent programming (writes only) for DDC0 and DDC1 is also written to DDC2/4/6 and DDC3/5/7.
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7.2.1
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Downconverter Function Blocks
From
rx_distribution
Bus
18
18
18
18
Delay
Adjust
4 to 2
Select
Zero
Pad
Six Stage
CIC Filter
Dec 4 to 32
Checksum
Generator
Frequency
Phase
32
16
NCO
CFIR
Filter
Dec by 2
PFIR
Filter
Dec by 1
AGC
Serial
Interface
Serial I, Q
up to 18
(25-Bits With
AGC Disabled)
RMS Power
Measure
Parallel I, Q
B0118-01
Figure 7-14. DDC Functional Block Diagram
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Each AFE8405 downconversion block can process two CDMA carriers or a single UMTS carrier. Signal
data is selected from one of four ports for real inputs, or two of four ports for complex inputs. Data from
the selected port(s) is multiplied with a complex, programmable, numerically controlled oscillator (NCO)
which tunes the signal of interest to baseband. The delay adjust and zero pad blocks permit adjustment of
the delay in the end-to-end channel. Zero padding interpolates the signal to the rxclk rate. Filtering
consists of a six-stage CIC filter which decimates the tuned data by a factor from 4 to 32, a compensating
FIR filter (CFIR) which decimates by a factor of two, followed by a programmable FIR filter (PFIR) which
does not decimate. The output interface block can be programmed to decimate by 2 if desired.
The RMS power meter measures the power within the channel bandwidth. The AGC automatically drives
the gain and keeps the magnitude of the signal at a user-specified level. This allows fewer bits to
represent the signal. The serial output interface formats and rounds the output data. Each of the
previously mentioned blocks is described in greater detail in the following sections.
7.2.2
DDC Mixer
From
rx_distribution
Bus
18
18
18
18
4 to 2
Select
18
18
Demux
and
Round
20
18
18
18
18
IA
QA
IB
QB
To
Channel
Delay
20
mixer_gain
Sin
Cos
From NCO
B0119-01
Figure 7-15. Mixer Functional Block Diagram
The receive mixer translates the input (from one of the input signal sources) to baseband where
subsequent filtering is performed to isolate the signal of interest. The mixer is a complex multiplier that
accepts 18-bit I and 18-bit Q signal data from the receive input interface and 20-bit sine and cosine
sequences from the NCO. The NCO generates a mixing frequency (sometimes referred to as a local
oscillator, or LO) specified by the user so that the desired signal is tuned to 0 Hz.
A DDC channel can support one UMTS signal directly, or two CDMA channels at half the input rate. When
in CDMA mode, the path selection and the mixer tuning and phase of each channel can be set
independently. The mixer output produces two complex streams; one representing the signal path for the
A-side DDC, the other for the B-side. Each of these streams drives a channel delay and zero pad block.
The maximum input rate for UMTS is rxclk for either real or complex input data.
The maximum input rate in CDMA mode with real inputs is rxclk (remix_only is set, see the following).
The maximum input rate in CDMA mode with complex inputs is rxclk/2 due to sharing of multiplier
resources.
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PROGRAMMING
VARIABLE
DESCRIPTION
ddcmux_sel_a(3:0)
Programs the I and Q complex input data routing onto two of the four input ports for stream A of CDMA DDC
ddcmux_sel_b(3:0)
Programs the I and Q complex input data routing onto two of the four input ports for stream B of CDMA DDC
remix_only
For CDMA mode only, set this bit for real input data at the rxclk rate.
For complex inputs in CDMA mode, the maximum input data rate is rxclk/2, and this bit must be cleared.
For CDMA mode with real inputs at the rxclk/2 rate or lower, this bit must be cleared.
zero_qsample
When set, the Q samples used by the mixer are always zero. This bit should be set for real only inputs in UMTS
mode, or real-only inputs in CDMA mode when the input sample rate is rxclk/2 or lower.
ch_rate_sel(1:0)
Specifies the input channel data rate (rxclk, rxclk/2, rxclk/4, or rxclk/8 MSPS). MUST BE SET THE SAME AS
REGISTER rate_sel(1:0).
mixer_gain
When asserted, adds 6 dB of gain in the mixer. This gain is highly recommended.
7.2.3
DDC Numerically Controlled Oscillator (NCO)
Frequency Sync
20
Frequency Word
32
Reg
32
Reg
32
23
23
Clear
Aligned
to Bottom
32 Bits
Zero Phase Sync
Phase Offset Sync
Phase Offset
16
Reg
5
Sin/Cos
Table
20
cos
sin
Aligned
to Bottom
5 Bits
Dither
Generator
16
Dither Sync
B0120-01
Figure 7-16. Detailed NCO Circuit
The NCO is a digital complex oscillator that is used to translate (or downconvert) an input signal of interest
to baseband. The block produces programmable complex digital sinusoids by accumulating a frequency
word which is programmed by the user. The output of the accumulator is a phase argument that indexes
into a sin/cos ROM table which produces the complex sinusoid. A phase offset can be added prior to
indexing if desired for channel calibration purposes. This changes the sin/cos phase with respect to the
NCOs of other channels.
A 5-bit dither generator is provided and generates a small level of digital pseudonoise that is added to the
phase argument below the bottom bits and is useful for reducing NCO spurious outputs. This dither
generation is enabled by setting the dither_ena bit; the magnitude of the dither can be reduced by setting
one or both of the dither_mask bits.
A
DITHER PROGRAMMING
VARIABLE
DESCRIPTION
dither_ena
When set, turns dither on. Clearing turns dither off.
dither_mask(1:0)
Masks the MSB and MSB – 1 dither bits, respectively, when set.
The NCO spurious levels are better than –115 dBc. Added phase dither randomizes the periodic nature of
the phase accumulation process and reduces low-level spurious energy. For some frequencies (N ×
Fs/24, where N = {1, 2, ..., 23}), dither is ineffective. In these cases, an initial phase of 4 reduces NCO
spurs. Figure 7-17 shows the spur level performance of the NCO without dither, with dither, and with a
phase offset value.
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a) Worst Case Spectrum Without Dither
b) Spectrum With Dither (Tuned to Same Frequency
Figure 7-17. NCO SFDR - Without Dither
a) Plot Without Dither or Phase Initialization
Figure 7-19. NCO Spectra (0 and Fs/4) - Without Dither or
Phase Initialization
Figure 7-18. NCO SFDR - With Dither
b) Plot With Dither or Phase Initialization
Figure 7-20. NCO Spectra (0 and Fs/4) - With Dither or
Phase Initialization
The tuning frequency is specified as a 32-bit frequency word and is programmed as two sequential 16-bit
words over the control port. The NCO frequency resolution is fclk/ 232, where fclk is the ADCCLK frequency.
As an example, at an input clock rate of 61.44 MHz, the frequency step size would be approximately 14
mHz. The frequency word is determined by the formula:
Frequency word (in decimal) = 232 × tuning frequency / fclk
Note that frequency tuning words can be positive or negative valued. Specifying a positive frequency
value translates complex negative frequencies upwards towards 0 Hertz. Specifying a negative tuning
frequency translates complex positive frequencies downwards towards 0 Hz.
A
FREQUENCY PROGRAMMING
VARIABLE
DESCRIPTION
phase_add_a(31:0)
32-bit tuning frequency word for the A-side DDC when in CDMA mode. Also for UMTS mode.
phase_add_b(31:0)
32-bit tuning frequency word for the B-side DDC when in CDMA mode. Not used in UMTS mode.
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Each of the 16 CDMA DDC channels can be loaded with unique frequency values.
The phase of the NCO sin/cos output can be adjusted relative to the phase of other channel NCOs by
specifying a phase offset. The phase offset is programmed as a 16-bit word, yielding a step size of about
5.5 m°. The phase offset word is determined by the formula:
Phase offset word = 216 × offset_in_degrees / 360, or
Phase offset word = 216 × offset_in_radians / 2π
A
PHASE PROGRAMMING
VARIABLE
DESCRIPTION
phase_offset_a(15:0)
16-bit phase offset word for the A-side DDC when in CDMA mode. Also for UMTS mode.
phase_offset_b(15:0)
16-bit phase offset word for the B-side DDC when in CDMA mode. Not used in UMTS mode.
Each of the 16 CDMA DDC channels can be loaded with unique phase-offset values.
Various synchronization signals are available which are used to synchronize the NCOs of all channels
with respect to each other. Frequency sync and phase-offset sync determine when frequency and phase
offset changes occur. For example, generating a frequency sync after programming the two frequency
words causes the NCO (or multiple NCOs) to change frequency at that time, rather than after each of the
three frequency words is programmed over the control bus. The zero-phase sync signal is used to force
the sine and cosine oscillators to their zero-phase state. Dither sync can be used to synchronize the dither
generators of multiple NCOs. The NCOs used in the transmit section are identical to what is described for
the receive section. Note that there is one set of syncs provided for each DDC. When one DDC is used to
process two CDMA signals, the syncs are shared between them.
A
SYNC PROGRAMMING
VARIABLE
DESCRIPTION
ssel_nco(2:0)
Sync source for NCO accumulator reset
ssel_dither(2:0)
Sync source for NCO dither reset
ssel_freq(2:0)
Sync source for NCO frequency register loading
ssel_phase(2:0)
Sync source for NCO phase register loading
7.2.4
DDC Filtering and Decimation
The purpose of the receive filter chain is to isolate the signal of interest (and reject all others) that has
been previously translated to baseband via the mixer and NCO. The overall decimation through the chain
must be considered. The goal, generally, is to output the isolated signal at a rate that is twice (2×) the
signal’s chip rate. For UMTS this would be 7.68 MSPS and for CDMA the output rate should be 2.4576
MSPS. TD-SCDMA systems require the output rate be the chip rate of 1.28 MSPS. The output interface is
programmed to decimate by 2 for the TD-SCDMA case.
Receive filtering and decimation is performed in several stages:
1. Zero-padding to interpolate the input sample rate (if needed) up to the rxclk rate
2. High-rate decimation (4 to 32) using a six-stage cascade-integrate-comb filter (CIC)
3. Decimate-by-two compensation filtering using the programmable compensating FIR filter (CFIR)
4. Pulse-shape filtering via the programmable FIR filter (PFIR) with no decimation
5. Output interface, serial or parallel format, with no decimation or decimate-by-2
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Delay
Adjust
From
Mixer
Six Stage
CIC Filter
Dec by {4–32}
Zero Pad
Interp by {1, 2, 4 ,8}
CFIR Filter
Dec by 2
Output Interface
Dec by {1, 2}
PFIR Filter
No Decimation
B0121-01
Figure 7-21. DDC Filtering Functional Block Diagram
Table 7-1 contains some examples of decimation and sample rates at the output of each block for UMTS,
CDMA and TD-SCDMA standards at various supported input samples. For each example, the differential
ADC clocks are provided to the AFE8405 at the input sample rate and rxclk is provided at the zero-pad
output rate.
Table 7-1. Examples of Decimation and Sample Rates (1)
Input
Sample
Rate
(MSPS)
Zeros
Added
rxclk(MHz) and
Zero-Pad
Output Rate
(MSPS)
CIC
Decimation
CIC
Output
Rate
(MSPS)
CFIR
Decimation
CFIR
Output
Rate
(MSPS)
PFIR
Decimation
PFIR
Output
Rate
(MSPS)
Output
Decimation
UMTS
76.80
UMTS
61.44
1
153.6
10
15.36
2
7.68
1
7.68
1
1
122.88
8
15.36
2
7.68
1
7.68
1
CDMA
78.6432
CDMA
78.6432
0
78.6432
16
4.9152
2
2.4576
1
2.4576
1
1
157.2864
32
4.9152
2
2.4576
1
2.4576
CDMA
1
61.44
1
122.88
25
4.9152
2
2.4576
1
2.4576
1
TD-SCDMA
81.92
0
81.92
16
5.12
2
2.56
1
2.56
2
TD-SCDMA
76.80
0
76.80
15
5.12
2
2.56
1
2.56
2
TD-SCDMA
76.80
1
153.6
30
5.12
2
2.56
1
2.56
2
TD-SCDMA
61.44
1
122.88
24
5.12
2
2.56
1
2.56
2
(1)
The DDC output interfaces, both serial and parallel formats, can be programmed to decimate by 2. For the TD-SCDMA examples listed,
the DDC output rate is 1.28 Msps (1× chip rate).
7.2.5
DDC Channel Delay Adjust and Zero Insertion
Interpolation
(Number of Zeros Stuffed Between Samples)
Input Rate
Samples From
Mixer
I
Q
Read Offset
18
18
Delay Memory
I:8 Slots ´ 18 Bits
Q:8 Slots ´ 18 Bits
3
18
18
18
Zero
Pad
18
I
Q
Full rxclk Rate
Samples to
CIC Filter
3
Sync (Offset Registers)
Sync (Zero Stuff Moment)
Insert Offset
3
B0122-01
Figure 7-22. DDC Delay and Zero Insertion Block
The receive-channel delay-adjust function is used to add programmable delays in the channel
downconvert path. Adjusting channel delay can be used to compensate for analog elements external to
the AFE8405 digital downconversion such as cables, splitters, analog downconverters, filters, etc.
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The delay memory block consists of an eight-register memory and a state machine. The state machine
uses a counter to control the write (input) pointer, and the programmed read offset register data to create
a read (output) pointer. Programming larger read offset register values increases the effective delay at a
resolution equal to the input sample rate.
The zero-pad block is used in conjunction with the delay memory for delay adjustments. For example, with
input rates of rxclk/8, the zero-pad block interpolates the input data to rxclk by inserting seven zeros. The
zero-pad’s sync and insert-offset controls specify when the zeros are inserted relative to the sync signal.
This permits a fine adjustment at the rxclk resolution.
The read offset register, tadf_offset_course_a/b, and the insert offset register, tadj_offset_fine_a/b, are
double-buffered. Writes to these registers may occur anytime, but the actual values used by the circuit are
not updated until a register sync.
A
PROGRAMMING
VARIABLE
DESCRIPTION
tadj_offset_coarse_a(2:0)
Read offset into the eight-element memory for the UMTS or CDMA mode-A channel DDC.
tadj_offset_coarse_b(2:0)
Read offset into the eight-element memory for the CDMA mode-B channel DDC when in CDMA mode.
tadj_offset_fine_a(2:0)
Controls the zero-pad (or stuff) insert offset (fine adjust) for the UMTS or CDMA mode-A channel of the
DDC.
tadj_offset_fine_b(2:0)
Controls the zero-pad (or stuff) insert offset (fine adjust) for the CDMA mode-B channel of the DDC
when in CDMA mode.
tadj_interp(2:0)
The interpolation value (1, 2, 4, or 8). Same used for both the A and B channels when in CDMA mode.
Selects the number of zeros to be inserted.
ssel_tadj_fine(2:0)
Selects the sync source for the fine time-adjust, zero-stuff moment. Same for A and B channels when in
CDMA mode.
ssel_tadj_reg(2:0)
Selects the sync source used to update the double-buffer caurse- and fine-delay selection registers.
Same for A and B channels when in CDMA mode.
7.2.6
DDC CIC Filter
Shift
18
–1
Z
N
–1
–1
–m1
Z
–1
Z
Z
–m2
Z
–1
Z
–m3
Z
–1
Z
–m4
Z
54
Z
–m5
Z
Shift
0–31
–m6
Z
24
Decimate
by 4–32
24
Round
and
Limit
18
B0123-01
Figure 7-23. DDC CIC Filter Block Diagram
The CIC filter provides the first stage of filtering and large-value decimation. The filter consists of six
stages and decimates over a range from 4 to 32.
I data and Q data are handled separately with two CIC filters. In addition, when in CDMA mode (two
CDMA channels processed within a single DDC), another pair of CIC filters handles the B-side channel.
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The filter response is 6×(sin(x)/x) in character where the key attribute is that the resulting response nulls
signal aliases from decimation. A consequence of this desirable behavior is that only a small portion of the
passband can be used, generally less than 25%. This means that the CIC decimation value should be
chosen so that the signal exiting the CIC filter is oversampled by at least a factor of four.
The filter is equivalent to six stages of an FIR filter with uniform coefficients (six combined boxcar filter
stages). Each filter would be of length N if m = 1, or 2N if m = 2.
The filter is made up of six banks of 54-bit accumulator sections followed by six banks of 24-bit subtractor
sections. Each of the subtractor sections can be independently programmed with a differential delay of
either one or two. A shift block follows the last integration stage and can shift the 54-bit accumulated data
down by 36-rcic_shift (a programmable factor from 0 to 31 bits).
The CIC filter exhibits a droop across its frequency response. The following CFIR filter compensates for
the CIC droop with a gradually rising frequency response. It is also possible to compensate for CIC droop
in the PFIR filter.
The gain of the receive CIC filter is:
Ncic6 × 2(number of stages where M=2) × 2(–36+RCIC_SHIFT), where RCIC_SHIFT is 0 to 31.
There is no rollover protection internal to the CIC or at the final round, so the user must ensure no sample
exceeds full scale prior to rounding. For practical purposes, this means the CIC gain can only compensate
for peak gain less than one or must be less than or equal to one. A fixed gain of 12 dB at the output of the
CIC can also be programmed.
A
PROGRAMMING
VARIABLE
DESCRIPTION
cic_decim(4:0)
The CIC decimation ratio (4 to 32). The ratio is cic_decim + 1. This ratio applies to both A and B channels of
the DDC block in CDMA mode.
cic_scale_a(4:0)
The shift value for the A channel. A value of 0 is no shift; each increment in value increases the amplitude of
the shifter output by a factor of 2.
cic_scale_b(4:0)
The shift value for the B channel. A value of 0 is no shift; each increment in value increases the amplitude of
the shifter output by a factor of 2.
cic_gain_ddc
When asserted, adds a gain of 12 dB at the CIC output.
cic_m2_ena_a(5:0)
Sets the differential delay value M for each of the CIC subtractor stages for the UMTS or CDMA mode A
channel.
cic_m2_ena_b(5:0)
Sets the differential delay value M for each of the CIC subtractor stages for the CDMA mode B channel.
cic_bypass
Bypasses the CIC filter when set, for factory use only.
ssel_cic(2:0)
Sets syncing (1 of 8 sources) for the CIC decimation moment.
7.2.7
DDC Compensating FIR Filter (CFIR)
The receive compensating FIR filter (CFIR) decimates the output of the CIC filter by a fixed factor of two.
Filter coefficient size, input data size, and output data size are 18 bits. The CFIR length can be
programmed. This permits turning off taps and saving power if shorter filters are appropriate (the CFIR
power dissipation is proportional to its length).
The filter is organized in two partial filter blocks, each containing a data RAM, a coefficient RAM, and a
dual multiplier; and a common state machine and output accumulator.
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MPU Control
Interface
Read Data
Write Data
Write Pointer
COEF
RAM
32x18
COEF
RAM
32x18
mpu
ram_read
Reg
MUX
Complex
Output
Samples
Read Pointer
Complex
Input
Samples
DATA
RAM
64x36
DATA
RAM
64x36
Read
Pointer
Write
Pointer
crastarttap
Output
Sample
Valid
State Machine
B0124-01
Figure 7-24. DDC CFIR Block Diagram
The maximum CFIR filter length is a function of AFE8405 rxclk clock rate, output sample rate, and the
number of coefficient memory registers. The maximum number of taps is 64 and the minimum number is
14. Lengths between these limits can be specified in increments of 2.
Subject to the above minimum and maximum values, in the general case, the number of taps available is:
UMTS mode: 2 × (rxclk କtput sample rate)
CDMA mode if cic_decim is even (decimating by an odd number): 2 × (cic_decim)
CDMA mode if cic_decim is odd (decimating by an even number): 2 × (cic_decim + 1)
Example CFIR filter lengths available based on mode and rxclk frequency:
A
Mode
UMTS
rxclk
(MHz)
CIC
DECIMATION
cic_decim
CFIR
MAX LENGTH
CFIR
MIN LENGTH
10
9
40
14
UMTS
153.6
COMMENTS
UMTS
122.88
8
7
32
14
UMTS
CDMA
157.2864
32
31
64
14
CDMA2000
CDMA
122.88
25
24
48
14
CDMA2000
16
15
32
14
CDMA2000 low-power configuration
CDMA
CDMA
78.6432
30
29
60
14
TD-SCDMA
CDMA
153.6
81.92
16
15
32
14
TD-SCDMA
CDMA
76.8
15
14
28
14
TD-SCDMA low-power configuration
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A single set of programmed tap values is used for both the A-side and B-side DDC channels (two CDMA
channels) within a single DDC block when in CDMA mode.
After the CFIR filter performs the convolution, gain is applied at full precision, the signal is rounded, and
then hard limited. A shifter at the output of the filter then scales the data by either 2e-19 or 2e-18. The
gain through the filter is therefore:
Sum(CFIR coefficients) x 2 –(18 or 19)
Coefficients are organized in two groups of 32 words, each 18 bits wide. For fully utilized filters, the 64
coefficients are loaded 0 through 31 into the first RAM, and 32 through 63 into the second RAM. The
16-bit MSBs and 2-bit LSBs are written into the RAMs using different page register values. Shorter filters
require the coefficients be loaded into the 2 RAMs equally, starting from address 0.
For example, a CFIR coefficient set for a symmetric 58-tap TD-SCDMA CFIR is:
Taps
Coefficient
Taps
Coefficient
0 = 57
–13
15 = 42
–4,975
1 = 56
–20
16 = 41
–4,649
2 = 55
14
17 = 40
–232
3 = 54
101
18 = 39
6,581
4 = 53
184
19 = 38
11,266
5 = 52
133
20 = 37
8,917
6 = 51
–147
21 = 36
–1,957
7 = 50
–562
22 = 35
–16,736
8 = 49
–768
23 = 34
–25,469
9 = 48
–364
24 = 33
–17,599
10 = 47
719
25 = 32
11,560
11 = 46
1,905
26 = 31
56,455
12 = 45
2,126
27 = 30
102,215
13 = 44
567
28 = 29
131,071
14 = 43
–2,416
The first 29 coefficients are loaded into addresses 0 through 28 in the first coefficient RAM, and the
remaining 29 are loaded into addresses 0 through 28 in the second coefficient RAM. Loading the 18-bit
coefficients requires 2 writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 CFIR, the following control microprocessor interface
sequence would be used.
A
54
Step
Address
a[5:0]
Data
d[15:0]
Description
1
0x21
0x0480
Page register for DDC2 CFIR Coefficient RAM 0–31, LSBs.
2
0x00
0x0003
Lower 2 bits of coefficient 0
3
0x01
0x0000
Lower 2 bits of coefficient 1
4
0x02
0x0002
Lower 2 bits of coefficient 2
5
0x03
0x0001
Lower 2 bits of coefficient 3
6
0x04
0x0000
Lower 2 bits of coefficient 4
7
0x05
0x0001
Lower 2 bits of coefficient 5
8
0x06
0x0001
Lower 2 bits of coefficient 6
9
0x07
0x0002
Lower 2 bits of coefficient 7
10
0x08
0x0000
Lower 2 bits of coefficient 8
11
0x09
0x0000
Lower 2 bits of coefficient 9
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Step
Address
a[5:0]
Data
d[15:0]
12
0x0A
0x0003
Lower 2 bits of coefficient 10
13
0x0B
0x0001
Lower 2 bits of coefficient 11
14
0x0C
0x0002
Lower 2 bits of coefficient 12
15
0x0D
0x0003
Lower 2 bits of coefficient 13
16
0x0E
0x0000
Lower 2 bits of coefficient 14
17
0x0F
0x0001
Lower 2 bits of coefficient 15
18
0x10
0x0003
Lower 2 bits of coefficient 16
19
0x11
0x0000
Lower 2 bits of coefficient 17
20
0x12
0x0001
Lower 2 bits of coefficient 18
21
0x13
0x0002
Lower 2 bits of coefficient 19
22
0x14
0x0001
Lower 2 bits of coefficient 20
23
0x15
0x0003
Lower 2 bits of coefficient 21
24
0x16
0x0000
Lower 2 bits of coefficient 22
25
0x17
0x0003
Lower 2 bits of coefficient 23
26
0x18
0x0001
Lower 2 bits of coefficient 24
27
0x19
0x0000
Lower 2 bits of coefficient 25
28
0x1A
0x0003
Lower 2 bits of coefficient 26
29
0x1B
0x0003
Lower 2 bits of coefficient 27
30
0x1C
0x0003
Lower 2 bits of coefficient 28
31
0x1D
0x0000
Lower 2 bits of unused coefficient RAM location
32
0x1E
0x0000
Lower 2 bits of unused coefficient RAM location
33
0x1F
0x0000
Lower 2 bits of unused coefficient RAM location
34
0x21
0x04A0
Page register for DDC2 CFIR Coefficient RAM 32–63, LSBs.
35
0x00
0x0003
Lower 2 bits of coefficient 29
36
0x01
0x0003
Lower 2 bits of coefficient 30
37
0x02
0x0003
Lower 2 bits of coefficient 31
38
0x03
0x0000
Lower 2 bits of coefficient 32
39
0x04
0x0001
Lower 2 bits of coefficient 33
40
0x05
0x0003
Lower 2 bits of coefficient 34
41
0x06
0x0000
Lower 2 bits of coefficient 35
42
0x07
0x0003
Lower 2 bits of coefficient 36
43
0x08
0x0001
Lower 2 bits of coefficient 37
44
0x09
0x0002
Lower 2 bits of coefficient 38
45
0x0A
0x0001
Lower 2 bits of coefficient 39
46
0x0B
0x0000
Lower 2 bits of coefficient 40
47
0x0C
0x0003
Lower 2 bits of coefficient 41
48
0x0D
0x0001
Lower 2 bits of coefficient 42
49
0x0E
0x0000
Lower 2 bits of coefficient 43
50
0x0F
0x0003
Lower 2 bits of coefficient 44
51
0x10
0x0002
Lower 2 bits of coefficient 45
52
0x11
0x0001
Lower 2 bits of coefficient 46
53
0x12
0x0003
Lower 2 bits of coefficient 47
54
0x13
0x0000
Lower 2 bits of coefficient 48
55
0x14
0x0000
Lower 2 bits of coefficient 49
56
0x15
0x0002
Lower 2 bits of coefficient 50
57
0x16
0x0001
Lower 2 bits of coefficient 51
58
0x17
0x0001
Lower 2 bits of coefficient 52
59
0x18
0x0000
Lower 2 bits of coefficient 53
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Step
56
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Address
a[5:0]
Data
d[15:0]
Description
60
0x19
0x0001
Lower 2 bits of coefficient 54
61
0x1A
0x0002
Lower 2 bits of coefficient 55
62
0x1B
0x0000
Lower 2 bits of coefficient 56
63
0x1C
0x0003
Lower 2 bits of coefficient 57
64
0x1D
0x0000
Lower 2 bits of unused coefficient RAM location
65
0x1E
0x0000
Lower 2 bits of unused coefficient RAM location
66
0x1F
0x0000
Lower 2 bits of unused coefficient RAM location
67
0x21
0x04C0
Page register for DDC2 CFIR Coefficient RAM 0–31, MSBs.
68
0x00
0xFFFC
Upper 16 bits of coefficient 0
69
0x01
0xFFFB
Upper 16 bits of coefficient 1
70
0x02
0x0003
Upper 16 bits of coefficient 2
71
0x03
0x0019
Upper 16 bits of coefficient 3
72
0x04
0x002E
Upper 16 bits of coefficient 4
73
0x05
0x0021
Upper 16 bits of coefficient 5
74
0x06
0xFFDB
Upper 16 bits of coefficient 6
75
0x07
0xFF73
Upper 16 bits of coefficient 7
76
0x08
0xFF40
Upper 16 bits of coefficient 8
77
0x09
0xFFA5
Upper 16 bits of coefficient 9
78
0x0A
0x00B3
Upper 16 bits of coefficient 10
79
0x0B
0x01DC
Upper 16 bits of coefficient 11
80
0x0C
0x0213
Upper 16 bits of coefficient 12
81
0x0D
0x008D
Upper 16 bits of coefficient 13
82
0x0E
0xFDA4
Upper 16 bits of coefficient 14
83
0x0F
0xFB24
Upper 16 bits of coefficient 15
84
0x10
0xFB75
Upper 16 bits of coefficient 16
85
0x11
0xFFC6
Upper 16 bits of coefficient 17
86
0x12
0x066D
Upper 16 bits of coefficient 18
87
0x13
0x0B00
Upper 16 bits of coefficient 19
88
0x14
0x08B5
Upper 16 bits of coefficient 20
89
0x15
0xFE16
Upper 16 bits of coefficient 21
90
0x16
0xEFA8
Upper 16 bits of coefficient 22
91
0x17
0xE720
Upper 16 bits of coefficient 23
92
0x18
0xEED0
Upper 16 bits of coefficient 24
93
0x19
0x0B4A
Upper 16 bits of coefficient 25
94
0x1A
0x3721
Upper 16 bits of coefficient 26
95
0x1B
0x63D1
Upper 16 bits of coefficient 27
96
0x1C
0x7FFF
Upper 16 bits of coefficient 28
97
0x1D
0x0000
Upper 16 bits of unused coefficient RAM location
98
0x1E
0x0000
Upper 16 bits of unused coefficient RAM location
99
0x1F
0x0000
Upper 16 bits of unused coefficient RAM location
100
0x21
0x04E0
Page register for DDC2 CFIR Coefficient RAM 32–63, MSBs.
101
0x00
0x7FFF
Upper 16 bits of coefficient 29
102
0x01
0x63D1
Upper 16 bits of coefficient 30
103
0x02
0x3721
Upper 16 bits of coefficient 31
104
0x03
0x0B4A
Upper 16 bits of coefficient 32
105
0x04
0xEED0
Upper 16 bits of coefficient 33
106
0x05
0xE720
Upper 16 bits of coefficient 34
107
0x06
0xEFA8
Upper 16 bits of coefficient 35
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Step
Address
a[5:0]
Data
d[15:0]
Description
108
0x07
0xFE16
Upper 16 bits of coefficient 36
109
0x08
0x08B5
Upper 16 bits of coefficient 37
110
0x09
0x0B00
Upper 16 bits of coefficient 38
111
0x0A
0x066D
Upper 16 bits of coefficient 39
112
0x0B
0xFFC6
Upper 16 bits of coefficient 40
113
0x0C
0xFB75
Upper 16 bits of coefficient 41
114
0x0D
0xFB24
Upper 16 bits of coefficient 42
115
0x0E
0xFDA4
Upper 16 bits of coefficient 43
116
0x0F
0x008D
Upper 16 bits of coefficient 44
117
0x10
0x0213
Upper 16 bits of coefficient 45
118
0x11
0x01DC
Upper 16 bits of coefficient 46
119
0x12
0x00B3
Upper 16 bits of coefficient 47
120
0x13
0xFFA5
Upper 16 bits of coefficient 48
121
0x14
0xFF40
Upper 16 bits of coefficient 49
122
0x15
0xFF73
Upper 16 bits of coefficient 50
123
0x16
0xFFDB
Upper 16 bits of coefficient 51
124
0x17
0x0021
Upper 16 bits of coefficient 52
125
0x18
0x002E
Upper 16 bits of coefficient 53
126
0x19
0x0019
Upper 16 bits of coefficient 54
127
0x1A
0x0003
Upper 16 bits of coefficient 55
128
0x1B
0xFFFB
Upper 16 bits of coefficient 56
129
0x1C
0xFFFC
Upper 16 bits of coefficient 57
130
0x1D
0x0000
Upper 16 bits of unused coefficient RAM location
131
0x1E
0x0000
Upper 16 bits of unused coefficient RAM location
132
0x1F
0x0000
Upper 16 bits of unused coefficient RAM location
133
0x21
0x0500
Page register for DDC2 control registers 0–31
134
0x00
0x8EE0
DDC2 FIR_MODE register; cdma_mode enabled, 60-tap PFIR, 58-tap CFIR
135
0x01
0x2000
DDC2 PFIR gain = sum(taps) × 2–18 and CFIR gain = sum(taps) × 2–19
A
PROGRAMMING
VARIABLE
DESCRIPTION
crastarttap_cfir(4:0)
Number of DDC CFIR filter taps is 2 × gbl_ddc_writegbl_ddc_writegbl_ddc_write
mpu_ram_read
What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface. The AFE8405 signal
path is not operational when this bit is set, it is intended for debug purposes only.
cfir_gain
0 = 2e–19, 1 = 2e–18
The CFIR filter’s 18-bit coefficients are loaded in two 32-word memories.
Note: CFIR filter coefficients are shared between A and B channels of a DDC block in CDMA mode.
7.2.8
DDC Programmable FIR Filter (PFIR)
The receive programmable FIR filter (PFIR) provides final pulse shaping of the baseband signal data. It
does not perform any decimation. Filter coefficient size, input, and output data size is 18 bits. A special
strapped mode can be employed for UMTS where two adjacent DDCs (2k and 2k + 1, k = 0 to 3) can be
combined to yield a filter with twice the number of coefficients. This means the AFE8405 can support 4
UMTS DDC channels with double-length filter coefficients (up to 128 taps).
The filter is organized in four partial filter blocks, each containing a data RAM, a coefficient RAM and a
dual multiplier, a common state machine and output accumulator.
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MPU Control
Interface
Read Data
Write Data
Write Pointer
Filter Cell 1
Cell 2
Cell 3
Cell 4
COEF
RAM
16x18
mpu
ram_read
reg
MUX
Read Pointer
Complex
Output
Samples
From Adjacent DDC
(if double_tap="10")
Complex Input
Samples From cfir
(or Adjacent DDC if
double_tap="01")
To Adjacent DDC
(if double_tap="10")
DATA
RAM
32x36
Write
Pointer
Read
Pointer
crastarttap
Output
Sample
Valid
State Machine
B0125-01
Figure 7-25. DDC PFIR Block Diagram
The PFIR length is programmable. This permits turning off taps and saving power if short filters are
appropriate. The filter’s output data can be shifted over a range of 0 to 7 bits where it is then rounded and
hard-limited to 18 bits. The shift range results in a gain that ranges from 2e–19 to 2e–12.
The gain of the PFIR block is: sum(coefficients) × 2–shift, where shift ranges from 12 to 19.
The maximum PFIR filter length is a function of AFE8405 clock rate and output sample rate and is limited
by the number of coefficient memory registers. The maximum number of taps is 64 and the minimum
number is 32 (for both CDMA and UMTS). Lengths between these limits can be specified in increments of
4. For strapped UMTS with double length filters, the range of taps available is 64 to 128 in increments
of 8.
Subject to the above minimum and maximum values, the number of maximum taps available is:
UMTS mode: 4 × (rxclk ÷ output + sample rate)
Strapped UMTS mode: 8 × (rxclk ÷ output + sample rate)
CDMA mode: 2 × (rxclk ÷ output + sample rate)
PFIR coefficients and gain shift values are shared between both A and B CDMA channels in a DDC block.
Example PFIR filter lengths available based on mode and rxclk frequency:
58
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Mode
SLWS212 – OCTOBER 2008
rxclk
(MHz)
CIC
DECIMATIO
N
PFIR
MAX LENGTH
PFIR
MIN LENGTH
COMMENTS
10
64
32
UMTS, 1 to 6 DDC channels
UMTS
153.6
UMTS
122.88
8
64
32
UMTS, 1 to 6 DDC channels
UMTS
153.6
10
128
64
Strapped UMTS double length PFIR configuration; 1, 2, or 3 DDC
channels.
UMTS
122.88
8
128
64
Strapped UMTS double length PFIR configuration; 1, 2, or 3 DDC
channels
CDMA
157.2864
32
64
32
CDMA2000
CDMA
122.88
25
64
32
CDMA2000
16
64
32
CDMA2000 low power configuration
30
64
32
TD-SCDMA
CDMA
78.6432
CDMA
153.6
CDMA
81.92
16
64
32
TD-SCDMA
CDMA
76.8
15
60
32
TD-SCDMA low power configuration
Coefficients are organized in four groups of 16 words, each 18 bits wide. For fully utilized filters, the 64
coefficients are loaded 0 through 31 into the first and second RAMs, and 32 through 63 into the third and
fourth RAMs. The 16-bit MSBs and 2-bit LSBs are written into the RAMs using different page register
values. Shorter filters require the coefficients be loaded into the four RAMs equally, starting from address
0 and address 16.
For example, a CFIR coefficient set for a symmetric 60-tap TD-SCDMA PFIR is:
Taps
Coefficient
Taps
0 = 59
–2
15 = 44
Coefficient
420
1 = 58
1
16 = 43
–331
2 = 57
4
17 = 42
–319
3 = 56
–8
18 = 41
744
4 = 55
–2
19 = 40
–440
5 = 54
21
20 = 39
–1,005
6 = 53
–13
21 = 38
2,389
7 = 52
–28
22 = 37
514
8 = 51
46
23 = 36
–6,182
9 = 50
1
24 = 35
1,845
10 = 49
–85
25 = 34
12,959
11 = 48
96
26 = 33
–8,691
12 = 47
82
27 = 32
–27,246
13 = 46
–266
28 = 31
34,166
14 = 45
38
29 = 30
131,071
The first 15 coefficients are loaded into addresses 0 through 14 in the first coefficient RAM, the second
group of 15 are loaded into addresses 16 through 30 corresponding to the second coefficient RAM, the
third group of 15 are loaded into the third coefficient ram at addresses 0 through 14, and the fourth group
of 15 are loaded into addresses 16 through 30 in the fourth coefficient RAM. Loading the 18-bit
coefficients requires two writes per coefficient, one for the upper 16 bits and another for the lower 2 bits.
To program this coefficient set for the DDC2 PFIR, the following control microprocessor interface
sequence would be used.
A
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Step
Address
a[5:0]
Data
d[15:0]
Description
1
0x21
0x0400
Page register for DDC2 CFIR Coefficient RAMs 0–15 and 16–31, LSBs.
2
0x00
0x0002
Lower 2 bits of coefficient 0
3
0x01
0x0001
Lower 2 bits of coefficient 1
4
0x02
0x0000
Lower 2 bits of coefficient 2
5
0x03
0x0000
Lower 2 bits of coefficient 3
6
0x04
0x0002
Lower 2 bits of coefficient 4
7
0x05
0x0001
Lower 2 bits of coefficient 5
8
0x06
0x0003
Lower 2 bits of coefficient 6
9
0x07
0x0000
Lower 2 bits of coefficient 7
10
0x08
0x0002
Lower 2 bits of coefficient 8
11
0x09
0x0001
Lower 2 bits of coefficient 9
12
0x0A
0x0003
Lower 2 bits of coefficient 10
13
0x0B
0x0000
Lower 2 bits of coefficient 11
14
0x0C
0x0002
Lower 2 bits of coefficient 12
15
0x0D
0x0002
Lower 2 bits of coefficient 13
16
0x0E
0x0002
Lower 2 bits of coefficient 14
17
0x0F
0x0000
Lower 2 bits of unused coefficient RAM location
18
0x10
0x0000
Lower 2 bits of coefficient 15
19
0x11
0x0001
Lower 2 bits of coefficient 16
20
0x12
0x0001
Lower 2 bits of coefficient 17
21
0x13
0x0000
Lower 2 bits of coefficient 18
22
0x14
0x0000
Lower 2 bits of coefficient 19
23
0x15
0x0003
Lower 2 bits of coefficient 20
24
0x16
0x0001
Lower 2 bits of coefficient 21
25
0x17
0x0002
Lower 2 bits of coefficient 22
26
0x18
0x0002
Lower 2 bits of coefficient 23
27
0x19
0x0001
Lower 2 bits of coefficient 24
28
0x1A
0x0003
Lower 2 bits of coefficient 25
29
0x1B
0x0001
Lower 2 bits of coefficient 26
30
0x1C
0x0002
Lower 2 bits of coefficient 27
31
0x1D
0x0002
Lower 2 bits of coefficient 28
32
0x1E
0x0003
Lower 2 bits of coefficient 29
33
0x1F
0x0000
Lower 2 bits of unused coefficient RAM location
34
0x21
0x0420
Page register for DDC2 CFIR Coefficient RAMs 32–47 and 48–63, LSBs.
35
0x00
0x0003
Lower 2 bits of coefficient 30
36
0x01
0x0002
Lower 2 bits of coefficient 31
37
0x02
0x0002
Lower 2 bits of coefficient 32
38
0x03
0x0001
Lower 2 bits of coefficient 33
39
0x04
0x0003
Lower 2 bits of coefficient 34
40
0x05
0x0001
Lower 2 bits of coefficient 35
41
0x06
0x0002
Lower 2 bits of coefficient 36
42
0x07
0x0002
Lower 2 bits of coefficient 37
43
0x08
0x0001
Lower 2 bits of coefficient 38
44
0x09
0x0003
Lower 2 bits of coefficient 39
45
0x0A
0x0000
Lower 2 bits of coefficient 40
46
0x0B
0x0000
Lower 2 bits of coefficient 41
47
0x0C
0x0001
Lower 2 bits of coefficient 42
48
0x0D
0x0001
Lower 2 bits of coefficient 43
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Step
Address
a[5:0]
Data
d[15:0]
49
0x0E
0x0000
Lower 2 bits of coefficient 44
50
0x0F
0x0000
Lower 2 bits of unused coefficient RAM location
51
0x10
0x0002
Lower 2 bits of coefficient 45
52
0x11
0x0002
Lower 2 bits of coefficient 46
53
0x12
0x0002
Lower 2 bits of coefficient 47
54
0x13
0x0000
Lower 2 bits of coefficient 48
55
0x14
0x0003
Lower 2 bits of coefficient 49
56
0x15
0x0001
Lower 2 bits of coefficient 50
57
0x16
0x0002
Lower 2 bits of coefficient 51
58
0x17
0x0000
Lower 2 bits of coefficient 52
59
0x18
0x0003
Lower 2 bits of coefficient 53
60
0x19
0x0001
Lower 2 bits of coefficient 54
61
0x1A
0x0002
Lower 2 bits of coefficient 55
62
0x1B
0x0000
Lower 2 bits of coefficient 56
63
0x1C
0x0000
Lower 2 bits of coefficient 57
64
0x1D
0x0001
Lower 2 bits of coefficient 58
65
0x1E
0x0002
Lower 2 bits of coefficient 59
66
0x1F
0x0000
Lower 2 bits of unused coefficient RAM location
67
0x21
0x0440
Page register for DDC2 PFIR Coefficient RAMs 0–15 and 16–31, MSBs.
68
0x00
0xFFFF
Upper 16 bits of coefficient 0
69
0x01
0x0000
Upper 16 bits of coefficient 1
70
0x02
0x0001
Upper 16 bits of coefficient 2
71
0x03
0xFFFE
Upper 16 bits of coefficient 3
72
0x04
0xFFFF
Upper 16 bits of coefficient 4
73
0x05
0x0005
Upper 16 bits of coefficient 5
74
0x06
0xFFFC
Upper 16 bits of coefficient 6
75
0x07
0xFFF9
Upper 16 bits of coefficient 7
76
0x08
0x000B
Upper 16 bits of coefficient 8
77
0x09
0x0000
Upper 16 bits of coefficient 9
78
0x0A
0xFFEA
Upper 16 bits of coefficient 10
79
0x0B
0x0018
Upper 16 bits of coefficient 11
80
0x0C
0x0014
Upper 16 bits of coefficient 12
81
0x0D
0xFFBD
Upper 16 bits of coefficient 13
82
0x0E
0x0009
Upper 16 bits of coefficient 14
83
0x0F
0x0000
Upper 16 bits of unused coefficient RAM location
84
0x10
0x0069
Upper 16 bits of coefficient 15
85
0x11
0xFFAD
Upper 16 bits of coefficient 16
86
0x12
0x0FFB0
Upper 16 bits of coefficient 17
87
0x13
0x0B0A
Upper 16 bits of coefficient 18
88
0x14
0xFF92
Upper 16 bits of coefficient 19
89
0x15
0xFF04
Upper 16 bits of coefficient 20
90
0x16
0x0255
Upper 16 bits of coefficient 21
91
0x17
0x0080
Upper 16 bits of coefficient 22
92
0x18
0xF9F6
Upper 16 bits of coefficient 23
93
0x19
0x01CD
Upper 16 bits of coefficient 24
94
0x1A
0x0CA7
Upper 16 bits of coefficient 25
95
0x1B
0xF783
Upper 16 bits of coefficient 26
96
0x1C
0xE564
Upper 16 bits of coefficient 27
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Step
Address
a[5:0]
Data
d[15:0]
Description
97
0x1D
0x215D
Upper 16 bits of coefficient 28
98
0x1E
0x7FFF
Upper 16 bits of coefficient 29
99
0x1F
0x0000
Upper 16 bits of unused coefficient RAM location
100
0x21
0x0460
Page register for DDC2 PFIR Coefficient RAMS 32–47 and 48–63, MSBs.
101
0x00
0x7FFF
Upper 16 bits of coefficient 30
102
0x01
0x215D
Upper 16 bits of coefficient 31
103
0x02
0xE564
Upper 16 bits of coefficient 32
104
0x03
0xF783
Upper 16 bits of coefficient 33
105
0x04
0x0CA7
Upper 16 bits of coefficient 34
106
0x05
0x01CD
Upper 16 bits of coefficient 35
107
0x06
0xF9F6
Upper 16 bits of coefficient 36
108
0x07
0x0080
Upper 16 bits of coefficient 37
109
0x08
0x0255
Upper 16 bits of coefficient 38
110
0x09
0xFF04
Upper 16 bits of coefficient 39
111
0x0A
0xFF92
Upper 16 bits of coefficient 40
112
0x0B
0x00BA
Upper 16 bits of coefficient 41
113
0x0C
0xFFB0
Upper 16 bits of coefficient 42
114
0x0D
0xFFAD
Upper 16 bits of coefficient 43
115
0x0E
0x0069
Upper 16 bits of coefficient 44
116
0x0F
0x008D
Upper 16 bits of unused coefficient RAM location
117
0x10
0x0009
Upper 16 bits of coefficient 45
118
0x11
0xFFBD
Upper 16 bits of coefficient 46
119
0x12
0x0014
Upper 16 bits of coefficient 47
120
0x13
0x0018
Upper 16 bits of coefficient 48
121
0x14
0xFFEA
Upper 16 bits of coefficient 49
122
0x15
0x0000
Upper 16 bits of coefficient 50
123
0x16
0x000B
Upper 16 bits of coefficient 51
124
0x17
0xFFF9
Upper 16 bits of coefficient 52
125
0x18
0xFFFC
Upper 16 bits of coefficient 53
126
0x19
0x0005
Upper 16 bits of coefficient 54
127
0x1A
0xFFFF
Upper 16 bits of coefficient 55
128
0x1B
0xFFFE
Upper 16 bits of coefficient 56
129
0x1C
0x0001
Upper 16 bits of coefficient 57
130
0x1D
0x0000
Upper 16 bits of coefficient 58
131
0x1E
0xFFFF
Upper 16 bits of coefficient 59
132
0x1F
0x0000
Upper 16 bits of unused coefficient RAM location
133
0x21
0x0500
Page register for DDC2 control registers 0–31
134
0x00
0x8EE0
DDC2 FIR_MODE register; cdma_mode enabled, 60-tap PFIR, 58-tap CFIR
135
0x01
0x2000
DDC2 PFIR gain = sum(taps) × 2–18 and CFIR gain = sum(taps) × 2–19
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PROGRAMMING
VARIABLE
DESCRIPTION
crastarttap_pfir(4:0)
Number of DDC PFIR filter taps is 4 × (crastartap + 1)
For double length PFIR the number of taps is 8 × (crastartap + 1)
cdma_mode
When set, puts the CFIR & PFIR blocks in CDMA mode.
mpu_ram_read
What set, the PFIR and CFIR coefficient rams are readable via the MPU control interface.
The AFE8405 signal path is not operational when this bit is set, it is intended for debug purposes only.
pfir_gain(2:0)
Sets the gain of the PFIR filter.
The range is from 2e–19 to 2e–12; 000 = 2e–19 and 111 = 2e–12
double_tap(1:0)
When set, puts two adjacent DDC (2k and 2k + 1, k = 0 to 2) in double length (from 64- to 128-tap)
UMTS mode.
Set to 00 for normal mode.
In double-tap mode, data out of the last PFIR RAM in the main DDC (DDC0, DDC2, DDC4, or DDC6) is
sent to the adjacent secondary DDC (DDC1, DDC3, DDC5, or DDC7) PFIR as input, thus forming a
128-tap delay line. Data received from the adjacent PFIR summers is added into the main DDC’s PFIR
sum to form the final output.
When using double-tap mode, set double_tap to 10 for the main DDC, and to 01 for the secondary
DDC.
When in double-tap mode, the first half of the coefficients should be loaded into the main DDC (DDC0,
DDC2, DDC4, or DDC6), the remaining coefficients are loaded into the secondary DDC (DDC1, DDC3,
DDC5, or DDC7).
In double-tap mode, the main DDC must be turned on (ddc_ena = 1), and the secondary DDC must be
turned off (ddc_ena = 0).
The PFIR filter’s 18-bit coefficients are loaded in four 16-word memories.
Note: PFIR filter coefficients are shared between A and B channels of a DDC block when in CDMA mode.
7.2.9
DDC RMS Power Meter
36
18
I
37
55-Bit
Integrator
55-Bit
Register
36
18
Q
Transfer
Clear
Sync
RMS Power
8-Bit
Sync Delay
Counter
8
Delay
(in 8 Sample
Increments)
18-Bit
Interval
Counter
8
Interval
(in 8 Sample
Increments)
18-Bit
Integration
Counter
Interrupt
16
Integration
(in 8 Sample
Increments)
B0108-02
Figure 7-26. DDC RMS Power Meter Block Diagram
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Sync
Delay
Interrupt
Interrupt
Integration Time
Integration Time
Interval Time
Sync
Event
Integration
Start
Interrupt
Integration Time
Interval Time
Integration
Start
Integration
Start
T0116-01
Figure 7-27. DDC RMS Power Meter Timing
Each DDC channel includes an RMS power meter which is used to measure the total power within the
channel pass band.
The power meter samples the I and Q data stream after the PFIR filter. Both 18-bit I and Q data are
squared, summed, and then integrated over a period determined by a programmable counter. The
integration time is a 16-bit word which is programmed into the 18-bit counter.
There is a programmable 18-bit interval timer which sets the interval over which power measurements are
made. The timer counts in increments of 1024 samples. This allows the user to select intervals from 1 ×
1024 samples up to 256 × 1024 samples. For UMTS systems with sample rate rate at 7.68 MHz, the
power meter interval range is from 133 µs to 34.1 ms. For a CDMA system with the sample rate at 2.4576
MHz, the power meter interval range is 417 µs to 107 ms.
The power measurement process starts with a sync event. The integration starts at sync event + 3 chips +
sync_delay. The 8-bit delay register permits delays from 1 to 256 samples after sync. The integration
continues until the integration count is met. At that point, the result in the 55-bit accumulator is transferred
to the read holding register and an interrupt is generated indicating the power value is ready to read. The
interval counter continues until the programmed interval count is reached. When reached, the integration
counter and the interval counter start over again. Each time the integration count is reached, the 55 result
bits are again transferred to the read register, overwriting the previous value, and an interrupt is generated
signifying the data is ready to be read. Failure to read the data in time results in overwriting the previous
interval measurement.
Sync starts the process. Whenever a sync is received, all the counters are reset to zero no matter what
the status.
For UMTS, I and Q are calculated and the integrated power is read. When in CDMA mode, the power is
calculated for both the A (signal) path and the B (diversity) signal. As a result, there are two 55-bit words
representing the signal and diversity when in CDMA mode.
The power read is:
power = [ (I2 + Q2) × (N × 4 + 1) ], where N is the integration count.
A
PROGRAMMING
VARIABLE
DESCRIPTION
pmeter_result_a(54:0)
55-bit UMTS or CDMA mode-A channel-power measurement result
pmeter_result_b(54:0)
55-bit CDMA mode-B channel-power measurement result
pmeter_sqr_sum_ddc(15:0)
Integration (square and sum) count in increments of four samples.
pmeter_sync_delay_ddc(7:0)
Sync delay count in samples.
pmeter_interval_ddc(7:0)
The measurement interval in increments of 2048 samples. This value must be greater than SQR_SUM.
ssel_pmeter(2:0)
Sync source selection.
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PROGRAMMING
VARIABLE
DESCRIPTION
pmeter_sync_disable
Turns off the sync to the channel power meter. This can be used to individually turn off syncs to a
channel power meter while still having syncs to other power meters on the chip.
7.2.10 DDC AGC
I, Q
Limit
and
Round
18
12 Integer
and
12 Fractional
24
18
I, Q Outputs (Up to 25 Bits in AGC Bypass Mode)
threshold
zero mask
8
4
8
Magnitude
ucnt
8
2
Compare
Freeze
(From Register Bit)
29
Shift
4
dzro
4
dsat
4
2
Shift Select
5
S = +/-1, D = 4-Bit Shift
amin
16
29
Accumulate
dblw dabv
4
Under/Over
Detect
amax
16
clear
ocnt
4
24
Limit
Freeze
(From Sync Source)
Min Limit
Max Limit
Gain
Gain Adjust
24
B0126-01
Figure 7-28. DDC AGC Block Diagram
The AFE8405 automatic gain control circuit is shown in Figure 7-28. The basic operation of the circuit is to
multiply the 18-bit input data from the PFIR by a 24-bit gain word that represents a gain or attenuation in
the range of 0 to 4096. The gain format is mixed integer and fraction. The 12-bit integer allows the gain to
be boosted by up to factor of 4096 (72 dB). The 12-bit fractional part allows the gain to be adjusted up or
down in steps of one part in 4096, or approximately 0.002 dB. If the integer portion is zero, then the circuit
attenuates the signal. The gain-adjusted output data is saturated to full scale and then rounded to
between 4 and 18 bits in steps of one bit.
The AGC portion of the circuit is used to adjust the gain automatically so that the median magnitude of the
output data matches a target value, which is performed by comparing the magnitude of the output data
with a target threshold. If the magnitude is greater than the threshold, then the gain is decreased,
otherwise it is increased. The gain is adjusted as: G(t) = G + A(t), where G is the default user-supplied
gain value and A(t) is the time-varying adjustment. A(t) is updated as A(t) = A(t) + G(t) × S × 2–D, where S
= 1 if the magnitude is less than the threshold and is –1 if the magnitude exceeds the threshold, and
where D sets the adjustment step size. Note that the adjustment is a fraction of the current gain. This is
designed to set the AGC noise level to a known and acceptable level while keeping the AGC convergence
and tracking rate constant, independent of the gain level. The AGC noise is equal to 2–D, and the AGC
attack and decay rate is exponential, with a time constant equal to 2–D. Hence, the AGC increases or
decreases by 0.63 times G(t) in 2D updates.
If one assumes the data is random with a Gaussian distribution, which is valid for UMTS if more than 12
users with different codes have been overlaid, then the relationship between the RMS level and the
median is MEDIAN = 0.6745 × RMS, hence the threshold should be set to 0.6745 times the desired RMS
level.
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The gain step size can be set using four different values of D, each of which is a 4-bit integer. D can range
from 3 to 18. The user can specify values of D for different situations, i.e., when the signal magnitude is
below the user-specified threshold (Dblw), is above the threshold (Dabv), is consistently equal to zero
(Dzro) or is consistently equal to maximum (Dsat). It is important to note that D represents a gain step
size. Smaller values of D represent larger gain steps. The definition of equal to zero is any number when
masked by zero_mask is considered to be zero. This permits consistently very small amplitude signals to
have their gain increased rapidly.
Separate programmable D values allow the user to set different attack and decay time constants, and to
set shorter time constants for when the signal falls too low (equal to zero), or is too high (saturates). The
magnitude is considered to be consistently equal to zero by using a 4-bit counter that counts up every
time the 8-bit magnitude value is zero, and counts down otherwise. If the counter value exceeds a
user-specified threshold, then Dabv is used. Similarly the magnitude is considered too high by using a
counter that counts up when the magnitude is maximum, and counts down otherwise. If this counter
exceeds another user specified threshold, then Dsat is used.
As an example, if the AGC’s current gain at a particular moment in time is 5.123, and the magnitude of the
signal is greater than zero, but less than the user-programmed threshold. Step size Dblw is used to modify
the gain for the next sample. This represents the AGC attack profile. If Dblw is set to a value of 5, then the
gain for the next sample is 5.123 + 5.123 × 2–5 = 5.123 + 0.160 = 5.283. If the signal magnitude is still less
than the user-programmed threshold, then the gain for the next sample is 5.283 + 5.283 × 2–5 = 5.283 +
0.165 = 5.448. This continues until the signal magnitude exceeds the user-programmed threshold. When
the magnitude exceeds threshold (but is not saturated), then step size Dabv is automatically employed as
a size rather than Dblw.
The AGC converges linearly in dB with a step size of 40 log(1 + 2–D) when the error is greater than 12 dB
(i.e., the gain is off by 12 dB or more). Within 6 dB, the behavior is approximately an exponential decay
with a time constant of 2(D – 0.5) samples.
The suggested value of D is 5 or 6 when the error is greater than 12 dB (i.e., in the fast range detected by
consistently zero or saturated data). This gives a step size of 0.5 or 0.25 dB per sample.
The suggested value when the gain is off by less than 12 dB is D = 10, giving an exponential time
constant for delay of around 724 samples (63% decay every 724 samples).
Gain Error − dB
7
D=3
6
D=4
D=5
5
D=6
D=7
D=8
D=9
4
D=10
3
D=11
D=12
2
D=13
D=14
D=3
1
D=15
D=16
D = 18
D=17
D=18
0
1
10
100
1k
10k
100k
1M
Samples
G027
Figure 7-29. AGC Gain Error Over Time vs. D
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The AGC noise once the AGC has converged is a random error of amplitude 2–D relative to the RMS
signal level. This means that the error level is –6 × D dB below the signal RMS level. At D = 10 (–60 dB)
the error is negligible. The plot of Figure 7-29 shows the AGC response for vales of D ranging from 3 to
18. Error dB represents the distance the signal level is from the desired target threshold.
The AGC is also subject to user-specified upper and lower adjustment limits. The AGC stops incrementing
the gain if the adjustment exceeds Amax. It stops decrementing the gain if the adjustment is less than
Amin.
The input data is received with a valid flag that is high when a valid sample is received. For complex data,
the I and Q samples are on the same data input line and are not treated independently. An adjustment is
made for the magnitude of the I sample, and then another adjustment is made for the Q sample.
The AGC operates on UMTS and CDMA data. When in UMTS mode, the I and Q data are each used to
produce the AGC level. There is no separate I path gain and Q path gain. When in CDMA mode there are
separate gain levels for the signal and diversity I and Q data. The I and Q for A (or the signal) pair is
calculated and then the I' and Q' for the B (or diversity) pair is calculated.
There is a freeze mode for holding the accumulator at its current level. This puts the AGC in a hold mode
using the user-programmed gain along with the current gain_adjust value. To use only the
user-programmed gain value as the gain, set the freeze bit and then clear the accumulator. When using
the freeze bit, the full 25-bit output is sent out of the AGC block to support transferring up to 25 bits when
the AGC is disabled.
For TDD applications, freeze mode can be controlled using a sync source. This allows rxsync_a/b/c/d to
be assigned as an AGC hold signal to keep the AGC from responding during the transmit interval and run
during the receive interval. The freeze register bit is logically ORed with the freeze sync source.
The current AGC gain and state can also be optionally output with the DDCs I and Q output data by
setting the gain_mon variable. When in this mode, the top 14 bits of the current AGC gain word are
appended to the 8-bit AGC-modified I and Q output data.
A
Output
Bits(17:10)
I
I output data
Q
Q output data
Bits(9:4)
Bits(3:2)
Gain(23:16)
Gain(15:10)
Bits(1:0)
00
AGC State(1:0)
00
PROGRAMMING
VARIABLE
DESCRIPTION
agc_dblw(3:0)
Below threshold gain. Sets the value of gain step size Dblw (data x current gain below threshold). Ranges from
3 to 18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, … 18 = 1111
agc_dabv(3:0)
Above threshold gain. Sets the value of gain step size Dabv (data x current gain above threshold). Ranges
from 3 to 18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, … 18 = 1111
agc_dzro(3:0)
Zero signal gain. Sets the value of gain step size Dzro (data x current gain consistently zero). Ranges from 3 to
18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, … 18 = 1111
agc_dsat (3:0)
Saturated signal gain. Sets the value of gain step size Dsat (data x current gain consistently saturated).
Ranges from 3 to 18, and maps to a 4-bit field. For example: 3 = 0000, 4 = 0001, … 18 = 1111
agc_zero_msk(3:0)
Masks the lower 4 bits of signal data so as to be considered zeros.
agc_md(3:0)
AGC rounding. 0000 = 18 bits out, 1111 = 3 bits out.
agc_thresh(7:0)
AGC threshold. Compared with magnitude of 8 bits of input × gain.
agc_rnd_disable
AGC rounding is disabled when this bit is set.
agc_freeze
The AGC gain adjustment updates are disabled when set.
agc_clear
The AGC gain adjustment accumulator is cleared when set.
agc_gaina(23:0)
24-bit gain word for DDC A
agc_gainb(23:0)
24-bit gain word for DDC B (in CDMA mode)
agc_zero_cnt(3:0)
When the AGC output (input × gain) is zero-value this number of times, the shift value is changed to
agc_dzero.
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PROGRAMMING
VARIABLE
DESCRIPTION
agc_max_cnt(3:0)
When the AGC output (input × gain) is zero-value this number of times, the shift value is changed to agc_dsat.
agc_amax(15:0)
The maximum value that gain can be adjusted up to. Top 12 bits are integer, bottom 4 bits are fractional.
agc_amin(15:0)
The minimum value that gain can be adjusted down to. Top 12 bits are integer, bottom 4 bits are fractional.
gain_mon
When set, combines current AGC gain with I and Q data. The 18-bit output format thus becomes:
I portion: 8 bits of AGC’d I data - Gain(23:16) - 00
Q portion: 8 bits of AGC’d Q data - Gain(15:10) - Status(1:0) - 00.
Note: Bit 0 of Status, when set, indicates the data is saturated. Bit 1 of Status, when set, indicates the data is
zero.
ssel_agc_freeze(2:0)
Sync selection for freeze mode, 1 of 8 sources. This source is ORed with the freeze register bit.
ssel_gain(2:0)
Sync selection for the double buffered agc_gaina and agc_gainb register.
ssel_ddc_agc(2:0)
Sync selection used to initialize the AGC, primarily for test purposes.
7.2.11 DDC Output Interface
The baseband I/Q sample interface can be configured as serial or parallel formatted data. The serial
interface closely matches the GC5316-style interface. The parallel interface is provided to interface directly
to the TMS320TCI110 when delayed antenna streams used to implement channel estimation buffering
and/or transport format combination indicator (TFCI) buffering are not required.
The DDC output data is 2s-complement format.
7.2.11.1 Serial Output Interface
Serial Outputs
sync
clkdiv
Frame
Strobe
Delay
4
2
DDC Block
1 UMTS Mode Channel or
2 CDMA Mode Channels
CDMA
UMTS
rxout_X_a
I ch A
I msb
Double Length
PFIR UMTS
I msb
rxout_X_b
I ch B
I msb-1
I msb-1
rxout_X_c
Q ch A
Q msb
I msb-2
rxout_X_d
Q ch B
Q msb-1
I msb-3
rx_sync_out_X
Q msb
Four Outputs From
Adjacent DDC Block
Q msb-1
Q msb-2
Q msb-3
B0127-01
Figure 7-30. Serial Output Block Diagram and Output Pins for Each DDC Filter Mode
Each DDC block can be assigned four serial output data pins. These pins are used to transfer
downconverted I/Q baseband data out of the AFE8405 for subsequent processing. The usage of these
pins changes depending on how the DDC block is configured.
When the block is configured for two CDMA channels, a pair of serial data pins provides separate I and Q
data output for the two DDC channels. Word size is selectable from 4 to 25 bits with the most-significant
bit first.
When the DDC block is configured for a single UMTS channel, even and odd I and Q data drive the four
serial pins separately, most-significant bit first.
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Four serial pins each for I and Q data can be optionally employed (instead of two for I and two for Q) at
half the output rate. This would most likely be used when two DDC channels (2k and 2k + 1, k = 0 to 5)
are combined to support double-length PFIR filtering (a channel is sacrificed). Formatting for I data is then:
Imsb, Imsb-1, Imsb-2, Imsb-3. Q data formatting is: Qmsb, Qmsb-1, Qmsb-2, Qmsb-3.
The frame strobe signal provided on the rx_sync_out_X pins can be programmed to arrive from 0 to 3 bit
clocks early via a 2-bit control parameter. The frame interval can be programmed from 1 to 63 bits. A
programmable 4-bit clock divider circuit is used to specify the serial bit rate. The clock divider circuit is
synchronized using a sync block discussed later in this document.
Programming the serial port clock divider requires some thought and depends upon the channel's overall
decimation ratio, frame sync interval, number of output bits, and CDMA-UMTS mode.
In general:
the serial clock divide ratio ‫ נ‬the frame sync interval = the total receive decimation
The relationship between the number of serial bits output, clock divide ratio, and overall decimation ratio
is:
CDMA: [overall decimation ‫(נ‬pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) ≥ pser_recv_bits + 1
UMTS: 2 ‫[נ‬overall decimation ‫(נ‬pser_recv_8pin + 1) ] / (pser_recv_clkdiv + 1) ≥ pser_recv_bits + 1
where overall decimation = CIC DECIMATION × CFIR DECIMATION.
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The serial interface samples the PFIR output each time the transfer
interval defined by these two settings has completed. The decimation moment can be controlled using the
rxsync_X input signal selected as the sync source for the serial interface.
The timing diagram in Figure 7-31 shows the DDC serial output timing.
tsetup
thold
tpd
rxclk
rxsync_X
rxsync_X Can be a Pulse or Level - Interface Will Generate Periodic Frame Strobes Using Programmed Frame Sync Interval
rxsync_out_X
Programmed Bit Time
(2 rxclk Cycles for This Example)
3 rxclk + 1 Programmed Bit Time
rxout_X_Y
MSB
T0117-01
Figure 7-31. Serial Output Interface Timing Diagram
PROGRAMMING
VARIABLE
DESCRIPTION
pser_recv_fsinvl(6:0)
Frame sync interval in bits
pser_recv_bits(4:0)
Number of data output bits – 1. e.g., 10001 = 18 bits
pser_recv_clkdiv(3:0)
Receive serial interface clock divider rate – 1.
0 = rcclk, 15 = rxclk/16
pser_recv_8pin
When set, configures the serial out pins for 4I and 4Q in UMTS mode. When cleared, the mode is 2I
and 2Q. Used in conjunction with pser_recv_alt.
pser_recv_alt
When set, outputs Q data from adjacent DDC channel.
pser_recv_fsdel(1:0)
Number of bit clocks the frame sync is output early with respect to serial data.
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PROGRAMMING
VARIABLE
DESCRIPTION
ssel_serial(2:0)
Sync source selection, 1 of 8.
3-state(6:3)
3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in the high-impedance state when
the 3-state register bits are set.
7.2.11.2 Parallel Output Interface
DDC7
DDC6
DDC5
rx_sync_out_6
par_sync_out
rxclk_out
rxclk_out
rxout_7_d
rxout_7_c
rxout_7_b
I(15)
I(14)
I(13)
rxout_4_b
rxout_4_a
I(1)
I(0)
rxout_3_d
rxout_3_c
rxout_3_b
Q(15)
Q(14)
Q(13)
rxout_0_b
rxout_0_a
Q(1)
Q(0)
DDC4
Output
Format
DDC3
Parallel I/Q
DDC2
DDC1
DDC0
B0128-01
Figure 7-32. Parallel Output Interface Block Diagram and Output Pins
When a parallel I/Q interface is required, a 32-bit time-division-multiplexed output mode can be selected
using the rxout_X_X pins. This interface is provided for direct connection to the TMS320TCI110 receive
chip-rate ASSP when delayed antenna streams are not required. The output sample rate, rxclk_out clock
polarity, par_sync_out position and number of channels to be output are all programmable.
rxclk_out
par_sync_out
Parallel I/Q
IQ DDC0
IQ DDC1
IQ DDC2
IQ DDC3
IQ DDC4
IQ DDC5
IQ DDC6
IQ DDC7
T0118-01
Figure 7-33. Parallel Output Interface Timing Diagram
The DDC channel serial interface synchronization source selections should all be programmed to the
same value when using this parallel output interface (each DDC channel ssel_serial(2:0) in the SYNC_0
register should be programmed to the same rxsync_A/B/C/D value).
Decimation by 2 in the output interface can be achieved by setting the frame strobe interval and clock
divider to 1/2 the PFIR output rate. The parallel interface samples the PFIR outputs each time the transfer
interval defined by these two settings has completed.
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PROGRAMMING
VARIABLE
DESCRIPTION
par_recv_fsinvl(6:0)
rx_sync_out (frame strobe) sync interval. 0 is 1 rxclk cycle and 127 is 128 rxclk cycles.
par_recv_clkdiv(6:0)
rxclk_out cycles per IQ channel sample; 1 is full rate, 2 is rxclk/2, etc.
par_recv_chan(3:0)
Number channels to be output. 0 is 1 channel, and 15 is 16 channels.
par_recv_sync_del(6:0)
Delays the DDC0 pser sync source to establish the timing of IQ DDC0. Increasing the value delays the
par_sync_out location.
par_recv_syncout_del(3:0)
Delays the rx_sync_out position with respect to IQ DDC0. Setting to 0 moves the rx_sync_out pulse one
rxclk_out cycle before the IQ DDC0 word, setting to 1 places it as shown above, lined up with IQ DDC0,
etc.
par_recv_rxclk_pol
rxclk_out polarity. Outputs data on falling edges when cleared, rising edges when set.
par_recv_sync_pol
Parallel interface par_sync_out polarity. 0 is active-low, 1 for active-high
par_recv_ena
Parallel TCI110 style interface enabled when set, serial interface enabled when cleared.
ssel_serial(2:0)
DDC channel serial interface sync source selection. All DDCs should be programmed to the same sync
source when using this parallel output interface.
gain_mon
When set, the parallel output data includes 8b I at I(15:8), 8b Q at Q(15:8), 14b AGC gain at I(7:0) and
Q(7:2) and 2b AGC state at Q(1:0).
3-state(6:3)
3-state controls for the rx_sync_out_X and rxout_X_X pins. Pins are in the high-impedance state when
the 3-state register bits are set.
7.2.12 DDC Checksum Generator
The checksum generator is used in conjunction with the input test signal generator to implement a self-test
capability.
sync
rxclk
rxout_X_a
rxout_X_b
rxout_X_c
Checksum Read-Only
Results Updated on
Each Sync Event
Results
register
Checksum
Generator
rxout_X_d
Initialized On Sync Event to “0000 0000 0000 0010”
15
14
13 12
11
10
9
3
2 1
0
rxout_X_a
rxout_X_b
rxout_X_c
rxout_X_d
B0129-01
Figure 7-34. DDC Checksum Generator Block Diagram
The sync for the checksum generator is internally connected to the ddc_counter output.
A
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PROGRAMMING
VARIABLE
ddc_chk_sum(15:0)
72
DESCRIPTION
Read-only DDC channel checksum results
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8 AFE8405 GENERAL CONTROL
The AFE8405 is configured over a bidirectional 16-bit parallel-data microprocessor control port. The
control port permits access to the control registers which configure the chip. The control registers are
organized using a paged-access scheme using 6 address lines. Half of the 64 addresses (address 32
through address 63) represent global registers. The other 32 (address 0 through address 31) are paged
registers. This arrangement permits accessing a large number of control registers using relatively few
address lines.
Global registers (Address 32 through Address 63) are used to read/write AFE8405 parameters that are
global in nature and can benefit from single read/write operations. Examples include chip status, reset,
sync options, checksum ramp parameters, interrupt sources, interrupt masks, 3-state controls and the
page register.
Global address 33 is the page register. Writing a 16-bit value to this register sets the page to which future
write or read operations performed. These paged registers contain the actual parameters that configure
the chip and are accessed by writing/reading address 0 through address 31.
The global 3-state register can be used to place the output drivers on the AFE8405 in the high-impedance
state, and also includes the capability of disabling the internal rxclk of the chip.
A
PROGRAMMING
VARIABLE
DESCRIPTION
rxclk_ena
Enables the internal rxclk when set. When cleared, the AFE8405 ignores the rxclk input signal and hold
the internal clock low.
3-state(10:0)
Various output pins are forced into the high-impedance state when these bits are asserted. See the
GBL_3STATE register description for pin groups to bit assignments.
arst_func
When asserted, the internal data path is held reset. The control register programming is not affected.
8.1 Microprocessor Interface Control Data, Address, and Strobes
The microprocessor control bus consists of 16 bidirectional control data lines d[15:0], 6 address lines
a[5:0], a read enable line rd_n, a write enable line wr_n, and a chip enable line ce_n. These lines usually
interface to a microprocessor or DSP chip and are intended to look like a block of memory.
The interface can be operated in a three-pin control mode (using rd_n, wr_n and ce_n) or two-pin control
mode (using wr_n and ce_n with rd_n always low).
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8.1.1
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MPU Timing Diagrams
tREC
ce_n
wr_n
rd_n
tCSU
tHIZ
a[5:0]
tCDLY
tCOH
Valid Data
d[15:0]
T0119-01
Figure 8-1. Read Operation—Three-Pin Control Mode
tREC
ce_n
wr_n
tCSU
tHIZ
a[5:0]
tCDLY
tCOH
Valid Data
d[15:0]
T0120-01
Figure 8-2. Read Operation—Two-Pin Control Mode (rd_n Tied Low)
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tREC
ce_n
tCSPW
wr_n
tCSU
rd_n
a[5:0]
tCHD
Valid Data
d[15:0]
tEWCSU
T0121-01
Figure 8-3. Write Operation—Three-Pin Control Mode
tREC
ce_n
tCSPW
wr_n
tCSU
a[5:0]
tCHD
Valid Data
d[15:0]
tEWCSU
T0122-01
Figure 8-4. Write Operation—2-Pin Control Mode (rd_n Tied Low)
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8.2 Synchronization Signals
Various function blocks within the AFE8405 must be synchronized in order to realize predictable results.
The AFE8405 provides a flexible system where each function block that requires synchronization can be
independently synchronized from either device pins or from a software one-shot. The one-shot option is
setup and triggered through control registers. The four sync input pins, rxsync_a, rxsync_b, rxsync_c and
rxsync_d are qualified on the rxclk rising clock edge. Table 8-1 shows the different sync modes available.
Table 8-1. Different Sync Modes Available
SYNC SELECT CODE
RECEIVE SYNC SOURCE
000
rxsync_a
001
rxsync_b
010
rxsync_c
011
rxsync_d
100
ddc sync counter terminal count
101
ddc sync triggered by software one-shot (register bit)
110
0 (always off)
111
1 (always on)
Table 8-2 and Table 8-3 summarizes the blocks which have functions that can be synchronized using the
eight sync source options listed in Table 8-1.
Table 8-2. Receive Common Syncs
Sync Name
Purpose
sync_ddc_counter
Initializes the receive sync counter
sync_ddc
Initializes the receive ADC interface and clock generation circuits
sync_rxsync_out
Selects sync signal to be output on the rx_sync_out pin.
sync_adc_fifo
Initializes the input and output pointers in the ADC fifo circuits.
sync_tst_decim
Initializes the testbus decimation counter.
sync_recv_pmeterX
Initializes the rxin power meters. {X = 0, 1, 2, or 3}
sync_ragc_interval_X
Initializes the rxin receive AGC timers. {X = 0, 1, 2, or 3}
sync_ragc_freeze_X
rxin receive AGC freeze mode control. {X = 0, 1, 2, or 3}
sync_ragc_clear_X
Initializes the receive AGC error accumulator. {X = 0, 1, 2, or 3}
Table 8-3. DDC Channel Syncs
Sync Name
Purpose
sync_ddc_tadj
Selects zero stuff moment in the tadj fine-adjustment section
sync_ddc_tadj_reg
Updates the tadj output pointer register delay in the tadj coarse-adjustment section
sync_ddc_nco
Resets the NCO accumulator
sync_ddc_freq
Updates the NCO freq registers
sync_ddc_phase
Updates the NCO phase register
sync_ddc_dither
Initializes the NCO dither circuits
sync_ddc_cic
Selects the CIC decimation moment
sync_ddc_pmeter
Initializes the receive channel power meters
sync_ddc_gain
Updates the DDC channel AGC gain registers
sync_ddc_agc
Initializes the AGC accumulator
sync_ddc_agc_freeze
AGC freeze mode control
sync_ddc_serial
Initializes the receive serial interface
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A 32-bit general-purpose timer is included in the synchronization function. The timer loads the
user-programmed terminal count on a sync event and counts down to zero using rxclk. The duration of the
terminal-count pulse can also be programmed up to rxclk cycles. The timer output can be used as a sync
source for any other circuits requiring a sync if desired, and can also be routed to the rx_sync_out pin.
A
PROGRAMMING
VARIABLE
DESCRIPTION
ddc_counter(31:0)
32-bit programmable terminal count
ddc_counter_width(7:0)
8-bit programmable terminal-count pulse duration
ssel_ddc_counter(2:0)
Sync source selection for the ddc counter
ssel_rxsync_out(2:0)
Sync source selection for the rx_sync_out pin
3-state(0)
When set, the interrupt and rx_sync_out pins are placed in the high-impedance state.
rx_oneshot
Register bit used to generate the S/W oneshot signal for sync. This bit must be programmed from
cleared to set in order to generate a rising edge sync signal.
8.3 Interrupt Handling
When an AFE8405 block sets an interrupt, the interrupt pin goes active if the interrupt source is
masked. The microprocessor should then read the interrupt register to determine the source of
interrupt. The microprocessor then must write the interrupt register to clear the interrupt pin and
interrupt source. The interrupt register and interrupt mask are located in the global registers section of
control registers.
not
the
the
the
The AFE8405 has 16 interrupt sources; power meters in each of the eight DDC blocks, power meters in
the four receive input interface, and four rxin_X_ovr (adc overflow) input pins where X = {a, b, c, d}.
A
PROGRAMMING
VARIABLE
DESCRIPTION
pmeterX_im(7:0)
Channel pmeter interrupt mask bits. Interrupt source is masked when set.
recv_pmeterX_im(3:0)
Receive input power meter interrupt masks.
rxin_X_ovr_im
ADC overflow input pin interrupt masks.
pmeterX(7:0)
Channel pmeter interrupt status.
recv_pmeterX(3:0)
Receive input power meter interrupt status.
rxin_X_ovr
ADC overflow input pin interrupt status.
intr_clr
When asserted, holds all interrupt status bits cleared. The interrupt pin is inactive (always low) when this bit is
set. Intended for lab/debug use only
3-state(0)
When set, the interrupt and rx_sync_out pins are placed in the high-impedance state.
8.4 AFE8405 Programming
The AFE8405 includes over 2000 internal configuration registers and therefore implements a paged
addressing scheme. The register map includes a global control variables register address space that is
accessed directly when the a5 signal is high. This global control variables address space includes the
page register. All other registers are addressed using a combination of an address consisting of the
internal page register contents and the 6-bit external address: a5, a4, a3, a2, a1, and a0.
The page register is accessed when the 6-bit address a5:a0 is 0x21 (or 10 0001b).
A
Page Register
Contents in Hex
Address
Pin a5
Don’t care
1
Global control variables 0x00 through 0x1F
0x0000
0
DDC0 PFIR taps 0 through 31 coefficient lsbs (1:0)
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Page Register
Contents in Hex
Address
Pin a5
0x0020
0
DDC0 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0040
0
DDC0 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0060
0
DDC0 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0080
0
DDC0 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x00A0
0
DDC0 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x00C0
0
DDC0 CFIR taps 0 through 31 coefficient msbs (17:2)
0x00E0
0
DDC0 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0100
0
DDC0 control registers 0x00 through 0x1F
0x0120
0
DDC0 control registers 0x20 through 0x3F
0x0200
0
DDC1 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0220
0
DDC1 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0240
0
DDC1 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0260
0
DDC1 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0280
0
DDC1 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x02A0
0
DDC1 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x02C0
0
DDC1 CFIR taps 0 through 31 coefficient msbs (17:2)
0x02E0
0
DDC1 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0300
0
DDC1 control registers 0x00 through 0x1F
0x0320
0
DDC1 control registers 0x20 through 0x3F
0x0400
0
DDC2 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0420
0
DDC2 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0440
0
DDC2 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0460
0
DDC2 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0480
0
DDC2 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x04A0
0
DDC2 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x04C0
0
DDC2 CFIR taps 0 through 31 coefficient msbs (17:2)
0x04E0
0
DDC2 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0500
0
DDC2 control registers 0x00 through 0x1F
0x0520
0
DDC2 control registers 0x20 through 0x3F
0x0600
0
DDC3 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0620
0
DDC3 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0640
0
DDC3 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0660
0
DDC3 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0680
0
DDC3 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x06A0
0
DDC3 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x06C0
0
DDC3 CFIR taps 0 through 31 coefficient msbs (17:2)
0x06E0
0
DDC3 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0700
0
DDC3 control registers 0x00 through 0x1F
0x0720
0
DDC3 control registers 0x20 through 0x3F
0x0800
0
DDC4 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0820
0
DDC4 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0840
0
DDC4 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0860
0
DDC4 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0880
0
DDC4 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x08A0
0
DDC4 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x08C0
0
DDC4 CFIR taps 0 through 31 coefficient msbs (17:2)
AFE8405 GENERAL CONTROL
Registers Addressed With 5-Bit Address Space, Pins (a4:a0)
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Page Register
Contents in Hex
Address
Pin a5
Registers Addressed With 5-Bit Address Space, Pins (a4:a0)
0x08E0
0
DDC4 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0900
0
DDC4 control registers 0x00 through 0x1F
0x0920
0
DDC4 control registers 0x20 through 0x3F
0x0A00
0
DDC5 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0A20
0
DDC5 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0A40
0
DDC5 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0A60
0
DDC5 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0A80
0
DDC5 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x0AA0
0
DDC5 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x0AC0
0
DDC5 CFIR taps 0 through 31 coefficient msbs (17:2)
0x0AE0
0
DDC5 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0B00
0
DDC5 control registers 0x00 through 0x1F
0x0B20
0
DDC5 control registers 0x20 through 0x3F
0x0C00
0
DDC6 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0C20
0
DDC6 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0C40
0
DDC6 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0C60
0
DDC6 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0C80
0
DDC6 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x0CA0
0
DDC6 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x0CC0
0
DDC6 CFIR taps 0 through 31 coefficient msbs (17:2)
0x0CE0
0
DDC6 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0D00
0
DDC6 control registers 0x00 through 0x1F
0x0D20
0
DDC6 control registers 0x20 through 0x3F
0x0E00
0
DDC7 PFIR taps 0 through 31 coefficient lsbs (1:0)
0x0E20
0
DDC7 PFIR taps 32 through 63 coefficient lsbs (1:0)
0x0E40
0
DDC7 PFIR taps 0 through 31 coefficient msbs (17:2)
0x0E60
0
DDC7 PFIR taps 32 through 63 coefficient msbs (17:2)
0x0E80
0
DDC7 CFIR taps 0 through 31 coefficient lsbs (1:0)
0x0EA0
0
DDC7 CFIR taps 32 through 63 coefficient lsbs (1:0)
0x0EC0
0
DDC7 CFIR taps 0 through 31 coefficient msbs (17:2)
0x0EE0
0
DDC7 CFIR taps 32 through 63 coefficient msbs (17:2)
0x0F00
0
DDC7 control registers 0x00 through 0x1F
0x0F20
0
DDC7 control registers 0x20 through 0x3F
0x1000
0
Receive input AGC0 error RAM addresses 0 through 31
0x1020
0
Receive input AGC0 error RAM addresses 32 through 63
0x1040
0
Receive input AGC0 DVGA RAM addresses 0 through 31
0x1080
0
Receive input AGC0 gain RAM addresses 0 through 31
0x10A0
0
Receive input AGC0 gain RAM addresses 32 through 63
0x1100
0
Receive input AGC1 error RAM addresses 0 through 31
0x1120
0
Receive input AGC1 error RAM addresses 32 through 63
0x1140
0
Receive input AGC1 DVGA RAM addresses 0 through 31
0x1180
0
Receive input AGC1 gain RAM addresses 0 through 31
0x11A0
0
Receive input AGC1 gain RAM addresses 32 through 63
0x1400
0
Receive input AGC2 error RAM addresses 0 through 31
0x1420
0
Receive input AGC2 error RAM addresses 32 through 63
0x1440
0
Receive input AGC2 DVGA RAM addresses 0 through 31
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Page Register
Contents in Hex
Address
Pin a5
8.4.1
Registers Addressed With 5-Bit Address Space, Pins (a4:a0)
0x1480
0
Receive input AGC2 gain RAM addresses 0 through 31
0x14A0
0
Receive input AGC2 gain RAM addresses 32 through 63
0x1500
0
Receive input AGC3 error RAM addresses 0 through 31
0x1520
0
Receive input AGC3 error RAM addresses 32 through 63
0x1540
0
Receive input AGC3 DVGA RAM addresses 0 through 31
0x1580
0
Receive input AGC3 gain RAM addresses 0 through 31
0x15A0
0
Receive input AGC3 gain RAM addresses 32 through 63
0x1800
0
Receive input control registers 0x00 through 0x1F
0x1820
0
Receive input control registers 0x20 through 0x3F
0x1840
0
Receive input AGC control registers 0x00 through 0x1F
0x1860
0
Receive input AGC control registers 0x20 through 0x3F
Control Register Index
REGISTER NAME
Table 8-4. Control Register Index
SECTION
PMETER_RESULT_A_LSB
Section 8.4.5.32
SECTION
PMETER_RESULT_A_MID
Section 8.4.5.33
AGC_AMAX
Section 8.4.5.23
PMETER_RESULT_A_MSB
Section 8.4.5.34
AGC_AMIN
Section 8.4.5.24
PMETER_RESULT_B_LSB
Section 8.4.5.35
Section 8.4.5.17
PMETER_RESULT_B_MID
Section 8.4.5.36
AGC_CONFIG2
Section 8.4.5.18
PMETER_RESULT_B_MSB
Section 8.4.5.37
AGC_CONFIG3
Section 8.4.5.19
PMETER_RESULT_AB_UMSB
Section 8.4.5.38
Section 8.4.5.21
PSER_CONFIG1
Section 8.4.5.25
Section 8.4.5.22
PSER_CONFIG2
Section 8.4.5.26
AGC_GAINMSB
Section 8.4.5.20
RAGC_CONFIG0
Section 8.4.4.1
CIC_MODE1
Section 8.4.5.5
RAGC_CONFIG1
Section 8.4.4.2
Section 8.4.5.6
RAGC_CONFIG2
Section 8.4.4.3
CONFIG
Section 8.4.2.3
RAGC_CONFIG3
Section 8.4.4.4
CONFIG1
Section 8.4.5.15
RAGC0_ACCUM_LSB
Section 8.4.4.57
Section 8.4.5.16
RAGC0_ACCUM_MSB
Section 8.4.4.58
DDC_CHK_SUM
Section 8.4.5.31
RAGC0_CLIP_ERROR
Section 8.4.4.17
DDCCONFIG1
Section 8.4.5.27
RAGC0_CLIP_HITHRESH
Section 8.4.4.12
Section 8.4.5.2
RAGC0_CLIP_HITIMER
Section 8.4.4.14
Section 8.4.5.1
RAGC0_CLIP_LOTHRESH
Section 8.4.4.13
GBL_IMASK0
Section 8.4.2.8
RAGC0_CLIP_LOTIMER
Section 8.4.4.15
GBL_INTERRUPT0
Section 8.4.2.9
RAGC0_CLIP_SAMPLES
Section 8.4.4.16
Section 8.4.2.7
RAGC0_CONFIG0
Section 8.4.4.7
GBL_PAR_CONFIG0
Section 8.4.2.4
RAGC0_CONFIG1
Section 8.4.4.8
GBL_PAR_CONFIG1
Section 8.4.2.5
RAGC0_INTEGINVL_LSB
Section 8.4.4.5
Section 8.4.2.6
RAGC0_INTEGINVL_MSB
Section 8.4.4.6
NZ_PWR_MASK
Section 8.4.3.7
RAGC0_SD_SAMPLES
Section 8.4.4.11
PAGE
Section 8.4.2.2
RAGC0_SD_THRESH
Section 8.4.4.9
Section 8.4.5.13
RAGC0_SD_TIMER
Section 8.4.4.10
Section 8.4.5.14
RAGC1_ACCUM_LSB
Section 8.4.4.59
PHASEADD0A
Section 8.4.5.9
RAGC1_ACCUM_MSB
Section 8.4.4.60
PHASEADD0B
Section 8.4.5.11
RAGC1_CLIP_ERROR
Section 8.4.4.30
Section 8.4.5.10
RAGC1_CLIP_HITHRESH
Section 8.4.4.25
Section 8.4.5.12
RAGC1_CLIP_HITIMER
Section 8.4.4.27
REGISTER NAME
AGC_CONFIG1
AGC_GAINA
AGC_GAINB
CIC_MODE2
CONFIG2
FIR_GAIN
FIR_MODE
GBL_ONESHOT
GBL_3STATE
PHASE_OFFSETA
PHASE_OFFSETB
PHASEADD1A
PHASEADD1B
80
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Table 8-4. Control Register Index (continued)
REGISTER NAME
SECTION
RECV_PMETER0_CONFIG
Section 8.4.3.12
Section 8.4.4.26
RECV_PMETER0_LMSB
Section 8.4.3.28
RAGC1_CLIP_LOTIMER
Section 8.4.4.28
RECV_PMETER0_LSB
Section 8.4.3.26
RAGC1_CLIP_SAMPLES
Section 8.4.4.29
RECV_PMETER0_MID
Section 8.4.3.27
Section 8.4.4.20
RECV_PMETER0_SQR_SUM_LSB
Section 8.4.3.9
RAGC1_CONFIG1
Section 8.4.4.21
RECV_PMETER0_STRT_INTVL_LSB
Section 8.4.3.10
RAGC1_INTEGINVL_LSB
Section 8.4.4.18
RECV_PMETER0_SYNC_DLY
Section 8.4.3.11
Section 8.4.4.19
RECV_PMETER0_UMSB
Section 8.4.3.29
RAGC1_SD_SAMPLES
Section 8.4.4.24
RECV_PMETER1_CONFIG
Section 8.4.3.16
RAGC1_SD_THRESH
Section 8.4.4.22
RECV_PMETER1_LMSB
Section 8.4.3.32
Section 8.4.4.23
RECV_PMETER1_LSB
Section 8.4.3.30
Section 8.4.4.61
RECV_PMETER1_MID
Section 8.4.3.31
RAGC2_ACCUM_MSB
Section 8.4.4.62
RECV_PMETER1_SQR_SUM_LSB
Section 8.4.3.13
RAGC2_CLIP_ERROR
Section 8.4.4.43
RECV_PMETER1_STRT_INTVL_LSB
Section 8.4.3.14
Section 8.4.4.38
RECV_PMETER1_SYNC_DLY
Section 8.4.3.15
RAGC2_CLIP_HITIMER
Section 8.4.4.40
RECV_PMETER1_UMSB
Section 8.4.3.33
RAGC2_CLIP_LOTHRESH
Section 8.4.4.39
RECV_PMETER2_CONFIG
Section 8.4.3.20
Section 8.4.4.41
RECV_PMETER2_LMSB
Section 8.4.3.36
RAGC2_CLIP_SAMPLES
Section 8.4.4.42
RECV_PMETER2_LSB
Section 8.4.3.34
RAGC2_CONFIG0
Section 8.4.4.33
RECV_PMETER2_MID
Section 8.4.3.35
Section 8.4.4.34
RECV_PMETER2_SQR_SUM_LSB
Section 8.4.3.17
Section 8.4.4.31
RECV_PMETER2_STRT_INTVL_LSB
Section 8.4.3.18
RAGC2_INTEGINVL_MSB
Section 8.4.4.32
RECV_PMETER2_SYNC_DLY
Section 8.4.3.19
RAGC2_SD_SAMPLES
Section 8.4.4.37
RECV_PMETER2_UMSB
Section 8.4.3.37
Section 8.4.4.35
RECV_PMETER3_CONFIG
Section 8.4.3.24
RAGC2_SD_TIMER
Section 8.4.4.36
RECV_PMETER3_LMSB
Section 8.4.3.40
RAGC3_ACCUM_LSB
Section 8.4.4.63
RECV_PMETER3_LSB
Section 8.4.3.38
Section 8.4.4.64
RECV_PMETER3_MID
Section 8.4.3.39
RAGC3_CLIP_ERROR
Section 8.4.4.56
RECV_PMETER3_SQR_SUM_LSB
Section 8.4.3.21
RAGC3_CLIP_HITHRESH
Section 8.4.4.51
RECV_PMETER3_STRT_INTVL_LSB
Section 8.4.3.22
Section 8.4.4.53
RECV_PMETER3_SYNC_DLY
Section 8.4.3.23
Section 8.4.4.52
RECV_PMETER3_UMSB
Section 8.4.3.41
RAGC3_CLIP_LOTIMER
Section 8.4.4.54
RECV_SLF_TST_VALUE
Section 8.4.3.25
RAGC3_CLIP_SAMPLES
Section 8.4.4.55
SQR_SUM
Section 8.4.5.3
Section 8.4.4.46
SSEL_DDC_CNTR
Section 8.4.3.3
RAGC3_CONFIG1
Section 8.4.4.47
SSEL_RX_0
Section 8.4.3.4
RAGC3_INTEGINVL_LSB
Section 8.4.4.44
STRT_INTRVL
Section 8.4.5.4
Section 8.4.4.45
SYNC_0
Section 8.4.5.28
RAGC3_SD_SAMPLES
Section 8.4.4.50
SYNC_1
Section 8.4.5.29
RAGC3_SD_THRESH
Section 8.4.4.48
SYNC_2
Section 8.4.5.30
Section 8.4.4.49
SYNC_DDC_CNTR_LSB
Section 8.4.3.1
Section 8.4.3.5
SYNC_DDC_CNTR_MSB
Section 8.4.3.2
RECV_CONFIG1
Section 8.4.3.6
TADJC
Section 8.4.5.7
RECV_PMETER_SYNC
Section 8.4.3.8
TADJF
Section 8.4.5.8
VER
Section 8.4.2.1
REGISTER NAME
RAGC1_CLIP_LOTHRESH
RAGC1_CONFIG0
RAGC1_INTEGINVL_MSB
RAGC1_SD_TIMER
RAGC2_ACCUM_LSB
RAGC2_CLIP_HITHRESH
RAGC2_CLIP_LOTIMER
RAGC2_CONFIG1
RAGC2_INTEGINVL_LSB
RAGC2_SD_THRESH
RAGC3_ACCUM_MSB
RAGC3_CLIP_HITIMER
RAGC3_CLIP_LOTHRESH
RAGC3_CONFIG0
RAGC3_INTEGINVL_MSB
RAGC3_SD_TIMER
RECV_CONFIG0
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8.4.2
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Global Control Variables
These registers are accessed directly without page address extension; when pin a5 is high during a read
or write access, this block of 32 registers is accessed.
8.4.2.1 VER Register
Register name: VER
BIT 15
Unused
0
Address: 0x00
Read-only
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
BIT 8
Unused
0
Unused
0
Unused
0
Unused
0
VER3
0
VER2
0
VER1
*
VER0
*
BIT 7
Unused
0
VER(3:0):
82
BIT 0
A hardwired read-only register that returns the version of the chip
* A valid version code is 0010.
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8.4.2.2 PAGE Register
Register name: PAGE
BIT 15
Unused
0
Address: 0x01
Unused
0
Unused
0
0
W(2:0)
0
BIT 8
Y(2)
0
X
0
0
BIT 7
Y(1)
0
BIT 0
Y(0)
0
Zp
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
W(2:0):
Selects which dual-DDC block to address.
X:
The DDC modules are configured as dual DDCs; an even-numbered DDC and
odd-numbered DDC are contained in each dual-DDC module, the X bit selects which DDC
gets address. (DDC0/2/4/6=0, DDC1/3/5/7=1)
Y(2:0):
W(2:0)
X bit
Selected Block
000
0
DDC0
000
1
DDC1
001
0
DDC2
001
1
DDC3
010
0
DDC4
010
1
DDC5
011
0
DDC6
011
1
DDC7
100
0
Receive AGC0/1 RAMs
101
0
Receive AGC2/3 RAMs
110
0
Receive input interface
Within each major block, there are up to 8 different zones that can be addressed using the Y
bits.
Y(2:0)
DDC Zone
Receive Input Interface Zone
Receive AGC RAMs Zone
000
PFIR coeffient lower 2 bits
CHIPS control registers
RAGC0/2 ERRMAP
001
PFIR coeffient upper 16 bits
RAGC control registers
RAGC0/2 DVGAMAP
010
CFIR coeffient lower 2 bits
Not assigned
RAGC0/2 GAINMAP
011
CFIR coeffient upper 16 bits
Not assigned
Not assigned
100
Control registers
Not assigned
RAGC1/3 ERRMAP
101
Not assigned
Not assigned
RAGC1/3 DVGAMAP
110
Not assigned
Not assigned
RAGC1/3 GAINMAP
111
Not assigned
Not assigned
Not assigned
Zp:
The Zp bit is the MSB of the address word sent to the registers and RAMs. This bit can be
thought of as an upper/lower selector of the 64-word addressing.
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8.4.2.3 CONFIG Register
Register name: CONFIG
BIT 15
slf_ tst_ena
0
Address: 0x02
BIT 8
rduz_sens_ena
0
arst_ func
0
0
0
tst_rate_sel(4:0)
0
0
BIT 7
par_recv_ena
0
0
BIT 0
gbl_ ddc_write
0
intr_ clr
0
tst_select(3:0)
1
1
1
0
tst_ on
0
slf_tst_ena: Turns on the checksum LFSR for the receivers. They are located in the RECEIVE INPUT
INTERFACE and DDC blocks.
rduz_sens_ena: When enabled, adds noise to the LSBs of the ADC inputs.
arst_func:
When asserted, resets the functional portion of the circuits. The MPU registers are not reset
and retain their programmed value.
tst_rate_sel(4:0): Sets the rate of the output test data and clock. The length of the clock cycle is the
value in tst_rate_sel+1 multiplied by the RXCLK period. When the test bus source is set to
1000 (rxin_a and rxin_b FIFO outputs), tst_rate_sel(4:0) must be set to 0 for output.
Otherwise, it does not output a clock at the decimated test-bus rate.
par_recv_ena: When asserted, the rxout_*_* serial pins join to form a 32-bit parallel output using 32 pins
as a data bus, one pin as an output clock, and one pin as a sync. This is used to connect to
the TCI110 Chip rate processor from TI.
gbl_ddc_write: Factory use only. When asserted, the mpu writes are global. This means that DDC0/2/4/6
or DDC1/3/5/7 can be programmed simultaneously with the same values. This is an effort to
reduce the amount of time spent programming the device. A common setup can be used to
program DDC0/2/4/6, then DDC1/3/5/7. Afterwards, just individual writes to the registers
which differ between DDCs can be done. To use this feature, this bit must be asserted and
the DDC0/1 must be addressed. Any other DDC address does not work.
intr_clr:
When asserted, this bit forces all interrupts to be cleared. To allow the interrupts to be set
again, this bit must be programmed to zero. This does not stop blocks from generating
interrupts, but rather just keeps the interrupts from being reported.
tst_select(3:0): This selects which block the test output comes from:
tst_on:
84
tst_select(3:0)
Test Data Sent to Output
0000
DDC 0
0001
DDC 1
0010
DDC 2
0011
DDC 3
0100
DDC 4
0101
DDC 5
0110
DDC 6
0111
DDC 7
1000
rxin_a and rxin_b FIFO outputs
Others
None selected
When asserted, the testbus is active. The ADC input ports rxin_c(15:0), rxin_d(15:0),
dvga_c(5:0) and dvga_d(5:0) become the testbus output ports. When this bit is set, the
rxin_c(15:0) and rxin_d(15:0) ports become chip outputs. The dvga_c(5:0) and dvga_d(5:0)
ports are enabled separately using the GBL_3STATE register.
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8.4.2.4 GBL_PAR_CONFIG0 Register
Register name: GBL_PAR_CONFIG0
Address: 0x03
BIT 15
0
0
0
par_recv_sync_del(6:0)
0
0
0
0
BIT 7
BIT 0
par_recv_clkdiv(6:0)
0
BIT 8
tst_clk_pol
0
0
0
0
0
0
0
par_recv_
rxclk_pol
0
par_recv_sync_del(6:0): Delays the sync source from the DDC0 AGC output by (par_recv_sync_del+1)
rxclk cycles.
tst_clk_pol: Selects the polarity of the test clock output at dvga_c(1) when the test bus is enabled; 0 for
rising edge in the center of valid data, 1 for falling edge in the center of valid data. No effect
when tst_rate_sel is 0 0000.
par_recv_clkdiv(6:0): Selects the parallel interface output clock rate.
par_recv_rxclk_pol: Selects the polarity of the rxclk_out clock output; 0 for rising edge in the center of
valid data, 1 for falling edge in the center of valid data.
8.4.2.5 GBL_PAR_CONFIG1 Register
Register name: GBL_PAR_CONFIG1
Address: 0x04
BIT 15
0
BIT 8
par_recv_syncout_del(3:0)
0
0
0
0
par_recv_chan(3:0)
0
0
BIT 7
BIT 0
par_recv_fsinvl(6:0)
0
0
0
0
0
0
0
0
par_recv_
sync_pol
0
par_recv_syncout_del(3:0): Changes the rx_sync_out position with respect to IQ DDC0. Setting to 0
causes rx_sync_out to lead IQ DDC0 by 1 output sample, setting to 1 causes rx_sync_out to
line up with IQ DDC0, setting to 2 causes rx_sync_out to trail IQ DDC0 by 1 output sample,
etc.
par_recv_chan(3:0): Selects the number of channels to be output over the parallel interface, from 1 to 16
channels.
par_recv_fsinvl(6:0): Selects the number of rxclk cycles per parallel interface frame, from 1 to 128
cycles.
par_recv_sync_pol: Selects the polarity of the parallel interface sync pulse; 0 for active-low, 1 for
active-high.
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8.4.2.6 GBL_3STATE Register
Register name: GBL_3STATE
BIT 15
rxclk_ena
1
Unused
0
Address: 0x05
Unused
0
Unused
0
Unused
0
3-state(10)
1
3-state(9)
1
BIT 7
3-state(7)
1
BIT 8
3-state(8)
1
BIT 0
3-state(6)
1
rxclk_ena:
3-state(5)
1
3-state(4)
1
3-state(3)
1
3-state(2)
1
3-state(1)
1
3-state(0)
1
Master rxclk enable. When set, the chip’s rxclk is enabled, when cleared, rxclk is disabled.
All 3-states are ACTIVE-LOW so a 0 turns on the output and a 1 places it in the high-impedance
state.
3-state(10): This bit turns on the dvga_d outputs.
3-state(9):
This bit turns on the dvga_c outputs.
3-state(8):
This bit turns on the dvga_b outputs.
3-state(7):
This bit turns on the dvga_a outputs.
3-state(6):
This bit turns on the rx_sync_out_6/7 and the rxout_6/7_a/b/c/d outputs. (For parallel
interface use only)
3-state(5):
This bit turns on the rx_sync_out_4/5 and the rxout_4/5_a/b/c/d outputs.
3-state(4):
This bit turns on the rx_sync_out_2/3 and the rxout_2/3_a/b/c/d outputs.
3-state(3):
This bit turns on the rx_sync_out_0/1 and the rxout_0/1_a/b/c/d outputs.
3-state(2):
Unused
3-state(1):
rxclk_out
3-state(0):
interrupt and rx_sync_out.
8.4.2.7 GBL_ONESHOT Register
Register name: GBL_ONESHOT
BIT 15
Unused
0
Address: 0x06
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
BIT 8
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
BIT 7
rx_oneshot
0
BIT 0
rx_oneshot: When set, a one-shot pulse is sent to the receive blocks for syncing. This only works if the
blocks are programmed to use the one-shot as the sync source. To use the one-shot again,
it must be programmed to a 0 and then back to a 1.
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8.4.2.8 GBL_IMASK0 Register
Register name: GBL_IMASK0
BIT 15
pmeter7_im
0
Address: 0x07
pmeter6_im
0
pmeter5_im
0
pmeter4_im
0
pmeter3_im
0
pmeter2_im
0
pmeter1_im
0
BIT 7
recv_
pmeter0_im
0
BIT 8
pmeter0_im
0
BIT 0
recv_
pmeter1_im
0
recv_
pmeter2_im
0
recv_
pmeter3_im
0
rxin_a_ ovr_im
rxin_b_ ovr_im
rxin_c_ ovr_im
rxin_d_ ovr_im
0
0
0
0
pmeterX_im: When asserted, masks the interrupt for the particular DDC pmeter, X = {0, 1, 2, 3,4, 5, 6, 7}.
recv_pmeterX_im: When asserted, masks the interrupt for the particular receive input pmeter,
X = {0, 1, 2, 3}.
rxin_X_ovr_im: When asserted, masks the interrupt for the particular rxin overflow, X = {a, b, c, d}.
8.4.2.9 GBL_INTERRUPT0 Register
Register name: GBL_INTERRUPT0
BIT 15
pmeter7
0
Address: 0x08
pmeter6
0
pmeter5
0
pmeter4
0
pmeter3
0
pmeter2
0
pmeter1
0
BIT 8
pmeter0
0
recv_ pmeter1
0
recv_ pmeter2
0
recv_ pmeter3
0
rxin_a_ovr
0
rxin_b_ovr
0
rcin_c_ovr
0
rxin_d_ovr
0
BIT 7
recv_ pmeter0
0
BIT 0
pmeterX:
Asserted when an interrupt has been generated by this DDC pmeterX block,
X = {0, 1, 2, 3, 4, 5, 6, 7}
recv_pmeterX: Asserted when an interrupt has been generated by this receive input pmeter,
X = {0, 1, 2, 3}.
rxin_X_ovr: Asserted when a logic high input from the rxin_X_ovr pin occurs, X={a,b,c,d}.
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8.4.3
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Receive Input Interface Controls
8.4.3.1 SYNC_DDC_CNTR_LSB Register
Register name: SYNC_DDC_CNTR_LSB
Page: 0x1800
Address: 0x00
BIT 15
0
BIT 8
0
0
ddc_counter(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
ddc_counter(7:0)
0
0
0
0
0
8.4.3.2 SYNC_DDC_CNTR_MSB
Register name: SYNC_DDC_CNTR_MSB
Page: 0x1800
Address: 0x01
BIT 15
0
BIT 8
0
0
ddc_counter(31:24)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
ddc_counter(23:16)
0
0
0
0
0
ddc_counter(32:0): 32-bit interval timer common to all DDC sync inputs. This timer may be programmed
to any interval count, and each DDC synchronization input can select this counter as a
source. The value programmed into the counter is: (desired number – 1). The counter
increments on each RX clock rising edge.
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8.4.3.3 SSEL_DDC_CNTR Register
Register name: SSEL_DDC_CNTR
BIT 15
rxinab_mux
0
Page: 0x1800
Address: 0x02
BIT 8
rxincd_mux
0
Unused
0
Unused
0
Unused
0
ssel_ddc_counter(2:0)
0
0
BIT 7
0
0
BIT 0
0
ddc_counter_width(7:0)
0
0
0
0
0
0
rxinab_mux: When asserted, the rxin_a and rxin_b inputs are internally driven by the rxin_c and rxin_d
ports, respectively (factory-test use only).
rxincd_mux: When asserted, the rxin_c and rxin_d inputs are internally driven by the rxin_a and rxin_b
ports, respectively (factory-test use only).
ssel_ddc_counter(2:0): Selects the sync source for the DDC sync counter
ddc_counter_width(7:0): Sets the duration of the counter-generated sync pulse in RX clock cycles, from
1 to 256.
Sync sources are contained in this and many of the following registers. For all sync source selections:
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ssel_ddc_XXXXX(2:0)
Selected Sync Source
000
rxsyncA
001
rxsyncB
010
rxsyncC
011
rxsyncD
100
DDC sync counter
101
One-shot (register write triggered)
110
Always 0
111
Always 1
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8.4.3.4 SSEL_RX_0 Register
Register name: SSEL_RX_0
BIT 15
Unused
0
Page: 0x1800
Address: 0x03
BIT 8
0
ssel_adc_fifo(2:0)
0
0
Unused
0
0
ssel_tst_decim(2:0)
0
BIT 7
Unused
0
0
BIT 0
0
ssel_rxsync_out(2:0)
0
0
Unused
0
0
ssel_ddc(2:0)
0
0
ssel_adc_fifo(2:0): Selects the sync source for the adc FIFO blocks. Sync reinitializes the read and write
pointers of the FIFO.
ssel_tst_decim(2:0): Selects the sync source for the test bus decimator block.
ssel_rxsync_out(2:0): Selects the sync source for the RXSYNC_OUT pin.
ssel_ddc(2:0): Selects the sync source for the DDC data input multiplexer and mixer. Controls clock
generation in each DDC block (before the CIC input), which must match because the FIFO
output clock is common for all DDC blocks.
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8.4.3.5 RECV_CONFIG0 Register
Register name: RECV_CONFIG0
Page: 0x1800
Address: 0x04
BIT 15
BIT 8
rate_sel(1:0)
0
0
adc_
fifo_strap_ab
0
adc_
fifo_strap_cd
0
self_test_
const_ena
0
adc_
fifo_bypass
0
ragc_mpu_ram
_read
0
BIT 7
0
tst_ decim17
0
BIT 0
tst_decim_delay(3:0)
0
0
0
pmeter3_iq
0
pmeter2_iq
0
pmeter1_iq
0
pmeter0_iq
0
rate_sel(1:0): Tells RECV_CDRV the input rate. This is the rxin_a/b/c/d input rate and the rate that the
receive input interface block sends data to the DDCs.
rate_sel
Input clock rate
00
rxclk
01
rxclk/2
10
rxclk/4
11
rxclk/8
adc_fifo_strap_ab: When asserted, the input pointers of the rxin_a FIFO and rxin_b FIFO are hooked
together in lock-step configuration. This is used for maintaining FIFO delay consistency when
complex inputs are driven on rxin_a(I) and rxin_b(Q). rxin_a is the master.
adc_fifo_strap_cd: When asserted, the input pointers of the rxin_c FIFO and rxin_d FIFO are hooked
together in lock-step configuration. This is used for maintaining FIFO delay consistency when
complex inputs are driven on rxin_c(I) and rxin_d(Q). rxin_c is the master.
self_test_const_ena: When asserted, (with slf_tst_ena also asserted), a constant value is output by the
test and noise generator instead of the pseudorandom sequence. The constant value is
programmable.
adc_fifo_bypass: When asserted, the ADC FIFO circuits are bypassed. Input data is then clocked in
directly using the rxclk input. The ssel_ddc selection value controls the location of the
internally generated sample clock when this bit is asserted, where rate_sel is rxclk/2, rxclk/4,
or rxclk/8.
ragc_mpu_ram_read: When asserted, the RAMs in the RAGC blocks can be read. This bit should only
be set when reading the RAGC map RAMs via the MPU interface, and must be cleared for
proper RAGC operation.
tst_decim17: Must be cleared
tst_decim_delay(3:0): These bits set the delay from the occurrence of sync until the decimator samples.
In other words, the moment of the decimator is set by this delay value.
pmeter3_iq: When asserted, the pmeter3 block takes input from both rxin_c and rxin_d as a complex
sample pair. When de-asserted, only input from rxin_d is used for the power measurement.
pmeter2_iq: When asserted, the pmeter2 block takes input from both rxin_c and rxin_d as a complex
sample pair. When de-asserted, only input from rxin_c is used for the power measurement.
pmeter1_iq: When asserted, the pmeter1 block takes input from both rxin_a and rxin_b as a complex
sample pair. When de-asserted, only input from rxin_b is used for the power measurement.
pmeter0_iq: When asserted, the pmeter0 block takes input from both rxin_a and rxin_b as a complex
sample pair. When de-asserted, only input from rxin_a is used for the power measurement.
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8.4.3.6 RECV_CONFIG1 Register
Register name: RECV_CONFIG1
Page: 0x1800
Address: 0x05
BIT 15
0
msb_pos_d(2:0)
0
0
offset_bin_d
0
0
msb_pos_c(2:0)
0
0
BIT 7
0
BIT 8
offset_bin_c
0
BIT 0
msb_pos_b(2:0)
0
0
offset_bin_b
0
0
msb_pos_a(2:0)
0
0
offset_bin_a
0
msb_pos_X(2:0): Places the MSB of the input word from the ADC. The value programmed into these 3
bits is the MSB location in bit positions to the left of bit 16 of the input word. For example, if a
14-bit input word is driving rxin_a input and is aligned with rxin_a_0, then msb_pos_a is
programmed to 010 meaning the MSB is shifted down 2 bits from bit 16. X = {a, b, c, d}.
offset_bin_X: rxin_X input data is in 2s complement and not offset binary. If cleared, the input value is
converted to 2s complement using the MSB from the corresponding msb_pos_X value. X =
{a, b, c, d}. Note that the internal ADCs use 2s complement format, so offset_bin_A
and offset_bin_B must be cleared.
8.4.3.7 NZ_PWR_MASK Register
Register name: NZ_PWR_MASK
Page: 0x1800
Address: 0x06
BIT 15
0
BIT 8
0
0
nz_pwr_mask (15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
nz_pwr_mask (7:0)
0
0
0
0
0
nz_pwr_mask(15:0): Used with rduz_sens_ena, it selects the noise bits to be added to the ADC input
sample when asserted.
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8.4.3.8 RECV_PMETER_SYNC Register
Register name: RECV_PMETER_SYNC
Page: 0x1800
BIT 15
recv_pmeter0_
ena
0
recv_pmeter1_
ena
0
Address: 0x07
BIT 8
ssel_recv_pmeter0(2:0)
0
0
0
ssel_ recv_pmeter1(2:0)
0
0
BIT 7
recv_pmeter2_
ena
0
0
BIT 0
ssel_ recv_pmeter2(2:0)
0
0
0
recv_pmeter3_
ena
0
ssel_ recv_pmeter3(2:0)
0
0
0
recv_pmeter0_ena: Enables the receive input interface pmeter0 block when set
recv_pmeter1_ena: Enables the receive input interface pmeter1 block when set
recv_pmeter2_ena: Enables the receive input interface pmeter2 block when set
recv_pmeter3_ena: Enables the receive input interface pmeter3 block when set
ssel_ recv_pmeter0(2:0): Selects the sync source for the receive input interface pmeter0 block
ssel_ recv_pmeter1(2:0): Selects the sync source for the receive input interface pmeter1 block
ssel_ recv_pmeter2(2:0): Selects the sync source for the receive input interface pmeter2 block
ssel_ recv_pmeter3(2:0): Selects the sync source for the receive input interface pmeter3 block
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8.4.3.9 RECV_PMETER0_SQR_SUM_LSB Register
Register name: RECV_PMETER0_SQR_SUM_LSB
Page: 0x1800
Address: 0x08
BIT 15
0
BIT 8
0
0
recv_pmeter0_sqr_sum (15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
recv_pmeter0_sqr_sum (7:0)
0
0
0
0
0
recv_pmeter0_sqr_sum(15:0): The sqr_sum register controls the number of samples to accumulate for a
power measurement. Ia is (or Ia and Qa are) if complex mode is selected squared and
accumulated. Eight Ia samples (or eight pairs of Ia and Qa samples) equal one sqr_sum
count. The accumulation interval is initiated when sync is asserted and the programmed (8 ×
sync_delay + 2) samples have expired or when the interval start time is reached. When the
(8 × sqr_sum + 1) sample time is reached, the accumulated powers are made available for
MPU access and an interrupt is generated.
8.4.3.10 RECV_PMETER0_STRT_INTVL_LSB Register
Register name: RECV_PMETER0_STRT_INTVL_LSB
Page: 0x1800
Address: 0x09
BIT 15
0
BIT 8
0
0
recv_pmeter0_strt_intrvl (15:8)
0
0
0
recv_pmeter0_strt_intrvl (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter0_strt_intrvl(15:0): The start interval timer is the interval over which sqr_sum is restarted.
The timer value is (8 × strt_intrvl + 1) samples and must be larger than (8 × sqr_sum + 1)
samples. The interval start counter and RMS power accumulation is started at the sync pulse
after the programmed delay and every time the STRT_INTRVL counter reaches its limit.
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8.4.3.11 RECV_PMETER0_SYNC_DLY Register
Register name: RECV_PMETER0_SYNC_DLY
Page: 0x1800
Address: 0x0A
BIT 15
delay_line_0(5:0)
0
0
0
Unused
0
0
0
0
BIT 8
recv_pmeter0_
sync_delay(8)
0
BIT 7
0
BIT 0
0
0
recv_pmeter0_sync_delay (7:0)
0
0
0
0
0
delay_line_0(5:0): Pointer offset for the rxin_a path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
recv_pmeter0_sync_delay(8:0): Programmable start delay from sync, in eight-sample units. The actual
value is (8 × sync_delay + 2) samples.
8.4.3.12 RECV_PMETER0_CONFIG Register
Register name: RECV_PMETER0_CONFIG
Page: 0x1800
BIT 15
0
recv_pmeter0_sqr_sum(20:16)
0
0
0
0
Address: 0x0B
BIT 8
recv_pmeter0_strt_intrvl(20:18)
0
0
0
BIT 7
BIT 0
recv_pmeter0_strt_ intrvl(17:16)
0
0
Unused
0
Unused
0
Unused
0
0
ssel_delay_line_0(2:0)
0
0
recv_pmeter0_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter0_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units.
ssel_delay_line_0(2:0): Sync source selection for the 64-sample delay line pointer value update
8.4.3.13 RECV_PMETER1_SQR_SUM_LSB Register
Register name: RECV_PMETER1_SQR_SUM_LSB
Page: 0x1800
Address: 0x0C
BIT 15
0
BIT 8
0
0
recv_pmeter1_sqr_sum (15:8)
0
0
0
recv_pmeter1_sqr_sum (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter1_sqr_sum(15:0): Lower 16 bits of the sqr_sum interval timer, in eight-sample units.
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8.4.3.14 RECV_PMETER1_STRT_INTVL_LSB Register
Register name: RECV_PMETER1_STRT_INTVL_LSB
Page: 0x1800
Address: 0x0D
BIT 15
0
BIT 8
0
0
recv_pmeter1_strt_intrvl (15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
recv_pmeter1_strt_intrvl (7:0)
0
0
0
0
0
recv_pmeter1_strt_intrvl(15:0): Lower 16 bits of the interval timer, in eight-sample units.
8.4.3.15 RECV_PMETER1_SYNC_DLY Register
Register name: RECV_PMETER1_SYNC_DLY
Page: 0x1800
Address: 0x0E
BIT 15
delay_line_1(5:0)
0
0
0
0
Unused
0
0
0
BIT 7
0
BIT 8
recv_pmeter1_
sync_ delay(8)
0
BIT 0
0
0
recv_pmeter1_sync_delay (7:0)
0
0
0
0
0
delay_line_1(5:0): Pointer offset for the rxin_b path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
recv_pmeter1_sync_delay(8:0): Programmable start delay from sync, in eight-sample units
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8.4.3.16 RECV_PMETER1_CONFIG Register
Register name: RECV_PMETER1_CONFIG
Page: 0x1800
BIT 15
0
recv_pmeter1_sqr_sum(20:16)
0
0
0
0
Address: 0x0F
BIT 8
recv_pmeter1_strt_intrvl(20:18)
0
0
0
BIT 7
BIT 0
recv_pmeter1_strt_ intrvl(17:16)
0
0
Unused
0
Unused
0
Unused
0
0
ssel_delay_line_1(2:0)
0
0
recv_pmeter1_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter1_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units
ssel_delay_line_1(2:0): Sync source selection for the 64-sample delay-line pointer-value update
8.4.3.17 RECV_PMETER2_SQR_SUM_LSB Register
Register name: RECV_PMETER2_SQR_SUM_LSB
Page: 0x1800
Address: 0x10
BIT 15
0
BIT 8
0
0
recv_pmeter2_sqr_sum (15:8)
0
0
0
recv_pmeter2_sqr_sum (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter2_sqr_sum(15:0): Lower 16 bits of the sqr_sum interval timer, in eight-sample units
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8.4.3.18 RECV_PMETER2_STRT_INTVL_LSB Register
Register name: RECV_PMETER2_STRT_INTVL_LSB
Page: 0x1800
Address: 0x11
BIT 15
0
BIT 8
0
0
recv_pmeter2_strt_intrvl (15:8)
0
0
0
0
0
BIT 7
0
BIT 0
0
0
recv_pmeter2_strt_intrvl (7:0)
0
0
0
0
0
recv_pmeter2_strt_intrvl(15:0): Lower 16 bits of the interval timer, in eight-sample units
8.4.3.19 RECV_PMETER2_SYNC_DLY Register
Register name: RECV_PMETER2_SYNC_DLY
Page: 0x1800
Address: 0x12
BIT 15
delay_line_2(5:0)
0
0
0
0
Unused
0
0
0
BIT 8
recv_pmeter2_
sync_ delay(8)
0
BIT 7
0
BIT 0
0
0
recv_pmeter2_sync_delay (7:0)
0
0
0
0
0
delay_line_2(5:0): Pointer offset for the rxin_c path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
recv_pmeter2_sync_delay (8:0): Programmable start delay from sync, in eight-sample units
8.4.3.20 RECV_PMETER2_CONFIG Register
Register name: RECV_PMETER2_CONFIG
Page: 0x1800
BIT 15
0
recv_pmeter2_sqr_sum(20:16)
0
0
0
0
Address: 0x13
BIT 8
recv_pmeter2_strt_intrvl(20:18)
0
0
0
BIT 7
recv_pmeter2_strt_ intrvl(17:16)
0
0
BIT 0
Unused
0
Unused
0
Unused
0
0
ssel_delay_line_2(2:0)
0
0
recv_pmeter2_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter2_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units
ssel_delay_line_2(2:0): Sync source selection for the 64-sample delay-line pointer-value update
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8.4.3.21 RECV_PMETER3_SQR_SUM_LSB Register
Register name: RECV_PMETER3_SQR_SUM_LSB
Page: 0x1800
Address: 0x14
BIT 15
0
BIT 8
0
0
recv_pmeter3_sqr_sum (15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
recv_pmeter3_sqr_sum (7:0)
0
0
0
0
0
recv_pmeter3_sqr_sum(15:0): Lower 16 bits of the sqr_sum interval timer, in eight-sample units
8.4.3.22 RECV_PMETER3_STRT_INTVL_LSB Register
Register name: RECV_PMETER3_STRT_INTVL_LSB
Page: 0x1800
Address: 0x15
BIT 15
0
BIT 8
0
0
recv_pmeter3_strt_intrvl (15:8)
0
0
0
recv_pmeter3_strt_intrvl (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter3_strt_intrvl(15:0): Lower 16 bits of the interval timer, in eight-sample units
8.4.3.23 RECV_PMETER3_SYNC_DLY Register
Register name: RECV_PMETER3_SYNC_DLY
Page: 0x1800
Address: 0x16
BIT 15
delay_line_3(5:0)
0
0
0
0
Unused
0
0
0
BIT 7
0
BIT 8
recv_pme
ter3_sync_
delay(8)
0
BIT 0
0
0
recv_pmeter3_sync_delay (7:0)
0
0
0
0
0
delay_line_3(5:0): Pointer offset for the rxin_d path variable delay line. Larger values result in larger
pointer offsets and therefore more path delay.
recv_pmeter3_sync_delay(8:0): Programmable start delay from sync, in eight-sample units
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8.4.3.24 RECV_PMETER3_CONFIG Register
Register name: RECV_PMETER3_CONFIG
Page: 0x1800
Address: 0x17
BIT 15
0
recv_pmeter3_sqr_sum(20:16)
0
0
0
BIT 8
recv_pmeter3_strt_intrvl(20:18)
0
0
0
0
BIT 7
BIT 0
recv_pmeter3_strt_ intrvl(17:16)
0
0
Unused
0
Unused
0
Unused
0
0
ssel_delay_line_3(2:0)
0
0
recv_pmeter3_sqr_sum(20:16): MSBs of sqr_sum value, in eight-sample units
recv_pmeter3_strt_intrvl(20:16): MSBs of start interval value, in eight-sample units
ssel_delay_line_3(2:0): Sync source selection for the 64-sample delay-line pointer-value update
8.4.3.25 RECV_SLF_TST_VALUE Register
Register name: RECV_SLF_TST_VALUE
Page: 0x1800
Address: 0x18
BIT 15
0
BIT 8
0
0
self_test_constant(15:8)
0
0
0
self_test_constant(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
self_test_constant(15:0): 16-bit constant presented at the test and noise generator output when
enabled. Used for test and debug purposes.
8.4.3.26
RECV_PMETER0_LSB Register
Register name: RECV_PMETER0_LSB
Page: 0x1820
Address: 0x00
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter0(15:8)
0
0
0
recv_pmeter0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter0(15:0): Lower bits of the power meter 0 measurement
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8.4.3.27 RECV_PMETER0_MID Register
Register name: RECV_PMETER0_MID
Page: 0x1820
Address: 0x01
Read-only
BIT 15
0
BIT 8
0
recv_pmeter0(31:24)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
recv_pmeter0(23:16)
0
0
0
0
0
0
recv_pmeter0(31:16): Mid bits of the power meter 0 measurement
8.4.3.28 RECV_PMETER0_LMSB Register
Register name: RECV_PMETER0_LMSB
Page: 0x1820
Address: 0x02
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter0(47:40)
0
0
0
recv_pmeter0(39:32)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter0(47:32): Lower MSB bits of the power meter 0 measurement
8.4.3.29 RECV_PMETER0_UMSB Register
Register name: RECV_PMETER0_UMSB
BIT 15
Unused
0
Unused
0
Unused
0
Page: 0x1820
Unused
0
Unused
0
Address: 0x03
Unused
0
Read-only
BIT 8
recv_pmeter0(57:56)
0
0
BIT 7
0
BIT 0
0
0
recv_pmeter0(55:48)
0
0
0
0
0
recv_pmeter0(57:48): Upper MSB bits of the power meter 0 measurement
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8.4.3.30
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RECV_PMETER1_LSB Register
Register name: RECV_PMETER1_LSB
Page: 0x1820
Address: 0x04
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter1(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
recv_pmeter1(7:0)
0
0
0
0
0
recv_pmeter1(15:0): Lower bits of the power meter 1 measurement
8.4.3.31 RECV_PMETER1_MID Register
Register name: RECV_PMETER1_MID
Page: 0x1820
Address: 0x05
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter1(31:24)
0
0
0
recv_pmeter1(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter1(31:16): Mid bits of the power meter 1 measurement
8.4.3.32 RECV_PMETER1_LMSB Register
Register name: RECV_PMETER1_LMSB
Page: 0x1820
Address: 0x06
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter1(47:40)
0
0
0
recv_pmeter1(39:32)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter1(47:32): Lower MSB bits of the power meter 1 measurement
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8.4.3.33 RECV_PMETER1_UMSB Register
Register name: RECV_PMETER1_UMSB
BIT 15
Unused
0
Unused
0
Unused
0
Page: 0x1820
Unused
0
Address: 0x07
Unused
0
Unused
0
Read-only
BIT 8
recv_pmeter1(57:56)
0
0
BIT 7
0
BIT 0
0
0
recv_pmeter1(55:48)
0
0
0
0
0
recv_pmeter1(57:48): Upper MSB bits of the power meter 1 measurement
8.4.3.34 RECV_PMETER2_LSB Register
Register name: RECV_PMETER2_LSB
Page: 0x1820
Address: 0x08
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter2(15:8)
0
0
0
recv_pmeter2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter2(15:0): Lower bits of the power meter 2 measurement
8.4.3.35 RECV_PMETER2_MID Register
Register name: RECV_PMETER2_MID
Page: 0x1820
Address: 0x09
Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter2(31:24)
0
0
0
recv_pmeter2(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter2(31:16): Mid bits of the power meter 2 measurement
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8.4.3.36 RECV_PMETER2_LMSB Register
Register name: RECV_PMETER2_LMSB
Page: 0x1820
Address: 0x0A Read-only
BIT 15
0
BIT 8
0
recv_pmeter2(47:40)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
recv_pmeter2(39:32)
0
0
0
0
0
0
recv_pmeter2(47:32): Lower MSB bits of the power meter 2 measurement
8.4.3.37 RECV_PMETER2_UMSB Register
Register name: RECV_PMETER2_UMSB
BIT 15
Unused
0
Unused
0
Unused
0
Page: 0x1820
Unused
0
Unused
0
Address: 0x0B Read-only
Unused
0
BIT 8
recv_pmeter2(57:56)
0
0
BIT 7
0
BIT 0
0
0
recv_pmeter2(55:48)
0
0
0
0
0
recv_pmeter2(57:48): Upper MSB bits of the power meter 2 measurement
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8.4.3.38 RECV_PMETER3_LSB Register
Register name: RECV_PMETER3_LSB
Page: 0x1820
Address: 0x0C Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter3(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
recv_pmeter3(7:0)
0
0
0
0
0
recv_pmeter3(15:0): Lower bits of the power meter 3 measurement
8.4.3.39 RECV_PMETER3_MID Register
Register name: RECV_PMETER3_MID
Page: 0x1820
Address: 0x0D Read-only
BIT 15
0
BIT 8
0
0
recv_pmeter3(31:24)
0
0
0
recv_pmeter3(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter3(31:16): Mid bits of the power meter 3 measurement
8.4.3.40 RECV_PMETER3_LMSB Register
Register name: RECV_PMETER3_LMSB
Page: 0x1820
Address: 0x0E READ_ONLY
BIT 15
0
BIT 8
0
0
recv_pmeter3(47:40)
0
0
0
recv_pmeter3(39:32)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
recv_pmeter3(47:32): Lower MSB bits of the power meter 3 measurement
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8.4.3.41 RECV_PMETER3_UMSB Register
Register name: RECV_PMETER3_UMSB
BIT 15
Unused
0
Unused
0
0
Page: 0x1820
0
Address: 0x0F READ_ONLY
0
0
BIT 8
recv_pmeter3(57:56)
0
0
BIT 7
0
BIT 0
0
0
recv_pmeter3(55:48)
0
0
0
0
0
recv_pmeter3(57:48): Upper MSB bits of the power meter 3 measurement
8.4.4
Receive AGC Controls
8.4.4.1 RAGC_CONFIG0 Register
Register name: RAGC_CONFIG0
BIT 15
hp_ena_0
0
hp_ena_1
0
Page: 0x1840
hp_ena_2
0
hp_ena_3
0
Address: 0x00
sd_ena_0
0
sd_ena_1
0
sd_ena_2
0
BIT 8
sd_ena_3
0
Unused
0
Unused
0
Unused
0
Unused
0
BIT 7
ragc_ bypass_0 ragc_ bypass_1 ragc_ bypass_2 ragc_ bypass_3
0
0
0
0
BIT 0
hp_ena_X: Enables the high pass filter in receive AGC X when set.
sd_ena_X: Enables the Signal Detect block in receive AGC X when set.
ragc_bypass_X: Bypasses the receive AGC X block when set.
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8.4.4.2 RAGC_CONFIG1 Register
Register name: RAGC_CONFIG1
BIT 15
ragc_ freeze_0
0
ragc_ freeze_1
0
ragc_ freeze_2
0
ragc_ freeze_3
0
Page: 0x1840
Address: 0x01
ragc_ clear_0
0
ragc_ clear_1
0
ragc_ clear_2
0
BIT 8
ragc_ clear_3
0
BIT 7
BIT 0
complex01
0
complex23
0
0
ssel_ragc_interval_0(2:0)
0
0
0
ssel_ragc_interval_1(2:0)
0
0
ragc_freeze_X: Freezes the receive AGC block when set.
ragc_clear_X: Clears the loop error accumulator when set.
complex01: When set, receive AGC 0 uses complex input with the second sample stream coming from
receive AGC 1. The clip detect, high pass, and squarer from receive AGC 1 are used to
generate inputs for receive AGC 0.
complex23: When set, receive AGC 2 uses complex input with the second sample stream coming from
receive AGC 3. The clip detect, high pass, and squarer from receive AGC 3 are used to
generate inputs for receive AGC 2.
ssel_ragc_interval_0(2:0): Selects the sync source for receive AGC 0. After a programmed delay from
sync, the interval update timer is started.
ssel_ragc_interval_1(2:0): Selects the sync source for receive AGC 1. After a programmed delay from
sync, the interval update timer is started.
8.4.4.3 RAGC_CONFIG2 Register
Register name: RAGC_CONFIG2
Page: 0x1840
Address: 0x02
BIT 15
0
ssel_ragc_freeze_0(2:0)
0
0
0
ssel_ragc_freeze_1(2:0)
0
0
BIT 8
ssel_ragc_ freeze_2(2:1)
0
0
BIT 7
ssel_ragc_freez
e_2(0)
0
BIT 0
ssel_ragc_freeze_3(2:0)
0
0
ssel_ragc_interval_2(2:0)
Unused
0
0
0
0
0
ssel_ragc_freeze_X(2:0): Selects the sync source that freezes the receive AGC loop when asserted.
ssel_ragc_interval_2(2:0): Selects the sync source for receive AGC 2. After a programmed delay from
sync, the interval update timer is started.
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8.4.4.4 RAGC_CONFIG3 Register
Register name: RAGC_CONFIG3
Page: 0x1840
Address: 0x03
BIT 15
0
ssel_ragc_clear_0(2:0)
0
0
0
ssel_ragc_clear_1(2:0)
0
BIT 8
ssel_ragc_ clear_2(2:1)
0
0
0
BIT 7
ssel_ragc_
clear_2(0)
0
BIT 0
ssel_ragc_clear_3(2:0)
0
0
Unused
0
0
ssel_ragc_interval_3(2:0)
0
0
0
ssel_agc_clear_X(2:0: Controls the selection of the sync that clears the receive AGC error accumulator.
ssel_agc_interval_3(2:0): Selects the sync source for receive AGC 3. After a programmed delay from
sync, the interval update timer is started.
8.4.4.5 RAGC0_INTEGINVL_LSB Register
Register name: RAGC0_INTEGINVL_LSB
Page: 0x1840
Address: 0x04
BIT 15
0
BIT 8
0
0
integ_interval_0(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
integ_interval_0(7:0)
0
0
0
0
0
integ_interval_0(15:0): The 16 LSBs of the integration time for receive AGC 0.
8.4.4.6 RAGC0_INTEGINVL_MSB Register
Register name: RAGC0_INTEGINVL_MSB
Page: 0x1840
Address: 0x05
BIT 15
0
BIT 8
0
0
ragc_update_0(7:0)
0
0
0
integ_interval_0(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc_update_0(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_0(23:16): The eight MSBs of the integration time for receive AGC 0.
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8.4.4.7 RAGC0_CONFIG0 Register
Register name: RAGC0_CONFIG0
Page: 0x1840
Address: 0x06
BIT 15
0
BIT 8
0
0
ragc_sync_delay_0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
hp_corner_0(2:0)
0
0
0
0
acc_shift_0(4:0)
0
0
0
ragc_sync_delay_0(7:0): The input sync to the receive AGC block is delayed by this number of samples.
hp_corner_0(2:0): Sets the corner frequency of the high-pass filter. Larger values result in higher corner
frequencies
acc_shift_0(4:0): Selects the integrated power measurements result bits to be used as the error lookup
table address. A larger number means fewer samples must be integrated to achieve the
same result.
8.4.4.8
RAGC0_CONFIG1 Register
Register name: RAGC0_CONFIG1
Page: 0x1840
Address: 0x07
BIT 15
0
0
acc_offset_0(5:0)
0
0
BIT 8
err_shift_0(4:3)
0
0
0
0
0
delay_adj_0(4:0)
0
BIT 7
0
BIT 0
err_shift_0(2:0)
0
0
0
0
0
acc_offset_0(5:0): Constant subtracted from the integrated power measurement result before the error
lookup table.
err_shift_0(4:0): Adjusts the loop gain by controlling the amount of shifting applied to the error lookup
table output. Larger values result in higher gain.
delay_adj_0(4:0): Sets the delay difference, in samples, between the DVGA outputs and the value
applied to the sample multiplier.
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8.4.4.9 RAGC0_SD_THRESH Register
Register name: RAGC0_SD_THRESH
Page: 0x1840
Address: 0x08
BIT 15
0
BIT 8
0
0
sd_thresh_0(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
sd_thresh_0(7:0)
0
0
0
0
0
sd_thresh_0(15:0): This is the threshold used by the signal-detect block to determine if there is a signal
on the inputs. The comparison is done to the output of the squarer block, which is a 32-bit
word. Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared
value.
8.4.4.10 RAGC0_SD_TIMER Register
Register name: RAGC0_SD_TIMER
Page: 0x1840
Address: 0x09
BIT 15
0
BIT 8
0
0
sd _timer_0(15:8)
0
0
0
0
BIT 7
0
BIT 0
sd _timer_0(7:0)
0
0
0
0
0
0
0
0
sd_timer_0(15:0): Qualification window timer for loss of input signal.
8.4.4.11 RAGC0_SD_SAMPLES Register
Register name: RAGC0_SD_SAMPLES
Page: 0x1840
Address: 0x0A
BIT 15
0
BIT 8
0
0
sd_samples_0(15:8)
0
0
0
sd_samples_0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
sd_samples_0(15:0): Number of samples that must be below the sd_thresh_X within the sd_timer_X
timer value for the loss-of-signal condition to occur.
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8.4.4.12 RAGC0_CLIP_HITHRESH Register
Register name: RAGC0_CLIP_HITHRESH
Page: 0x1840
Address: 0x0B
BIT 15
0
BIT 8
0
0
clip_hi_thresh_0(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
clip_hi_thresh_0(7:0)
0
0
0
0
0
clip_hi_thresh_0(15:0): The high threshold value for clip detection
8.4.4.13 RAGC0_CLIP_LOTHRESH Register
Register name: RAGC0_CLIP_LOTHRESH
Page: 0x1840
Address: 0x0C
BIT 15
0
BIT 8
0
0
clip_lo_thresh_0(15:8)
0
0
0
clip_lo_thresh_0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_lo_thresh_0(15:0): The low threshold value for clip detection
8.4.4.14 RAGC0_CLIP_HITIMER Register
Register name: RAGC0_CLIP_HITIMER
Page: 0x1840
Address: 0x0D
BIT 15
0
BIT 8
0
0
clip_hi_timer_0(15:8)
0
0
0
clip_hi_timer_0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_timer_0(15:0): The high timer value in samples
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8.4.4.15 RAGC0_CLIP_LOTIMER Register
Register name: RAGC0_CLIP_LOTIMER
Page: 0x1840
Address: 0x0E
BIT 15
0
BIT 8
0
clip_lo_timer_0(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
clip_lo_timer_0(7:0)
0
0
0
0
0
0
clip_lo_timer_0(15:0): The low timer value in samples
8.4.4.16 RAGC0_CLIP_SAMPLES Register
Register name: RAGC0_CLIP_SAMPLES
Page: 0x1840
Address: 0x0F
BIT 15
0
BIT 8
0
0
clip_hi_samples_0(7:0)
0
0
0
clip_lo_samples_0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_samples_0(7:0): Number of samples above the high threshold within the clip high time to enable
the clip event
clip_lo_samples_0(7:0): Number of samples below the low threshold within the clip low time to disable
the clip event
8.4.4.17 RAGC0_CLIP_ERROR Register
Register name: RAGC0_CLIP_ERROR
Page: 0x1840
Address: 0x10
BIT 15
0
BIT 8
0
0
clip_error_0(15:8)
0
0
0
clip_error_0(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_error_0(15:0): This is the error value that is added into the loop accumulator when a clip is detected.
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8.4.4.18 RAGC1_INTEGINVL_LSB Register
Register name: RAGC1_INTEGINVL_LSB
Page: 0x1840
Address: 0x11
BIT 15
0
BIT 8
0
0
integ_interval_1(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
integ_interval_1(7:0)
0
0
0
0
0
integ_interval_1(15:0): The LSBs of the integration time for receive AGC 1
8.4.4.19 RAGC1_INTEGINVL_MSB Register
Register name: RAGC1_INTEGINVL_MSB
Page: 0x1840
Address: 0x12
BIT 15
0
BIT 8
0
0
ragc_update_1(7:0)
0
0
0
integ_interval_1(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc_update_1(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_1(23:16): The MSBs of the integration time for receive AGC 1
8.4.4.20 RAGC1_CONFIG0 Register
Register name: RAGC1_CONFIG0
Page: 0x1840
Address: 0x13
BIT 15
0
BIT 8
0
0
ragc_sync_delay_1(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
hp_corner_1(2:0)
0
0
0
0
acc_shift_1(4:0)
0
0
0
ragc_sync_delay_1(7:0): The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_1(2:0): This sets the corner frequency of the high-pass filter. Larger values result in higher
corner frequencies.
acc_shift_1(4:0): Selects the integrated power measurements result bits to be used as the error lookup
table address. A larger number means fewer samples must be integrated to achieve the
same result.
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8.4.4.21 RAGC1_CONFIG1 Register
Register name: RAGC1_CONFIG1
Page: 0x1840
Address: 0x14
BIT 15
0
0
acc_offset_1(5:0)
0
0
0
0
BIT 8
err_shift_1(4:3)
0
0
BIT 7
0
BIT 0
err_shift_1(2:0)
0
0
0
0
delay_adj_1(4:0)
0
0
0
acc_offset_1(5:0): Constant subtracted from the integrated power measurement result before the error
lookup table
err_shift_1(4:0): Controls the loop gain by left-shifting the error output. Larger values result in higher
gain.
delay_adj_1(4:0): Sets the delay difference, in samples, between the DVGA outputs and the value
applied to the sample multiplier.
8.4.4.22 RAGC1_SD_THRESH Register
Register name: RAGC1_SD_THRESH
Page: 0x1840
Address: 0x15
BIT 15
0
BIT 8
0
0
sd_thresh_1(15:8)
0
0
0
sd_thresh_1(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
sd_thresh_1(15:0): This is the threshold used by the signal-detect block to determine if there is signal on
the inputs. The comparison is done to the output of the squarer block, which is a 32-bit word.
Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared value.
8.4.4.23 RAGC1_SD_TIMER Register
Register name: RAGC1_SD_TIMER
Page: 0x1840
Address: 0x16
BIT 15
0
BIT 8
0
0
sd_timer_1(15:8)
0
0
0
0
BIT 7
0
BIT 0
sd_timer_1(7:0)
0
0
0
0
0
0
0
0
sd_timer_1(15:0): After the first no-signal sample occurs, this is the amount of samples that controls the
length of time to determine the loss-of-signal condition.
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8.4.4.24 RAGC1_SD_SAMPLES Register
Register name: RAGC1_SD_SAMPLES
Page: 0x1840
Address: 0x17
BIT 15
0
BIT 8
0
sd_samples_1(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
sd_samples_1(7:0)
0
0
0
0
0
0
sd_samples_1(15:0): Number of samples that must be below the sd_thresh_X threshold within the
sd_timer_X timer value for the loss-of-signal condition to occur.
8.4.4.25 RAGC1_CLIP_HITHRESH Register
Register name: RAGC1_CLIP_HITHRESH
Page: 0x1840
Address: 0x18
BIT 15
0
BIT 8
0
0
clip_hi_thresh_1(15:8)
0
0
0
clip_hi_thresh_1(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_thresh_1(15:0): The high threshold value for clip detection
8.4.4.26 RAGC1_CLIP_LOTHRESH Register
Register name: RAGC1_CLIP_LOTHRESH
Page: 0x1840
Address: 0x19
BIT 15
0
BIT 8
0
0
clip_lo_thresh_1(15:8)
0
0
0
clip_lo_thresh_1(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_lo_thresh_1(15:0): The low threshold value for clip detection
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8.4.4.27 RAGC1_CLIP_HITIMER Register
Register name: RAGC1_CLIP_HITIMER
Page: 0x1840
Address: 0x1A
BIT 15
0
BIT 8
0
clip_hi_timer_1(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
clip_hi_timer_1(7:0)
0
0
0
0
0
0
clip_hi_timer_1(15:0): The high timer value in samples
8.4.4.28 RAGC1_CLIP_LOTIMER Register
Register name: RAGC1_CLIP_LOTIMER
Page: 0x1840
Address: 0x1B
BIT 15
0
BIT 8
0
0
clip_lo_timer_1(15:8)
0
0
0
clip_lo_timer_1(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_lo_timer_1(15:0): The low timer value in samples
8.4.4.29 RAGC1_CLIP_SAMPLES Register
Register name: RAGC1_CLIP_SAMPLES
Page: 0x1840
Address: 0x1C
BIT 15
0
BIT 8
0
0
clip_hi_samples_1(7:0)
0
0
0
clip_lo_samples_1(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_samples_1(7:0): Number of samples above the high threshold within the clip high time to enable
the clip event.
clip_lo_samples_1(7:0): Number of samples below the low threshold within the clip low time to disable
the clip event.
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8.4.4.30 RAGC1_CLIP_ERROR Register
Register name: RAGC1_CLIP_ERROR
Page: 0x1840
Address: 0x1D
BIT 15
0
BIT 8
0
clip_error_1(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
clip_error_1(7:0)
0
0
0
0
0
0
clip_error_1(15:0): This is the error value that is added into the loop accumulator when a clip is detected.
8.4.4.31 RAGC2_INTEGINVL_LSB Register
Register name: RAGC2_INTEGINVL_LSB
Page: 0x1840
Address: 0x1E
BIT 15
0
BIT 8
0
0
integ_interval_2(15:8)
0
0
0
integ_interval_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
integ_interval_2(15:0): The LSBs of the integration time for receive AGC 2
8.4.4.32 RAGC2_INTEGINVL_MSB Register
Register name: RAGC2_INTEGINVL_MSB
Page: 0x1840
Address: 0x1F
BIT 15
0
BIT 8
0
0
ragc_update_2(7:0)
0
0
0
integ_interval_2(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc_update_2(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_2(23:16): The MSBs of the integration time for receive AGC 2
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8.4.4.33 RAGC2_CONFIG0 Register
Register name: RAGC2_CONFIG0
Page: 0x1860
Address: 0x00
BIT 15
0
BIT 8
0
0
ragc_sync_delay_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
hp_corner_2(2:0)
0
0
0
0
acc_shift_2(4:0)
0
0
0
ragc_sync_delay_2(7:0): The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_2(2:0): This sets the corner frequency of the high-pass filter. Larger values result in higher
corner frequencies.
acc_shift_2(4:0): Selects the integrated power measurements result bits to be used as the error lookup
table address. A larger number means fewer samples must be integrated to achieve the
same result.
8.4.4.34 RAGC2_CONFIG1 Register
Register name: RAGC2_CONFIG1
Page: 0x1860
Address: 0x01
BIT 15
0
0
acc_offset_2(5:0)
0
0
0
0
0
delay_adj_2(4:0)
0
BIT 8
err_shift_2(4:3)
0
0
BIT 7
0
BIT 0
err_shift_2(2:0)
0
0
0
0
0
acc_offset_2(5:0): Constant subtracted from the integrated power measurement result before the error
lookup table.
err_shift_2(4:0): Controls the loop gain by left-shifting the error output. Larger values result in higher
gain..
delay_adj_2(4:0): Sets the delay difference, in samples, between the DVGA outputs and the value
applied to the sample multiplier.
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8.4.4.35 RAGC2_SD_THRESH Register
Register name: RAGC2_SD_THRESH
Page: 0x1860
Address: 0x02
BIT 15
0
BIT 8
0
0
sd_thresh_2(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
sd_thresh_2(7:0)
0
0
0
0
0
sd_thresh_2(15:0): This is the threshold used by the signal-detect block to determine if there is signal on
the inputs. The comparison is done to the output of the squarer block, which is a 32-bit word.
Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared value.
8.4.4.36 RAGC2_SD_TIMER Register
Register name: RAGC2_SD_TIMER
Page: 0x1860
Address: 0x03
BIT 15
0
BIT 8
0
0
sd_timer_2(15:8)
0
0
0
0
BIT 7
0
BIT 0
sd_timer_2(7:0)
0
0
0
0
0
0
0
0
sd_timer_2(15:0): After the first no-signal sample occurs, this is the amount of samples that control the
length of time to determine the loss-of-signal condition.
8.4.4.37 RAGC2_SD_SAMPLES Register
Register name: RAGC2_SD_SAMPLES
Page: 0x1860
Address: 0x04
BIT 15
0
BIT 8
0
0
sd_samples_2(15:8)
0
0
0
sd_samples_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
sd_samples_2(15:0): Number of samples that must be below the sd_thresh_X threshold within the
sd_timer_X timer value for the loss-of-signal condition to occur.
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8.4.4.38 RAGC2_CLIP_HITHRESH Register
Register name: RAGC2_CLIP_HITHRESH
Page: 0x1860
Address: 0x05
BIT 15
0
BIT 8
0
0
clip_hi_thresh_2(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
clip_hi_thresh_2(7:0)
0
0
0
0
0
clip_hi_thresh_2(15:0): The high threshold value for clip detection
8.4.4.39 RAGC2_CLIP_LOTHRESH Register
Register name: RAGC2_CLIP_LOTHRESH
Page: 0x1860
Address: 0x06
BIT 15
0
BIT 8
0
0
clip_lo_thresh_2(15:8)
0
0
0
clip_lo_thresh_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_lo_thresh_2(15:0): The low threshold value for clip detection
8.4.4.40 RAGC2_CLIP_HITIMER Register
Register name: RAGC2_CLIP_HITIMER
Page: 0x1860
Address: 0x07
BIT 15
0
BIT 8
0
0
clip_hi_timer_2(15:8)
0
0
0
clip_hi_timer_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_timer_2(15:0): The high timer value in samples
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8.4.4.41 RAGC2_CLIP_LOTIMER Register
Register name: RAGC2_CLIP_LOTIMER
Page: 0x1860
Address: 0x08
BIT 15
0
BIT 8
0
clip_lo_timer_2(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
clip_lo_timer_2(7:0)
0
0
0
0
0
0
clip_lo_timer_2(15:0): The low timer value in samples
8.4.4.42 RAGC2_CLIP_SAMPLES Register
Register name: RAGC2_CLIP_SAMPLES
Page: 0x1860
Address: 0x09
BIT 15
0
BIT 8
0
0
clip_hi_samples_2(7:0)
0
0
0
clip_lo_samples_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_samples_2(7:0): Number of samples above the high threshold within the clip high time to enable
the clip event
clip_lo_samples_2(7:0): Number of samples below the low threshold within the clip low time to disable
the clip event
8.4.4.43 RAGC2_CLIP_ERROR Register
Register name: RAGC2_CLIP_ERROR
Page: 0x1860
Address: 0x0A
BIT 15
0
BIT 8
0
0
clip_error_2(15:8)
0
0
0
clip_error_2(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_error_2(15:0): This is the error value that is added into the loop accumulator when a clip is detected.
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8.4.4.44 RAGC3_INTEGINVL_LSB Register
Register name: RAGC3_INTEGINVL_LSB
Page: 0x1860
Address: 0x0B
BIT 15
0
BIT 8
0
0
integ_interval_3(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
integ_interval_3(7:0)
0
0
0
0
0
integ_interval_3(15:0): The LSBs of the integration time for receive AGC 3
8.4.4.45 RAGC3_INTEGINVL_MSB Register
Register name: RAGC3_INTEGINVL_MSB
Page: 0x1860
Address: 0x0C
BIT 15
0
BIT 8
0
0
ragc_update_3(7:0)
0
0
0
integ_interval_3(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc_update_3(7:0): Sets the number of receive AGC updates per sync event (0x00 is infinite).
integ_interval_3(23:16): The MSBs of the integration time for receive AGC 3
8.4.4.46 RAGC3_CONFIG0 Register
Register name: RAGC3_CONFIG0
Page: 0x1860
Address: 0x0D
BIT 15
0
BIT 8
0
0
ragc_sync_delay_3(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
hp_corner_3(2:0)
0
0
0
0
acc_shift_3(4:0)
0
0
0
ragc_sync_delay_3(7:0): The input sync to the receive AGC block is delayed by this value of samples.
hp_corner_3(2:0): This sets the corner frequency of the high-pass filter. Larger values result in higher
corner frequencies.
acc_shift_3(4:0): Selects the integrated power measurements result bits to be used as the error lookup
table address. A larger number means fewer samples must be integrated to achieve the
same result.
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8.4.4.47 RAGC3_CONFIG1 Register
Register name: RAGC3_CONFIG1
Page: 0x1860
Address: 0x0E
BIT 15
0
0
acc_offset_3(5:0)
0
0
0
BIT 8
err_shift_3(4:3)
0
0
0
BIT 7
0
BIT 0
err_shift_3(2:0)
0
0
0
0
delay_adj_3(4:0)
0
0
0
acc_offset_3(5:0): Constant subtracted from the integrated power measurement result before the error
lookup table
err_shift_3(4:0): Controls the loop gain by left-shifting the error output. Larger values result in higher
gain.
delay_adj_3(4:0): Sets the delay difference, in samples, between the DVGA outputs and the value
applied to the sample multiplier.
8.4.4.48 RAGC3_SD_THRESH Register
Register name: RAGC3_SD_THRESH
Page: 0x1860
Address: 0x0F
BIT 15
0
BIT 8
0
0
sd_thresh_3(15:8)
0
0
0
sd_thresh_3(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
sd_thresh_3(15:0): This is the threshold used by the signal-detect block to determine if there is signal on
the inputs. The comparison is done to the output of the squarer block, which is a 32-bit word.
Because of this, these bits are aligned with bits 24 down to 8 of the 32-bit squared value.
8.4.4.49 RAGC3_SD_TIMER Register
Register name: RAGC3_SD_TIMER
Page: 0x1860
Address: 0x10
BIT 15
0
BIT 8
0
0
sd_timer_3(15:8)
0
0
0
0
BIT 7
0
BIT 0
sd_timer_3(7:0)
0
0
0
0
0
0
0
0
sd_timer_3(15:0): After the first no signal sample occurs, this is the amount of samples that control the
length of time to determine the loss-of-signal condition.
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8.4.4.50 RAGC3_SD_SAMPLES Register
Register name: RAGC3_SD_SAMPLES
Page: 0x1860
Address: 0x11
BIT 15
0
BIT 8
0
sd_samples_3(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
sd_samples_3(7:0)
0
0
0
0
0
0
sd_samples_3(15:0): Number of samples that must be below the sd_thresh_X threshold within the
sd_timer_X timer value for the loss-of-signal condition to occur
8.4.4.51 RAGC3_CLIP_HITHRESH Register
Register name: RAGC3_CLIP_HITHRESH
Page: 0x1860
Address: 0x12
BIT 15
0
BIT 8
0
0
clip_hi_thresh_3(15:8)
0
0
0
clip_hi_thresh_3(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_thresh_3(15:0): The high threshold value for clip detection
8.4.4.52 RAGC3_CLIP_LOTHRESH Register
Register name: RAGC3_CLIP_LOTHRESH
Page: 0x1860
Address: 0x13
BIT 15
0
BIT 8
0
0
clip_lo_thresh_3(15:8)
0
0
0
clip_lo_thresh_3(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_lo_thresh_3(15:0): The low threshold value for clip detection
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8.4.4.53 RAGC3_CLIP_HITIMER Register
Register name: RAGC3_CLIP_HITIMER
Page: 0x1860
Address: 0x14
BIT 15
0
BIT 8
0
clip_hi_timer_3(15:8)
0
0
0
0
0
BIT 7
0
0
BIT 0
0
clip_hi_timer_3(7:0)
0
0
0
0
0
0
clip_hi_timer_3(15:0): The clip high timer value in samples
8.4.4.54 RAGC3_CLIP_LOTIMER Register
Register name: RAGC3_CLIP_LOTIMER
Page: 0x1860
Address: 0x15
BIT 15
0
BIT 8
0
0
clip_lo_timer_3(15:8)
0
0
0
clip_lo_timer_3(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_lo_timer_3(15:0): The clip low timer value in samples
8.4.4.55 RAGC3_CLIP_SAMPLES Register
Register name: RAGC3_CLIP_SAMPLES
Page: 0x1860
Address: 0x16
BIT 15
0
BIT 8
0
0
clip_hi_samples_3(7:0)
0
0
0
clip_lo_samples_3(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
clip_hi_samples_3(7:0): Number of samples above the high threshold within the clip high time to enable
a clip event
clip_lo_samples_3(7:0): Number of samples below the low threshold within the clip low time to disable a
clip event
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8.4.4.56 RAGC3_CLIP_ERROR Register
Register name: RAGC3_CLIP_ERROR
Page: 0x1860
Address: 0x17
BIT 15
0
BIT 8
0
0
clip_error_3(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
clip_error_3(7:0)
0
0
0
0
0
clip_error_3(15:0): Error value that is added into the loop accumulator when a clip is detected.
8.4.4.57 RAGC0_ACCUM_LSB Register
Register name: RAGC0_ACCUM_LSB
Page: 0x1860
Address: 0x18
Read-only
BIT 15
0
BIT 8
0
0
ragc0_accum(15:8)
0
0
0
ragc0_accum (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc0_accum(15:0): Lower 16 bits of the ragc0 error accumulator
8.4.4.58 RAGC0_ACCUM_MSB Register
Register name: RAGC0_ACCUM_MSB
Page: 0x1860
Address: 0x19
Read-only
BIT 15
0
BIT 8
0
0
ragc0_accum(31:24)
0
0
0
ragc0_accum (23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc0_accum(31:16): Upper 16 bits of the ragc0 error accumulator
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8.4.4.59 RAGC1_ACCUM_LSB Register
Register name: RAGC1_ACCUM_LSB
Page: 0x1860
Address: 0x1A Read-only
BIT 15
0
BIT 8
0
0
ragc1_accum(15:8)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
ragc1_accum (7:0)
0
0
0
0
0
ragc1_accum(15:0): Lower 16 bits of the ragc1 error accumulator
8.4.4.60 RAGC1_ACCUM_MSB Register
Register name: RAGC1_ACCUM_MSB
Page: 0x1860
Address: 0x1B Read-only
BIT 15
0
BIT 8
0
0
ragc1_accum(31:24)
0
0
0
ragc1_accum (23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc1_accum(31:16): Upper 16 bits of the ragc1 error accumulator
8.4.4.61 RAGC2_ACCUM_LSB Register
Register name: RAGC2_ACCUM_LSB
Page: 0x1860
Address: 0x1C Read-only
BIT 15
0
BIT 8
0
0
ragc2_accum(15:8)
0
0
0
ragc2_accum (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc2_accum(15:0): Lower 16 bits of the ragc2 error accumulator
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8.4.4.62 RAGC2_ACCUM_MSB Register
Register name: RAGC2_ACCUM_MSB
Page: 0x1860
Address: 0x1D Read-only
BIT 15
0
BIT 8
0
0
ragc2_accum(31:24)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
ragc2_accum (23:16)
0
0
0
0
0
ragc2_accum(31:16): Upper 16 bits of the ragc2 error accumulator
8.4.4.63 RAGC3_ACCUM_LSB Register
Register name: RAGC3_ACCUM_LSB
Page: 0x1860
Address: 0x1E Read-only
BIT 15
0
BIT 8
0
0
ragc3_accum(15:8)
0
0
0
ragc3_accum (7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc3_accum(15:0): Lower 16 bits of the ragc3 error accumulator
8.4.4.64 RAGC3_ACCUM_MSB Register
Register name: RAGC3_ACCUM_MSB
Page: 0x1860
Address: 0x1F Read-only
BIT 15
0
BIT 8
0
0
ragc3_accum(31:24)
0
0
0
ragc3_accum (23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ragc3_accum(31:16): Upper 16 bits of the ragc3 error accumulator
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8.4.5
SLWS212 – OCTOBER 2008
DDC Channel Controls
8.4.5.1 FIR_MODE Register
Register name: FIR_MODE
BIT 15
cdma_mode
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1***
Address: 0x00
BIT 8
Unused
0
Unused
0
0
crastarttap_cfir(4:0)
0
0
0
crastarttap_pfir(4:0)
0
0
0
0
Unused
0
Unused
0
Unused
0
BIT 7
BIT 0
0
0
cdma_mode: When asserted, the DDC block is in CDMA mode (2 streams per DDC block).
crastarttap_pfir: These bits define the number of taps that PFIR uses for the filtering.
crastarttap_cfir: These bits define the number of taps that CFIR uses for the filtering.
Formulas for the number of taps, in the different FIRs, using the crastarttap word.
DDC PFIR: 4 × (crastarttap_pfir + 1)
DDC PFIR long mode: 8 × (crastarttap_pfir + 1)
DDC CFIR: 2 × (crastarttap_cfir + 1)
8.4.5.2 FIR_GAIN Register
Register name: FIR_GAIN
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x01
BIT 15
0
pfir_gain(2:0)
0
0
Unused
0
Unused
0
Unused
0
Unused
0
BIT 7
Unused
0
BIT 8
Unused
0
BIT 0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
pfir_gain(2:0): PFIR gain, from 2e–19 to 2e–12 for the receive PFIR. (000 = 2e–19 and 111 = 2e–12)
cfir_gain:
When 0, then the gain of the CFIR is 2e-19; when set to 1, the gain is 2e-18.
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8.4.5.3 SQR_SUM Register
Register name: SQR_SUM
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x02
BIT 15
0
BIT 8
0
0
pmeter_sqr_sum_ddc(15:8)
0
0
0
pmeter_sqr_sum_ddc(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_sqr_sum_ddc(15:0): The sqr_sum register is the number of four-sample sets to accumulate for
a power measurement. In CDMA mode, one sample set is the I & Q of the signal and
diversity. Ia & Qa (signal) are each squared and accumulated and Ib & Qb (diversity) are
squared and accumulated. In UMTS mode, each I and Q pair is squared and accumulated.
Four samples are equal to one SQR_SUM count. The count is initiated when sync is
asserted or when the interval start time is reached. When the SQR_NUM number is reached,
the accumulated powers are made available for MPU access and an interrupt is generated.
8.4.5.4 STRT_INTRVL Register
Register name: STRT_INTRVL
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x03
BIT 15
0
BIT 8
0
0
pmeter_sync_delay_ddc(7:0)
0
0
0
pmeter_interval_ddc(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_sync_delay_ddc(7:0): The delay from selected sync source to when the power calculation
starts. The actual value is sync_delay + 1.
pmeter_interval_ddc(7:0): The start interval timer is the interval over which the SQR_SUM is restarted
and must be greater than the SQR_SUM. The actual interval is interval +1, and must be
greater than the sqr_sum interval. The interval start counter and RMS power accumulation
is started at the sync pulse after the programmed delay and every time the interval counter
reaches its limit. This value is in 1024-sample units.
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8.4.5.5 CIC_MODE1 Register
Register name: CIC_MODE1
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x04
BIT 15
BIT 8
0
0
cic_scale_a(4:0)
0
0
cic_gain_ ddc
0
0
cic_scale_b(4:2)
0
0
0
0
cic_decim(4:0)
0
BIT 7
BIT 0
cic_scale_b(1:0)
0
0
0
0
0
cic_scale_a(4:0): This sets the gain shift at the output of the A channel CIC. 0x00 is no shift; each
increment by 1 increases the signal amplitude by 2X.
cic_scale_b(4:0): This sets the gain shift at the output of the B channel CIC. 0x00 is no shift; each
increment by 1 increases the signal amplitude by 2X.
cic_gain_ddc: Adds a fixed gain of 12 dB at the CIC output when asserted.
cic_decim(4:0): Sets the CIC decimation rate, where decimation is cic_decim + 1.
8.4.5.6 CIC_MODE2 Register
Register name: CIC_MODE2
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
BIT 15
0
0
cic_m2_ena_a(5:0)
0
0
0
Address: 0x05
BIT 8
cic_m2_ena_b(5:4)
0
0
0
BIT 7
0
BIT 0
cic_m2_ena_b(3:0)
0
0
0
Unused
0
Unused
0
Unused
0
Unused
0
cic_m2_ena_a(5:0): Programs the A channel CIC fir sections M value to 2 when set, 1 when cleared.
cic_m2_ena_a(0) controls the M value for the first comb section and cic_m2_ena_a(5)
controls the M value for the last comb section.
cic_m2_ena_b(5:0): Programs the B channel CIC fir sections M value to 2 when set, 1 when cleared.
cic_m2_ena_b(0) controls the M value for the first comb section and cic_m2_ena_b(5)
controls the M value for the last comb section.
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8.4.5.7 TADJC Register
Register name: TADJC
BIT 15
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Unused
0
Unused
0
0
tadj_offset_coarse_b(2:0)
0
Address: 0x06
Double buffered, requires sync for loading
0
tadj_offset_coarse_a(2:0)
0
0
Unused
0
0
Unused
0
BIT 8
Unused
0
Unused
0
Unused
0
Unused
0
BIT 7
BIT 0
Unused
0
tadj_offset_coarse_a(2:0): This is the coarse time adjustment offset and acts as an offset from the write
address in the delay RAM. This value affects the A-data in the path if CDMA mode is being
used. Each LSB is one more offset between input to the caurse delay block and the output of
the coarse block.
tadj_offset_coarse_b(2:0): Affects the B-channel in CDMA, just as tadj_offset_coarse_a(2:0) affects the
A-channel.
8.4.5.8 TADJF Register
Register name: TADJF
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x07
Double buffered, requires sync for loading
BIT 15
0
tadj_offset_fine_a(2:0)
0
0
0
tadj_offset_fine_b(2:0)
0
0
BIT 8
tadj_interp(2:1)
0
0
BIT 7
tadj_interp(0)
0
BIT 0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
Unused
0
tadj_offset_fine_a(2:0): This is the fine-adjust (zero stuff offset) value. It adjusts the time delay at the
rxclk rate. This value affects the A-channel data in the path if CDMA mode is being used.
tadj_offset_fine_b(2:0): Same as tadj_offset_fine_a(2:0) except this value affects the B-channel data in
CDMA mode.
tadj_interp(2:0): This is the interpolation (zero stuff) value for the fine time adjust block. Interpolation can
be from 1 to 8 (tadj_interp + 1). This value affects the A and B data in the path if CDMA
mode is being used.
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PHASEADD0A Register
Register name: PHASEADD0A
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x08
Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
phase_add_a(15:8)
0
0
0
phase_add_a(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
phase_add_a(15:0) This 32-bit word is used to control the frequency of the NCO. This value is added to
the frequency accumulator every clock cycle (UMTS mode and Main channel in CDMA
mode).
8.4.5.10 PHASEADD1A Register
Register name: PHASEADD1A
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x09
Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
phase_add_a(31:24)
0
0
0
phase_add_a(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
phase_add_a(31:16): This 32-bit word is used to control the frequency of the NCO. This value is added
to the frequency accumulator every clock cycle (UMTS mode and A channel in CDMA
mode).
8.4.5.11 PHASEADD0B Register
Register name: PHASEADD0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x0A Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
phase_add_b(15:8)
0
0
0
phase_add_b(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
phase_add_b(15:0): This 32-bit word is used to control the frequency of the NCO. This value is added to
the frequency accumulator every clock cycle (B channel in CDMA mode).
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8.4.5.12 PHASEADD1B Register
Register name: PHASEADD1B
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x0B Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
phase_add_b(31:24)
0
0
0
phase_add_b(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
phase_add_b(31:16): This 32-bit word is used to control the frequency of the NCO. This value is added
to the frequency accumulator every clock cycle (B channel in CDMA mode).
8.4.5.13 PHASE_OFFSETA Register
Register name:
PHASE_OFFSETA
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x0C Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
phase_offset_a(15:8)
0
0
0
phase_offset_a(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
phase_offset_a(15:0): This is the fixed phase offset added to the output of the frequency accumulator for
sinusoid generation in the NCO. (UMTS mode and A channel in CDMA mode).
8.4.5.14 PHASE_OFFSETB Register
Register name:
PHASE_OFFSETB
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x0D Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
phase_offset_b(15:8)
0
0
0
phase_offset_b(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
phase_offset_b(15:0): This is the fixed phase offset added to the output of the frequency accumulator for
sinusoid generation in the NCO. (B channel in CDMA mode)
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8.4.5.15 CONFIG1 Register
Register name: CONFIG1
BIT 15
dither_ena
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
dither_mask(1:0)
0
0
pmeter_ sync_
disable
0
Unused
0
Unused
0
Unused
0
Address: 0x0E
ddc_ena
muxed _data
mixer_gain
BIT 8
mpu_ram_read
0
0
0
0
Unused
0
zero_ qsample
0
mux_pos
0
mux_factor
0
BIT 7
Unused
0
BIT 0
dither_ena: This bit controls whether dither is turned on (1) or off (0).
dither_mask(1): This bit controls the MASKing of the dither word MSB. (1 = MASKed, 0 = used in dither
word).
dither_mask(0): This bit controls the MASKing of the dither word MSB-1. (1 = MASKed, 0 = used in
dither word).
pmeter_sync_disable: Turns off the sync to the channel power meter. This can be used to turn off syncs
individually to a channel power meter while still having syncs available to other power
meters.
ddc_ena:
When set, this turns on the DDC. When cleared, the clocks to this block are turned off. For
the DDC blocks used as the second half in the long PFIR configuration, this bit should be
cleared.
muxed_data: When asserted the DDC multiplexer block assumes that multiple channels are multiplexed
together on one input data stream. For factory use only.
For a 2× multiplexed stream it would look like: Sa0, Sb0, Sa1, Sb1, Sa2, Sb2 …. etc...
mixer_gain: Adds a fixed 6 dB of gain to the mixer output(before round and limiting) when asserted.
mpu_ram_read: (TESTING PURPOSES) Allows the coefficient RAMs in the PFIR/CFIR to be read out
the MPU data bus. Unfortunately, this cannot be done during normal operation and must be
done when the state of the output data is not important. THIS BIT MUST BE SET ONLY
DURING THE MPU READ OPERATION AND MUST BE CLEARED FOR NORMAL DDC
OPERATION.
zero_qsample: When asserted, the Q sample into the mixer is held to zero. For UMTS mode at any input
rate, and CDMA mode with input rates of rxclk/2 or lower, this bit must be set for real-only
input data mode (also for multiplexed input data stream modes). For real-only inputs at the
full rxclk rate in CDMA mode, the remix_only bit must be set in the DDCCONFIG1 register.
mux_pos:
These bits set the position for selection in the multiplexed data stream. This value must be
less than or equal to the mux_factor bits.
mux_factor: These two bits set the number of channels in the data stream. 0 = one stream, 1 = two
streams. The ch_rate_sel bits for the DDC should be programmed to rxclk/2 for the
two-stream mode.
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8.4.5.16 CONFIG2 Register
Register name: CONFIG2
BIT 15
Unused
0
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Unused
0
Unused
0
Address: 0x0F
Unused
0
Unused
0
Unused
0
BIT 7
BIT 8
Unused
0
BIT 0
Unused
0
Unused
0
ddc_tst_sel(5:0)
0
0
0
0
0
0
ddc_tst_sel(5:0): This is the selection of which signal comes out the test bus. When a constant 0 is
selected, this also reduces power by preventing the data at the input of the tst_blk from
changing. It does not stop the clock, however. The 36 bits for the test bus are routed to the
rxin_c, rxin_d, dvga_c and dvga_d pins on the chip.
136
SYNC on dvga_c(0)
AFLAG on dvga_d(5)
ddc_tst_sel(5:0)
Data selected for output (36 bits total)
rxin_d(15:0), dvga_c(3:2), rxin_c(15:0), dvga_c(5:4)
N
00 0000
constant 0
Y
00 0001
pfir output – (35:18) I and (17:0) Q
Y
00 0010
cfir output – (35:18) I and (17:0) Q
N
00 0011
tadj A output – (35:18) I and (17:0) Q
N
00 0100
tadj B output – (35:18) I and (17:0) Q
N
00 0101
nco SINE output – (35:20) zeroed (19:0) SINE
N
00 0110
nco COSINE output – (35:20) zeroed (19:0) COSINE
N
00 0111
cic output – (35:18) I and (17:0) Q
Y
00 1000
agc output – (35:11) I and (10:0) Q
{full 25b I result and upper 11b Q result}
N
00 1001
mix A output – (35:18) i × cos – q × sin and (17:0) i × sin + q × cos
N
00 1010
mix B output – (35:18) i × cos – q*sin and (17:0) i × sin + q × cos
N
00 1011
DDC MUX A output (35:18) I and (17:0) Q
N
00 1100
DDC MUX B output (35:18) I and (17:0) Q
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8.4.5.17 AGC_CONFIG1 Register
Register name: AGC_CONFIG1
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x10
BIT 15
BIT 8
agc_dblw(3:0)
0
0
agc_dabv(3:0)
0
0
0
0
0
BIT 7
BIT 0
agc_dzro(3:0)
0
0
0
agc_dsat(3:0)
0
0
0
0
0
0
agc_dblw(3:0): The value to shift the gain that is then added to the accumulator when the value of the
incoming data * current gain value is below the threshold.
agc_dabv(3:0): The value to shift the gain that is then subtracted from the accumulator when the value of
the incoming data * the current gain value is above the threshold.
agc_dzro(3:0): The value to shift the gain that is then added to the accumulator when the value of the
incoming data * current gain value is consistently equal to zero (usually a smaller number
than agc_dblw).
agc_dsat(3:0): The value to shift the gain that is then subtracted form the accumulator when the value of
the incoming data * the current gain value is consistently equal to maximum (saturation).
NOTE:The larger the number in the foregoing words, the smaller the step size. The preceding values
control the AGC gain shifting (range is from 3 to 18).
8.4.5.18 AGC_CONFIG2 Register
Register name: AGC_CONFIG2
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x11
BIT 15
BIT 8
zero_msk(3:0)
0
0
agc_rnd(3:0)
0
0
0
0
0
BIT 7
0
BIT 0
agc_thresh(7:0)
0
0
0
0
0
0
0
0
zero_msk(3:0): Masks the lower 4 bits of the magnitude of the input signal so that they are counted as
zeros.
agc_rnd(3:0): Determines where to round the output of the AGC; the number of bits output is (18 –
agc_rnd). For example, 0000 is 18 bits.
agc_thresh(7:0): Threshold for (input * gain) comparison. This value is compared to the magnitude of the
upper 8 bits of the agc output.
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8.4.5.19 AGC_CONFIG3 Register
Register name: AGC_CONFIG3
BIT 15
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x12
BIT 8
Unused
0
Unused
0
agc_ freeze
0
Unused
0
Unused
0
agc_ clear
0
0
agc_max_cnt(3:0)
0
0
0
agc_zero_cnt(3:0)
0
0
BIT 7
Unused
0
0
BIT 0
0
agc_freeze: Freezes the agc when set. This should be asserted when the AGC algorithm is bypassed or
held constant.
agc_max_cnt(3:0): When the agc_output (input * gain) is at full scale for this number of samples, then
the gain shift value is changed to agc_dsat.
agc_clear:
Clears the AGC accumulator when set. Assert this when the AGC is in bypass mode.
agc_zero_cnt(3:0): when the agc_output (input * gain) is zero value for this number of samples, then the
gain shift value is changed to agc_dzro.
8.4.5.20 AGC_GAINMSB Register
Register name:
AGC_GAINMSB
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x13
Double buffered, requires sync for loading
BIT 15
0
BIT 8
0
0
agc_gaina(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
agc_gainb(23:16)
0
0
0
0
0
agc_gaina(23:16): MSBs of the agc_gaina word.
agc_gainb(23:16): MSBs of the agc_gainb word.
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8.4.5.21 AGC_GAINA Register
Register name: AGC_GAINA
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x14
Double buffered, requires sync for loading
BIT 15
BIT 8
agc_gaina(15:8)
0
0
0
0
0
0
0
BIT 7
0
BIT 0
agc_gaina(7:0)
0
0
0
0
0
0
0
0
agc_gaina(15:0): This is the lower 16 bits of the total 24 bits of programmable gain. The gain value is
always positive with the upper 12 bits being the integer value and the lower 12 bits being the
fractional. This gain value is used for all UMTS operations and for A-channel data when in
CDMA mode. A 24-bit value of 0000 000 0001.0000 0000 0000 is unity gain.
8.4.5.22 AGC_GAINB Register
Register name: AGC_GAINB
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x15
Double buffered, requires sync for loading
BIT 15
BIT 8
agc_gainb(15:8)
0
0
0
0
0
0
0
BIT 7
0
BIT 0
agc_gainb(7:0)
0
0
0
0
0
0
0
0
agc_gainb(15:0): This is the lower 16 of the total of 24 bits of programmable gain. The gain value is
always positive with the upper 12 bits being the integer value and the lower 12 bits being the
fractional. This gain value is used for B-channel data when in CDMA. A 24-bit value of
0000 0000 0001.0000 0000 0000 is unity gain.
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8.4.5.23 AGC_AMAX Register
Register name: AGC_AMAX
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x16
BIT 15
BIT 8
agc_amax(15:8)
0
0
0
0
0
0
0
BIT 7
0
BIT 0
agc_amax(7:0)
0
0
0
0
0
0
0
0
agc_amax(15:0): This is the maximum gaina or gainb can be adjusted up. The value programmed is a
positive value that is used to generate the most-positive AGC gain adjust. For example, if
512 is programmed, the maximum gain is the programmed gain (AGC_GAINA/B) + 512.
8.4.5.24 AGC_AMIN Register
Register name: AGC_AMIN
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x17
BIT 15
BIT 8
agc_amin(15:8)
0
0
0
0
0
0
0
BIT 7
0
BIT 0
agc_amin(7:0)
0
0
0
0
0
0
0
0
agc_amin(15:0): This is the minimum gaina or gainb can be adjusted down. The value programmed is a
positive value that is inverted internally to generate the most-negative AGC gain adjust. For
example, if 512 is programmed, the minimum gain is the programmed gain (AGC_GAINA/B)
– 512.
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8.4.5.25 PSER_CONFIG1 Register
Register name: PSER_CONFIG1
BIT 15
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x18
BIT 8
0
0
Unused
0
Unused
0
0
pser_recv_fsinvl(6:0)
0
0
0
BIT 7
Unused
0
0
BIT 0
0
0
pser_recv_bits(4:0)
0
0
0
pser_recv_fsinvl(6:0): Receive serial interface frame sync interval in bit clocks.
pser_recv_bits(4:0): Number of output bits per sample – 1; for 18 bits, this is set to 1 0001.
8.4.5.26 PSER_CONFIG2 Register
Register name: PSER_CONFIG2
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x19
BIT 15
0
pser_recv_clkdiv(3:0)
0
0
0
Unused
0
Unused
0
BIT 7
pser_recv_8pin
0
Unused
0
BIT 8
Unused
0
BIT 0
pser_recv_alt
0
Unused
0
Unused
0
Unused
0
Unused
0
pser_recv_fsdel(1:0)
0
0
pser_recv_clkdiv(3:0): Receive serial interface clock divider rate – 1; 0 is full-rate and 15 divides the
clock by 16. For example, to run the receive serial interface at 1/4 the AFE8405 clock, set
pser_recv_clkdiv(3:0) = 0011.
pser_recv_8pin: When set, four pins are used for I and four pins for Q in UMTS mode. When cleared,
two pins are used for I and two pins for Q. This is used in combination with the pser_recv_alt
bit. When this bit is set, it would be set in two adjacent DDC channels; one would also set
the pser_recv_alt bit in the adjacent DDC. This causes the I channel to be serialized on four
pins and the Q channel to be serialized on the four adjacent-channel pins.
pser_recv_alt: When set, this channel's receive serial interface outputs the Q data from the adjacent
DDC channel.
pser_recv_fsdel(1:0): Delay between the receive frame sync output and the MSB of serial data {3, 2, 1,
0}. This number is in serial output bit times, not rxclk periods.
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8.4.5.27 DDCCONFIG1 Register
Register name: DDCCONFIG1
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x1A
BIT 15
BIT 8
0
agc_rnd_
disable
0
0
remix_only
0
ddcmux_sel_a (3:0)
0
0
0
gain_mon
0
ch_rate_sel(1:0)
0
0
BIT 7
BIT 0
ddcmux_sel_b(3:0)
0
0
0
cic_ bypass
0
double_tap(1:0)
0
0
ddcmux_sel_X(3:0): Controls which samples go to the mixer for I/Q. Because in CDMA there are two
streams, an A and B stream, two multiplex select values are used.
(1)
Select Value
I data from X input (1)
Q data from X input (1)
0000
RXINA
RXINA
0001
RXINB
RXINB
0010
RXINC
RXINC
0011
RXIND
RXIND
0100
RXINA
RXINB
0101
RXINA
RXINC
0110
RXINA
RXIND
0111
RXINB
RXINA
1000
RXINB
RXINC
1001
RXINB
RXIND
1010
RXINC
RXINA
1011
RXINC
RXINB
1100
RXINC
RXIND
1101
RXIND
RXINA
1110
RXIND
RXINB
1111
RXIND
RXINC
RXINA = internal A-side ADC, RXINB not used, RXINC = external input C, RXIND = external input D
agc_rnd_disable: When set, the agc_rnd bits have no effect. The whole 29 bits are used in the rounding
and the round bit is bit 4.
gain_mon: Combines the gain with the I/Q output signals when asserted.
OUTPUT
Bits(17:10)
I
Gained I value
Bits(9:4)
Q
Gained Q value
Bits(3:2)
Gain(18:11)
Gain(10:5)
Bits(1:0)
00
Shift status(1:0)
00
ch_rate_sel(1:0): Sets the DDC channel input data rate. The value set here should match the value in
the receive input interface rate-select bits (rate_sel).
ch_rate_sel
142
AFE8405 GENERAL CONTROL
Input data rate
00
rxclk
01
rxclk/2
10
rxclk/4
11
rxclk/8
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When muxed_data is set (Factory Use Only), rate_sel should be set to rxclk 00 and ch_rate_sel should be
set to rxclk/2 01.
remix_only: Assert this when real only, full rxclk rate input data is used in CDMA mode. The signal on the
Q bus selected by the ddcmux_sel_X(3:0) bits above is ignored (functions as if the Q data is
0).
cic_bypass: Factory Use Only. If asserted, then the data from the rxin_a(15:0) and rxin_b(15:0) are fed
directly into the cfir input as I and Q respectively. rxin_a(0) also functions as the sync_cfir
signal and should rise at the beginning of input data.
ONLY DDC0, DDC2, DDC4 and DDC6 can be the UMTS double-tap (64- to 128-tap) PFIR mode.
DDC1, DDC3, DDC5 and DDC7 PFIRs are used to lengthen the DDC0, DDC2, DDC4 and DDC6
PFIRs.
double_tap(1): When set, the DDC is in double-length PFIR mode, which sends the data out of the last
PFIR sample RAM in this DDC (DDC0, DDC2, DDC4, DDC6) to the adjacent secondary
DDC (DDC1, DDC3, DDC5, DDC7) PFIR forming a 128-tap delay line. Output data received
from the adjacent secondary DDC PFIR summer is added into the main DDC PFIR sum to
form the final output.
double_tap(0): When set, the PFIR input comes from the adjacent (main) PFIR. When cleared, PFIR
input is from the CFIR connected directly to this PFIR. Only valid in DDC1, DDC3, DDC5
and DDC7. The ddc_ena bit in the CONFIG1 register should be cleared for DDC1,
DDC3, DDC5 and DDC7 when double_tap(0) is set.
NOTE: To put 2 DDCs into 128 tap mode:
Program DDC0/DDC2/DDC4/DDC6 double_tap(1:0) to 10 and ddc_ena to 1.
Program DDC1/DDC3/DDC5/DDC7 double_tap(1:0) to 01 and ddc_ena to 0.
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8.4.5.28 SYNC_0 Register
Register name: SYNC_0
BIT 15
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x1B
BIT 8
0
ssel_cic(2:0)
0
1
ssel_agc_freeze(2:0)
1
0
Unused
0
0
Unused
0
0
ssel_pmeter(2:0)
0
0
ssel_serial(2:0)
0
BIT 7
Unused
0
0
BIT 0
0
ssel_cic(2:0): Selects the sync source for the DDC CIC filter, thus setting the decimation moment
ssel_pmeter(2:0): Selects the sync source for the channel power meter
ssel_agc_freeze(2:0): Selects the sync that is used to hold the AGC in freeze mode. With this
functionality the user can program the AGC freeze control to look at the state of an input
sync, or the one-shots. It defaults to being off or not looking at any syncs and not driving the
freeze control. This way, on startup, the chip looks at the MPU register bit for AGC freezing
and not the syncs.
ssel_serial(2:0): Selects the sync source for the DDC serial interface state machines.
Sync sources are contained in this and many of the following registers. For all sync source selections:
144
ssel_XXXX(2:0)
Selected sync source for DDC
000
rxsyncA
AFE8405 GENERAL CONTROL
001
rxsyncB
010
rxsyncC
011
rxsyncD
100
DDC sync counter
101
one shot (register write triggered)
110
always 0
111
always 1
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SLWS212 – OCTOBER 2008
8.4.5.29 SYNC_1 Register
Register name: SYNC_1
BIT 15
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x1C
BIT 8
0
ssel_tadj_fine(2:0)
0
0
ssel_gain(2:0)
0
0
Unused
0
0
Unused
0
0
ssel_tadj_reg(2:0)
0
0
ssel_ddc_agc(2:0)
0
BIT 7
Unused
0
0
BIT 0
0
ssel_tadj_fine(2:0): Selects the sync source for the fine time adjust zero stuff moment.
ssel_tadj_reg(2:0): Selects the sync source for the fine and coarse time adjust register updates.
ssel_gain(2:0): Selects the sync source for the DDC AGC gain register.
ssel_ddc_agc(2:0): Selects the sync source to initialize the AGC, primarily for test purposes.
8.4.5.30 SYNC_2 Register
Register name: SYNC_2
BIT 15
Unused
0
Page: 0x0%00
where:
% = 2 × (DDC channel #) + 1
Address: 0x1D
BIT 8
0
ssel_nco(2:0)
0
0
Unused
0
0
ssel_dither(2:0)
0
BIT 7
Unused
0
ssel_nco:
0
BIT 0
0
ssel_freq(2:0)
0
0
Unused
0
0
ssel_phase (2:0)
0
0
Selects the sync source for the NCO accumulator reset.
ssel_dither: Selects the sync source for the NCO phase dither generator reset.
ssel_freq:
Selects the sync source for the NCO frequency register.
ssel_phase: Selects the sync source for the NCO phase offset register.
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8.4.5.31 DDC_CHK_SUM Register
Register name: DDC_CHK_SUM
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x00
Read-only
BIT 15
0
BIT 8
0
0
ddc_chk_sum(15:0)
0
0
0
ddc_chk_sum(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
ddc_chk_sum: The DDC self test checksum value
8.4.5.32 PMETER_RESULT_A_LSB Register
Register name: PMETER_RESULT_A_LSB
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x01
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_a(15:8)
0
0
0
pmeter_result_a(7:0)
0
0
0
0
BIT 7
0
BIT 0
0
pmeter_result_a(15:0): Lower 16
measurement.
146
0
AFE8405 GENERAL CONTROL
bits
of
the
UMTS-mode
0
or
0
CDMA-mode
0
A-channel
power
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SLWS212 – OCTOBER 2008
8.4.5.33 PMETER_RESULT_A_MID Register
Register name: PMETER_RESULT_A_MID
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x02
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_a(31:24)
0
0
0
pmeter_result_a(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_result_a(31:16): Mid 16 bits of the UMTS-mode or CDMA-mode A-channel power measurement.
8.4.5.34 PMETER_RESULT_A_MSB Register
Register name: PMETER_RESULT_A_MSB
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x03
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_a(47:40)
0
0
0
pmeter_result_a(39:32)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_result_a(47:32): Upper mid 16 bits of the UMTS-mode or CDMA-mode A-channel power
measurement.
8.4.5.35 PMETER_RESULT_B_LSB Register
Register name: PMETER_RESULT_B_LSB
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x04
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_b(15:8)
0
0
0
pmeter_result_b(7:0)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_result_b(15:0): Lower 16 bits of the CDMA-mode B-channel power measurement
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8.4.5.36 PMETER_RESULT_B_MID Register
Register name: PMETER_RESULT_B_MID
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x05
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_b(31:24)
0
0
0
pmeter_result_b(23:16)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_result_b(31:16): Mid 16 bits of the CDMA-mode B-channel power measurement.
8.4.5.37 PMETER_RESULT_B_MSB Register
Register name: PMETER_RESULT_B_MSB
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x06
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_b(47:40)
0
0
0
pmeter_result_b(39:32)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_result_b(47:32): Upper mid 16 bits of the CDMA-mode B-channel power measurement.
148
AFE8405 GENERAL CONTROL
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8.4.5.38 PMETER_RESULT_AB_UMSB Register
Register name: PMETER_RESULT_AB_UMSB
Page: 0x0%20
where:
% = 2 × (DDC channel #) + 1
Address: 0x07
Read-only
BIT 15
0
BIT 8
0
0
pmeter_result_a(54:48)
0
0
0
pmeter_result_b(54:48)
0
0
0
0
BIT 7
0
0
BIT 0
0
0
0
0
pmeter_result_a(54:48): Most-significant 7 bits of the 55-bit UMTS- or CDMA-mode A-channel power
measurement. Bits 15–9 are used, bit 8 is not used.
pmeter_result_b(54:48): Most-significant 7 bits of the 55-bit
measurement. Bits 7–1 are used, bit 0 is not used.
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CDMA-mode
B-channel
AFE8405 GENERAL CONTROL
power
149
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
AFE8405IZDQ
ACTIVE
BGA
ZDQ
Pins Package Eco Plan (2)
Qty
484
60
Pb-Free
(RoHS)
Lead/Ball Finish
SNAGCU
MSL Peak Temp (3)
Level-3-260C-168 HR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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