PHILIPS UBA1706

INTEGRATED CIRCUITS
DATA SHEET
UBA1706
Cordless telephone line interface
Objective specification
Supersedes data of 1999 Mar 08
File under Integrated Circuits, IC17
1999 Jun 04
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
FEATURES
APPLICATIONS
Line interface
• Cordless base stations
• Low DC line voltage; operates down to 1.2 V (excluding
polarity guard)
• Mains or battery-powered telephone sets.
• Voltage regulator with adjustable DC voltage
GENERAL DESCRIPTION
• DC mask for voltage or current regulation (CTR21)
The UBA1706 is a BiCMOS integrated circuit intended for
use in mains-powered telecom terminals. It performs all
speech and line interface functions, DC mask for voltage
or current regulation and electronic hook switch control.
The device also includes general purpose switches.
• Line current limitation for protection
• Electronic hook switch control input
• Transmit amplifier with:
– Symmetrical inputs
Most of the characteristics are programmable via a 3-wire
serial bus interface.
– Fixed gain
– Large signal handling capability.
• Receive amplifier with fixed gain
• Transmit and receive amplifiers Automatic Gain Control
(AGC) for line loss compensation.
General purpose switches
Two switches with open-collector.
3-wire serial bus interface
Allows control of:
• DC mask (voltage or current regulation)
• Receive amplifier mute function
• AGC:
– On/off
– Slope
– Istart line current.
• The state of the general purpose switches
• Global power-down mode.
Supply
Operates with external supply voltage from 3.0 to 5.5 V.
ORDERING INFORMATION
PACKAGE
TYPE
NUMBER
NAME
UBA1706TS
SSOP24
1999 Jun 04
DESCRIPTION
plastic shrink small outline package; 24 leads; body width 5.3 mm
2
VERSION
SOT340-1
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
QUICK REFERENCE DATA
Iline = 15 mA; VCC = 3.3 V; RSLPE = 10 Ω; AGC pin connected to GND; Zline = 600 Ω; ZSET = 619 Ω; EHI = HIGH;
f = 1 kHz; Tamb = 25 °C; bit AGC at logic 1, all other configuration bits at logic 0; measured in the test circuit of Fig.14;
unless otherwise specified.
SYMBOL
PARAMETER
VCC
supply voltage
ICC
current consumption from pin VCC
Iline
line current operating range
VLN
DC line voltage
RREGC
DC mask slope in current regulation
mode
Gv(trx)
voltage gain
transmit amplifier from TXI to LN
CONDITIONS
1999 Jun 04
gain control range for transmit and
receive amplifiers with respect to
Iline = 15 mA
TYP.
MAX.
UNIT
3.0
−
5.5
V
normal operation; bit PD = 0
−
2.2
3.2
mA
power-down mode; bit PD = 1
−
110
150
µA
normal operation
11
−
140
mA
with reduced performance
3
−
11
mA
2.7
3.0
3.3
V
Iline > 35 mA (typical);
RLVI = 1 MΩ; RRGL = 7.15 kΩ;
bit CRC = 1
−
1.4
−
kΩ
VTXI = 50 mV (RMS)
10.6
11.6
12.6
dB
36.9
37.9
38.9
dB
−
6.5
−
dB
receive amplifier from RXI to RXO VRXI = 2 mV (RMS)
∆Gv(trx)
MIN.
Iline = 90 mA
3
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
BLOCK DIAGRAM
handbook, full pagewidth
VCC
21
RXI
9
UBA1706
RX PREAMP
V
I
TXI−
14
7
RXO
1
LN
2Vd
EHI
15
GND
LINE INTERFACE
RXM
2Vd
TXI+
19
V
ZSET
I
LINE
INTERFACE
TX PREAMP
300 mV
RAGC2
RAGC1
24
SLPE
2
REG
RSLPE
CREG
AGC
8
LOW VOLTAGE
PART
AGC
2
SAGC,
AGC
EHI
EHI
CURRENT
LIMITATION
VCC
SLPE
REG
SWITCH DRIVER
PROTECTION
10
EHI
5
LCC
6
CST
VCC
CCST
600 mV
TPDARL
D
CRC
RRGL
200 nA
RGL 4
3
LVI
RLVI
TNSW
TNON-HOOK
n.c.
16, 20, 22, 23
GENERAL SWITCHES
2
9
SERIAL
INTERFACE
SUPPLY
18
SWI1
17
SWI2
SWC1, SWC2
PD
12
13
11
EN
CLK
DATA
MBL039
Bit names are given in italics.
Fig.1 Block diagram.
1999 Jun 04
4
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
PINNING
SYMBOL
PIN
DESCRIPTION
LN
1
positive line terminal
REG
2
line voltage regulator decoupling
LVI
3
negative line voltage sense input
RGL
4
reference for current regulation mode
LCC
5
line current control output
CST
6
input for stability capacitor
RXO
7
receive amplifier output
AGC
8
automatic gain control/line loss
compensation adjustment
handbook, halfpage
LN
1
24 SLPE
REG
2
23 n.c.
LVI
3
22 n.c.
RGL
4
21 VCC
20 n.c.
RXI
9
receiver amplifier input
LCC
5
EHI
10
electronic hook switch control input
CST
6
DATA
11
serial bus data input
EN
12
programming serial bus enable input
CLK
13
serial bus clock input
TXI−
14
inverted transmit amplifier input
TXI+
15
non-inverted transmit amplifier input
n.c.
16
not connected
SWI2
17
NPN open-collector output 2
SWI1
18
NPN open-collector output 1
GND
19
ground reference
n.c.
20
not connected
VCC
21
supply voltage
n.c.
22
not connected
n.c.
23
not connected
SLPE
24
connection for slope resistor
1999 Jun 04
19 GND
UBA1706
RXO
7
18 SW1
AGC
8
17 SW2
RXI
9
16 n.c.
EHI 10
15 TXI+
DATA 11
14 TXI-
EN 12
13 CLK
FCA031
Fig.2 Pin configuration.
5
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
FUNCTIONAL DESCRIPTION
All data given in this chapter consists of typical values,
except when otherwise specified.
MGK706
8.5
handbook, halfpage
Vref
Supply (pins VCC and GND; bit PD)
(V)
7.5
The UBA1706 must be supplied with an external stabilized
voltage source across pins VCC and GND.
6.5
Without any signal and without any general purpose switch
selected, the internal current consumption is 2.2 mA at
VCC = 3.3 V. Each selected switch (pins SWI1 or SWI2)
increases the current consumption by 600 µA.
5.5
4.5
To drastically reduce current consumption, the UBA1706
is provided with a power-down mode controlled by bit PD.
When bit PD is at logic 1, the current consumption from
VCC becomes 110 µA. In the power-down mode, the serial
interface is the only function which remains active.
(1)
3.5
(2)
2.5
103
104
105
RVA (Ω)
106
Line interface
DC CHARACTERISTICS (PINS LN, SLPE, REG, CST, LVI,
LCC, RGL AND GND; BIT CRC)
(1) Influence of RVA on Vref.
(2) Vref without influence of RVA.
The IC generates a stabilized reference voltage (Vref)
across pins LN and SLPE. This reference voltage is equal
to 2.9 V, is temperature compensated and can be adjusted
by means of an external resistor (RVA). The reference
voltage can be increased by connecting the RVA resistor
between pins REG and SLPE (see Fig.3).
Fig.3 Reference voltage adjustment with RVA.
The IC regulates the line voltage at pin LN, which can be
calculated as follows:
V LN = V ref + R SLPE × I SLPE
The voltage at pin REG is used by the internal regulator to
generate the stabilized reference voltage and is decoupled
by a capacitor (CREG) which is connected to GND. This
capacitor, converted to an equivalent inductance
(see Section “Set impedance”) realizes the set impedance
conversion from its DC value (RSLPE) to its AC value
(ZSET in the audio frequency range). Figure 4 illustrates
the reference voltage supply configuration. As can be seen
from Fig.4, part of the line current flows into the ZSET
impedance network and is not sensed by the UBA1706.
Therefore, using the RVA resistor to change the value of
the reference voltage will also modify all parameters
related to the line current such as:
I SLPE = I line – I ZSET – I* ≅ I line – I ZSET
Where:
Iline = line current
IZSET = current flowing through ZSET
I* = current consumed between LN and GND
(approximately 100 µA).
The preferred value for RSLPE is 10 Ω. Changing RSLPE will
affect more than the DC characteristics; it also influences
the transmit gain, the gain control characteristics, the
sidetone level and the maximum output swing on the line.
• The AGC
Nevertheless, for compliance with CTR21, 8.66 Ω is the
optimum value for RSLPE.
• The DC mask management
• The low voltage area characteristics.
In the same way, changing the value of ZSET also affects
the characteristics. The IC has been optimized for
Vref = 2.9 V and ZSET = 619 Ω.
1999 Jun 04
6
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
LN+
handbook, full pagewidth
ILN
Iline
LN
Rp
UBA1706
35 kΩ
I*
IZSET
ZSET
619 Ω
Vd
Rd
4 kΩ
REG
SLPE
CREG
4.7 µF
ISLPE
GND
RSLPE
10 Ω
FCA032
Fig.4 Reference voltage supply configuration.
handbook, full pagewidth
ILN
Iline
LN+
Zline
LN
Rp
UBA1706
35 kΩ
IZSET
Vref
Rexch
ZSET
619 Ω
Vd
Rd
Vline
HOOK SWITCH
MANAGEMENT
4 kΩ
REG
CREG
4.7 µF
GND
SLPE
ISLPE
LCC
RSLPE
10 Ω
TNSW
Vexch
EHI
VEHI
VCE (TNSW)
LN−
FCA033
Fig.5 Line current settling simplified configuration.
1999 Jun 04
7
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
In off-hook conditions (voltage at pin EHI is HIGH), an
operational amplifier drives (at pin LCC) the base of
transistor TPDARL, which forms a current amplifier
structure in association with TNSW. The line current flows
through transistor TNSW. Transistor TNON-HOOK is forced
into deep saturation. A virtual ground is created at pin LVI
because of the operational amplifier. A DC current (ILVI) is
sourced from pin LVI into the RLVI resistor to generate a
voltage source. Thus, the voltage across pins GND and
LN− becomes:
The DC line current flowing into the set is determined by
the exchange supply voltage (Vexch), the feeding bridge
resistance (Rexch), the DC resistors of the telephone line
(Rline) and the set (RSET), the reference voltage (Vref) and
the voltage introduced by the transistor (TNSW) used as
line interrupter (see Fig.5).
With a line current below Ilow (8 mA with ZSET = 619 Ω), the
internal reference voltage (Vref) is automatically adjusted
to a lower value. This means that several sets can operate
in parallel with DC line voltages (excluding the polarity
guard) down to 1.2 V. With a line current below Ilow, the
circuit has limited transmit and receive levels. This is called
the low voltage area.
VCE (TNSW) = RLVI × ILVI + VCE (TNON-HOOK) ≅ RLVI × ILVI
The voltage Vline across line terminals LN+ and LN− can
be calculated as follows:
Figure 6 shows in more detail how the UBA1706, in
association with some external components, manages the
line interrupter (TNSW external transistor).
Vline ≅ Vref + RSLPE × (Iline − IZSET) + VCE (TNSW)
Where:
Iline = line current
In on-hook conditions (voltage at pin EHI is LOW), the
voltage at pin LCC is pulled up to the supply voltage level
(VCC) to turn off transistor TPDARL. As a result, because of
resistor RPD, transistors TNSW and TNON-HOOK are
switched off. Transistor TNON-HOOK disconnects resistor
RLVI from the LN− line terminal to guarantee a high
on-hook impedance.
1999 Jun 04
IZSET = current flowing through ZSET.
8
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LN+
UBA1706
Vref
REG
Iline
ILN
8.2 V
IZSET
Vd
ZSET
619 Ω
CREG
4.7 µF
Rd
ISLPE
4 kΩ
EHI
VEHI
RSLPE
10 Ω
SLPE
VCC
9
CURRENT
REGULATION
MODE
MANAGEMENT
CURRENT
LIMITATION
ILVIV
200 nA
RPLU
150 kΩ
LCC
ILVI
Philips Semiconductors
LN
35 kΩ
Cordless telephone line interface
1999 Jun 04
Rp
TPDARL
Vline
CRC
RGL
LVI
GND
RRGL
CLVI
RLVI
7.15 kΩ
470 pF
1 MΩ
CST
CCST
22 pF
RON-HOOK
TNON-HOOK
100 kΩ
DSW
TNSW
Dprot
RPD
Iline
LN−
Fig.6 Line interrupter management and DC mask regulation configuration.
UBA1706
Bit names are given in italics.
handbook, full pagewidth
FCA034
Objective specification
20 kΩ
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
Therefore, VCE (TNSW) ≅ RLVI × ILVIV = 200 mV in a typical
application (see Fig.15).
The UBA1706 offers the possibility to choose two kinds of
regulations for the DC characteristic between line
terminals LN+ and LN− (see Fig.7):
The slope ∆Vline/∆Iline of the Vline, Iline characteristic is
RREGV ≅ RSLPE.
• Voltage regulation mode
• Current regulation mode.
Current regulation mode
In current regulation mode (bit CRC at logic 1), when the
line current is lower than Iknee = 35 mA (with
ZSET = 619 Ω), VCE (TNSW) is fixed by means of a 200 nA
DC constant current ILVIV flowing through RLVI. When the
line current is higher than 35 mA, an additional current
(proportional to the line current) flows through RLVI. As a
result, TNSW works as a DC voltage source increasing with
the line current. VCE (TNSW) can be calculated as follows:
handbook, halfpage
Vline
 R SLPE

V CE ( TN SW ) ≅ R LVI ×  ---------------- × ( I line – I knee ) + I LVIV 
 R RGL

Where:
Iline = line current
RRGL = resistor connected at pin RGL.
(1)
(2)
Ilow
Iknee
In a typical application (see Fig.15), the slope ∆Vline/∆Iline
of the Vline, Iline characteristic is determined by the ratio of
the resistors connected at pins SLPE, LVI and RGL, as
follows:
R SLPE
R REGC ≅ R SLPE + R LVI × --------------- = 1400 Ω .
R RGL
Iline
(3)
Iprot
(4)
MGK710
(1) Low voltage area.
(2) Small slope (determined by RSLPE).
(3) Small slope (dashed line; determined by RSLPE) in voltage
regulation mode.
High slope (full line; determined by RSLPE, RLVI and RRGL) in
current regulation mode.
Current limitation
Whatever the selected mode is, the line current is limited
to approximately 145 mA; this current is sensed on SLPE.
For this purpose, the external Zener diode must be
connected between pins LN and SLPE. The speech
function no longer operates in this condition.
(4) Current limitation.
Fig.7
General form of the DC mask as a function
of the regulation mode.
ELECTRONIC HOOK SWITCH CONTROL (PIN EHI)
The regulation mode is selected by bit CRC via the serial
interface.
The electronic hook switch input (EHI) controls the state of
transistor TPDARL. When the voltage applied at pin EHI is
LOW, transistor TPDARL is turned off. The voltage at
pin LCC is pulled up to supply voltage (VCC). Transistors
TNSW and TNON-HOOK are also turned off by means of a
pull-down resistor (RPD). When the voltage applied at
pin EHI is HIGH, transistor TPDARL is driven by the
operational amplifier at pin LCC and the regulation mode
selected is operating. An internal 165 kΩ pull-up resistor is
connected between pins LCC and VCC.
The DC mask regulation is realised by adjusting the DC
voltage VCE (TNSW) across pin GND and line terminal LN−
as a function of the line current.
Voltage regulation mode
In the voltage regulation mode (bit CRC at logic 0), the
VCE (TNSW) voltage is fixed by means of a 200 nA DC
constant current ILVIV flowing through RLVI.
1999 Jun 04
10
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
The rail-to-rail output stage is designed to drive a 500 µA
peak current. The output impedance at pin RXO is
approximately 100 Ω.
Input EHI can also be used for pulse dialling or register
recall (timed loop break). During line breaks (the voltage at
pin EHI is LOW or open-circuit), the voltage regulator is
switched off and the capacitor at pin REG is internally
disconnected to prevent its discharge. As a result, the
voltage stabilizer will have negligible switch-on delay after
line interruptions. This minimizes the contribution of the IC
to the current waveform during pulse dialling or register
recall.
The voltage gain from pin RXI to pin RXO is set at 37.9 dB.
This gain value compensates typically the attenuation of
the anti-sidetone network (see Fig.10). The output and the
input are biased at 2 × Vd ≅ 1.4 V.
AGC is provided on this amplifier for line loss
compensation. This amplifier can be muted by activating
the receive mute function (bit RXM at logic 1).
When the UBA1706 is in power-down mode (bit PD at
logic 1), transistor TPDARL is forced off whatever the
voltage applied at pin EHI.
SET IMPEDANCE
In the audio frequency range, the dynamic impedance
between pins LN and GND (illustrated in Fig.8) is mainly
determined by the ZSET impedance. The impedance
introduced by the external TNSW transistor connected
between pins GND and LN− is negligible.
handbook, halfpage
LN
LEQ
TRANSMIT AMPLIFIER (PINS TXI+ AND TXI−)
Vref
The UBA1706 has symmetrical transmit inputs TXI+ and
TXI−. The input impedance between pins TXI+ or TXI− and
GND is 21 kΩ. The voltage gain from pins TXI+ or TXI− to
pin LN is set at 11.6 dB with 600 Ω line load (Zline) and
619 Ω set impedance. The inputs are biased at
2 × Vd ≅ 1.4 V, with Vd representing the diode voltage.
AGC is provided on this amplifier for line loss
compensation.
RSLPE
CREG
10 Ω
4.7 µF
GND
MGL215
Leq = CREG × RSLPE × RP
RP = internal resistance = 35 kΩ.
The receive amplifier (see Fig.9) has one input (RXI) and
one output (RXO). The input impedance between
pins RXI and GND is 21 kΩ.
Fig.8
Equivalent impedance between
pins LN and GND.
handbook, full pagewidth
RXM
V
I
2Vd
I
RXO
V
2Vd
from AGC
UBA1706
FCA035
Bit names are given in italics.
Fig.9 Receive amplifier.
1999 Jun 04
REG
SLPE
RECEIVE AMPLIFIER (PINS RXI AND RXO; BIT RXM)
RXI
ZSET
619 Ω
RP
11
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
Therefore, the value chosen for Zbal should be for an
average line length, which gives satisfactory sidetone
suppression with short and long lines.
SIDETONE SUPPRESSION
The UBA1706 anti-sidetone network comprising
ZSET//Zline, Rast1, Rast2, Rast3, RSLPE and Zbal (see Fig.10)
suppresses the transmitted signal in the received signal.
Maximum compensation is obtained when the following
conditions are fulfilled:
The suppression also depends on the accuracy of the
match between Zbal and the impedance of the average
line.
RSLPE × Rast1 = ZSET × (Rast2 + Rast3)
The anti-sidetone network for the UBA1706 (see Fig.15)
attenuates the receiving signal from the line by 38 dB
before it enters the receiving amplifier. The attenuation is
almost constant over the whole audio frequency range.
A Wheatstone bridge configuration (see Fig.11) may also
be used.
( R ast2 × ( R ast3 + R SLPE ) )
k = ------------------------------------------------------------------( R ast1 × R SLPE )
Zbal = k × Zline
The scale factor ‘k’ is chosen to meet the compatibility with
a standard capacitor from the E6 or E12 range for Zbal.
More information on the balancing of an anti-sidetone
bridge can be obtained in our publication “Applications
Handbook for Wired Telecom Systems, IC03b”.
In practice, Zline varies considerably with the line type and
the line length.
LN
handbook, full pagewidth
Zline
ZSET
Rast1
Im
GND
RXI
ZRXI
Rast2
RSLPE
Rast3
SLPE
Zbal
MGL216
Fig.10 Equivalent circuit of UBA1706 anti-sidetone bridge.
1999 Jun 04
12
Philips Semiconductors
Objective specification
Cordless telephone line interface
handbook, full pagewidth
UBA1706
LN
Zline
ZSET
Zbal
Im
GND
RSLPE
RXI
ZRXI
Rast1 RA
SLPE
MGL217
Fig.11 Equivalent circuit of an anti-sidetone network in a Wheatstone bridge configuration.
An external resistor RAGC (connected between pins GND
and AGC) enables the Istart and Istop line currents to be
increased (the ratio between Istart and Istop is not affected
by this external resistor). Therefore, internal and external
adjustments of the AGC allow optimization of the IC for
many configurations of exchange supply voltage and
feeding bridge resistance.
AUTOMATIC GAIN CONTROL (PIN AGC; BITS RAGC1,
RAGC2, SAGC AND AGC)
The UBA1706 performs automatic line loss compensation.
The AGC varies the gain of the transmit amplifier and the
gain of the receive amplifier in accordance with the DC line
current. The control range is 6.5 dB (which corresponds
roughly to a line length of 5.5 km for a 0.5 mm diameter
twisted-pair copper cable with a DC resistance of
176 Ω/km and an average attenuation of 1.2 dB/km).
Part of the line current flows into the ZSET impedance
network. The IC has been optimized for ZSET = 619 Ω.
Changing this 619 Ω value slightly modifies Istop and Istart
line currents as well as the value of the two AGC slopes.
When the line current is greater than Istop, the voltage
gains are minimum. When the line current is less than Istart,
the voltage gains are maximum.
The AGC function can be disabled by setting the AGC bit
to logic 0 via the serial interface or by leaving pin AGC
open-circuit. In this case, both of the voltage gains are
maximum.
When the AGC pin is connected to pin GND, the start line
current (Istart) can be chosen between 22.5 and 29.5 mA
via bits RAGC1 and RAGC2 through the serial interface.
Two values for the Istop/Istart ratio (slope of the AGC) are
possible via bit SAGC through the serial interface. When
bit SAGC is at logic 0 then Istop = 2.7 × Istart (optimized for
voltage regulation mode). When SAGC is at logic 1 then
Istop = 1.9 × Istart (optimized for current regulation mode).
1999 Jun 04
13
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
Additional leading bits are ignored and no check is made
on the number of clock pulses. New programming data can
always be captured during global power-down (bit PD at
logic 1).
General purpose switches (pins SWI1 and SWI2; bits
SWC1 and SWC2)
The UBA1706 is equipped with two general purpose
open-collector switches, which short circuit pins SWI1 and
SWI2 to ground. These switches are controlled by bits
SWC1 and SWC2, respectively, and have an operating
voltage limited to 12 V. The outputs have to be current
biased. For a bias current between 2 and 20 mA, the
AC impedance is 30 Ω maximum.
Data is entered with the most significant bit first. The
leading six bits make up the data field (bits D0 to D5) while
the trailing two bits are the address field (bits ADO and
AD1). The first bit entered is D5, the last bit AD0. This
organisation allows the transmission of only the number of
bits of the addressed register.
Serial interface (pins DATA, CLK and EN)
Figure 13 shows the serial timing diagram. Table 1 gives
the list of registers.
A simple 3-wire unidirectional serial bus is used to program
the circuit. The three wires of the bus are EN, CLK and
DATA. The data sent to the device is loaded in bursts
framed by EN. Programming clock edges (falling edges)
and their appropriate data bits are ignored until EN goes
HIGH. The programmed information is loaded into the
addressed register when EN returns to LOW or left
open-circuit.
When the supply voltage VCC drops below 2.5 V, all
register files are set to the initial state (see Table 1)
defined by the power-up reset. At start-up, the circuit is in
power-down mode.
When the IC is used in a noisy environment, it is advised
to periodically refresh the content of registers.
During normal operation, EN should be kept LOW. Only
the last seven bits serially clocked into the device are
retained within the programming register.
1999 Jun 04
14
Philips Semiconductors
Objective specification
Cordless telephone line interface
Table 1
UBA1706
Register description; note 1
BIT
NAME
FUNCTION
POLARITY
DATA
ADDRESS
STATE AT
POWER-UP
RESET
(AD1, AD0) = (0,0)
0
Register 0: general purpose switches state and DC mask regulation mode
SWC1
SWI1 output connection
SWC2
SWI2 output connection
un
un
CRC
unused
unused
current regulation mode
0: SWI1 switched-off
1: SWI1 switched-on
0: SWI2 switched-off
1: SWI2 switched-on
must be set to logic 0
must be set to logic 0
0: voltage regulation
1: current regulation
D0
D1
0
D2
D3
D4
0
0
0
Register 1: automatic gain control
RAGC1
RAGC2
SAGC
AGC range selection 1
AGC range selection 2
AGC slope selection
AGC
line loss compensation mode
0: 2.7 type slope; note 2
1: 1.9 type slope; note 2
0: AGC inhibited
1: AGC enabled
D0
D1
D2
(AD1, AD0) = (0,1)
D3
0
0
0
0
Register 2
unused, in case of programming register 2 data must be set to: 000100 (D5; D0)
(AD1, AD0) = (1,0)
−
(AD1, AD0) = (1,1)
0
0
Register 3: mute functions and power-down
un
RXM
unused
receive amplifier mute
PD
reduced consumption mode
un
unused
must be set to logic 1
0: amplifier enabled
1: amplifier muted
0: normal operating mode
1: power-down mode
must be set to logic 1
D0
D1
D2
1
D3
0
Notes
1. For full software compatibility, the registers have the same addresses as for the UBA1707.
2. See Section “Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)”.
1999 Jun 04
15
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VCC
supply voltage
GND − 0.4 5.5
V
VLN
positive continuous line voltage on pin LN
GND − 0.4 12.0
V
repetitive line voltage during switch-on or
line interruption
GND − 0.4 13.2
V
continuous
GND − 0.4 12.0
V
during switching
GND − 0.4 13.2
V
GND − 0.4 VCC + 0.4
V
VSWIn
voltage on pins SWI1 and SWI2
Vn(max)
maximum voltage on all other pins
ILN
current sunk by pin LN
see Fig.12
−
150
mA
ISWIn
continuous current sunk by pins SWI1 and
SWI2
bit SWCn = 1
−
20
mA
Ptot
total power dissipation
Tamb = 75 °C; see Fig.12 −
454
mW
Tstg
IC storage temperature
−40
+125
°C
Tamb
ambient temperature
−25
+75
°C
Tj
junction temperature
−
+125
°C
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Jun 04
PARAMETER
CONDITIONS
thermal resistance from junction to ambient in free air
16
VALUE
UNIT
100
K/W
Philips Semiconductors
Objective specification
Cordless telephone line interface
handbook, full pagewidth
UBA1706
FCA036
150
ILN
(mA)
130
(4)
110
(3)
(2)
(1)
90
70
50
30
2
3
4
5
6
7
8
9
(1) Tamb = 45 °C; Ptot = 727 mW
(2) Tamb = 55 °C; Ptot = 636 mW
(3) Tamb = 65 °C; Ptot = 545 mW
(4) Tamb = 75 °C; Ptot = 454 mW
The line current value can be calculated from the ILN value as follows:
I LN × ( R SET + R SLPE ) + V LN – V SLPE
I line = --------------------------------------------------------------------------------------------- where RSET is the resistive part of ZSET.
R SET
Fig.12 Safe operating area.
1999 Jun 04
17
10
11
12.
VLN - VSLPE (V)
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
CHARACTERISTICS
Iline = 15 mA; VCC = 3.3 V; RSLPE = 10 Ω; AGC pin connected to GND; Zline = 600 Ω; ZSET = 619 Ω; EHI = HIGH;
f = 1 kHz; Tamb = 25 °C; bit AGC at logic 1, all other configuration bits at logic 0; measured in test circuit of Fig.14;
unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply (pins VCC and GND; bit PD)
VCC
supply voltage
3.0
−
5.5
V
ICC
current consumption from
pin VCC
−
2.2
3.2
mA
ICC(pd)
current consumption from
pin VCC in power-down mode
bit PD = 1
−
110
150
µA
Line interface (pins LN, SLPE and REG)
DC CHARACTERISTICS
Vref
stabilized voltage between
pins LN and SLPE
Iline = 11 to 140 mA
2.6
2.9
3.2
V
VLN
DC line voltage between pins
LN and GND
Iline = 2 mA
−
1.2
−
V
Iline = 4 mA
−
1.8
−
V
Iline = 15 mA
2.7
3.0
3.3
V
Iline = 140 mA
−
4.35
−
V
VLN(Rext)
DC line voltage between pins
LN and GND with an external
resistor RVA
RVA(SLPE−REG) = 8 kΩ
−
4.5
−
V
∆VLN(T)
DC line voltage variation with
temperature referenced to
25 °C
Tamb = −25 to +75 °C
−
8.0
−
mV
Masks regulation (pins LCC, LVI, CST and RGL; bit CRC)
DC CHARACTERISTICS
ILCC(max)
maximum current sunk by
pin LCC
500
−
−
µA
Rint(LCC)
internal resistance between
pins VCC and LCC
−
165
−
kΩ
bit CRC = 0
−
200
−
nA
Voltage regulation mode
ILVIV
current sourced from pin LVI
Current regulation mode
Iknee
start line current for current
regulation mode
bit CRC = 1
−
35
−
mA
RREGC
DC mask slope in current
regulation mode
Iline > Iknee; RLVI = 1 MΩ;
−
RRGL = 7.15 kΩ; bit CRC = 1
1.4
−
kΩ
−
145
−
mA
Current limitation
Iprot
1999 Jun 04
current limitation level
18
Philips Semiconductors
Objective specification
Cordless telephone line interface
SYMBOL
PARAMETER
UBA1706
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Electronic hook-switch control (pin EHI)
2.3
−
VIH
HIGH-level input voltage
VCC + 0.4
V
VIL
LOW-level input voltage
VCC = 3.0 to 5.5 V
GND − 0.4 −
0.3VCC
V
Ibias
input bias current
input level = HIGH
1
2
5
µA
between pins TXI+ and
GND or TXI− and GND
−
21
−
kΩ
between pins TXI+ and TXI− −
36
−
kΩ
VTXI = 50 mV (RMS)
10.6
11.6
12.6
dB
−
±0.3
−
dB
−
±0.3
−
dB
Transmit amplifier (pins TXI+, TXI− and LN)
Zi
input impedance
Gv(TX)
voltage gain from TXI+/TXI−
to LN
∆Gv(TX)(f)
voltage gain variation with
f = 300 to 3400 Hz
frequency referenced to 1 kHz
∆Gv(TX)(T)
voltage gain variation with
temperature referenced to
25 °C
CMRR
common mode rejection ratio
−
65
−
dB
PSRR
power supply rejection ratio
−
36
−
dB
Tamb = −25 to +75 °C
VLN(max)(rms) maximum sending signal
(RMS value)
Iline = 15 mA; THD = 2%
1.2
1.4
−
V
Iline = 4 mA; THD = 10%
−
0.26
−
V
ViTX(max)(rms) maximum transmit input
voltage (RMS value) for
2% THD on pin LN
Iline = 15 mA
−
0.35
−
V
Iline = 90 mA
−
0.75
−
V
−
−74
−
dBmp
−
21
−
kΩ
Vno(LN)
noise output voltage at pin LN pins TXI+ and TXI−
short-circuited through
200 Ω in series with 10 µF;
psophometrically weighted
(P53 curve)
Receive amplifier (pins RXI and RXO; bit RXM)
Zi
input impedance between
pins RXI and GND
Gv(RX)
voltage gain from RXI to RXO VRXI = 2 mV (RMS)
36.9
37.9
38.9
dB
∆Gv(RX)(f)
voltage gain variation with
f = 300 to 3400 Hz
frequency referenced to 1 kHz
−
±0.2
−
dB
∆Gv(RX)(T)
voltage gain variation with
temperature referenced to
25 °C
−
±0.3
−
dB
PSRR
power supply rejection ratio
THD
total harmonic distortion
1999 Jun 04
Tamb = −25 to +75 °C
−
68
−
dB
VRXI = 2 mV (RMS)
−
0.03
−
%
VRXI = 12.5 mV (RMS)
−
2
−
%
VRXI = 19.5 mV (RMS);
Iline = 90 mA
−
2
−
%
19
Philips Semiconductors
Objective specification
Cordless telephone line interface
SYMBOL
PARAMETER
UBA1706
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Vno(RXO)(rms) noise output voltage at
pin RXO (RMS value)
RXI open-circuit;
psophometrically weighted
(P53 curve)
−
−81
−
dBVp
∆Gv(RX)(m)
VRXI = 10 mV (RMS);
bit RXM = 1
−
80
−
dB
voltage gain reduction from
pin RXI to RXO when muted
Automatic gain control (pin AGC; bits RAGC1, RAGC2, SAGC and AGC)
∆Gv(trx)
gain control range for transmit Iline = 90 mA
and receive amplifiers with
respect to Iline = 15 mA
−
6.5
−
dB
Istart
highest line current for
maximum gain
bits RAGC1 = 1;
RAGC2 = 1
−
22.5
−
mA
bits RAGC1 = 1;
RAGC2 = 0
−
25
−
mA
bits RAGC1 = 0;
RAGC2 = 1
−
27
−
mA
bits RAGC1 = 0;
RAGC2 = 0
−
29.5
−
mA
lowest line current for
minimum gain when
Istart = 23 mA
bits SAGC = 0; RAGC1 = 1;
RAGC2 = 1
−
62
−
mA
bits SAGC = 1; RAGC1 = 1;
RAGC2 = 1
−
43
−
mA
gain variation for transmit and
receive amplifiers when AGC
is off
bit AGC = 0;
Iline = 15 to 140 mA
−
−
±0.2
dB
Istop
∆Gv(trxoff)
Switches (pins SWI1 and SWI2; bits SWC1 and SWC2)
Zi(off)
AC impedance between pins
SWIn and GND when not
selected
bit SWCn = 0
700
−
−
kΩ
Zi(on)
AC impedance between pins
SWIn and GND when
selected
2 mA < ISWIn < 20 mA;
bit SWCn = 1
−
−
30
Ω
2.3
−
VCC + 0.4
V
0.3VCC
V
Serial interface (pins DATA, CLK and EN)
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
VCC = 3 to 5.5 V
Ibias
input bias current
input level = HIGH
Ci
input capacitance at pins
DATA, CLK and EN
1999 Jun 04
20
GND − 0.4 −
1
2
5
µA
−
4
−
pF
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
SERIAL BUS TIMING CHARACTERISTICS
VCC = 3.3 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
Serial programming clock; pin CLK
clock frequency
fclk
0
300
kHz
1
−
µs
Enable programming; pin EN
tSTART
delay to falling clock edge
tEND
delay from last rising clock edge
0.1
−
µs
tW(min)
minimum inactive pulse width
1.5
−
µs
tSU; EN
enable set-up time to next clock edge
0.1
−
µs
Serial data; pin DATA
tSU; DATA
input data to clock set-up time
2
−
µs
tHD; DATA
input data to clock hold time
2
−
µs
tW
handbook, full pagewidth
tSU;DATA
tHD;DATA
tSU;EN
1/fclk
CLK
DATA
D5
D4
AD1
AD0
EN
tEND
tSTART
Fig.13 Serial bus timing diagram.
1999 Jun 04
21
MGK716
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SWI2
17
SWI1
18
EHI
10
DATA EN
11
12
CLK
13
9
15
RXI
220 nF
Cline
100 µF
619 Ω
CEMC
14
7 RXO
UBA1706
10 nF
22
ICC
Zline
VCC
21
600 Ω
VVCC
5
6
LCC
CVCC
3
CST
2
LVI
8
REG
4
AGC
24
RGL
SLPE
TPDARL
MPSA92
10 µF
CLCC
6.8 pF
CCST
RLVI
CLVI
1 MΩ
470 pF
CREG
4.7 µF
RRGL
7.15 kΩ
RSLPE
10 Ω
27 pF
FCA037
RON-HOOK
TNSW
DSW
1N4148
TNON-HOOK
MPSA42
100 kΩ
BUX86
20 kΩ
Dprot
1N4148
UBA1706
Fig.14 Test circuit.
Objective specification
RPD
handbook, full pagewidth
Iline
VRXI
VTXI
TXI−
ZSET
CRXI
Philips Semiconductors
TXI+
GND
19
Cordless telephone line interface
LN
1
TEST AND APPLICATION INFORMATION
1999 Jun 04
from
microcontroller
VLN
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Zbal
3.92 kΩ
260 kΩ
CRXI
100 nF
VLN
Rast3
392 Ω
CRXO
LN
SWI2
1
17
SWI1
RXI
18
9
RXO
7
24
CTXIP
TXI+
SLPE
RSLPE
10 Ω
15
100 nF
10
CTXIM
ZSET
619 Ω
CEMC(3)
10 nF
TXI−
14
11 DATA
UBA1706
100 nF
12
ICC
VCC
23
CVCC
a/b
10 µF
EN
13 CLK
21
VVCC
BRIDGE
4 × BAS11
EHI
5
6
LCC
3
CST
2
LVI
8
REG
4
AGC
M
I
C
R
O
C
O
N
T
R
O
L
L
E
R
Philips Semiconductors
Rast2
Cordless telephone line interface
1999 Jun 04
BZX79C8V2
Rast1
19
RGL
GND
TPDARL
MPSA92
BOD
BR211-240
CLCC(4)
6.8 pF
CCST
RLVI
CLVI(2)
1 MΩ
470 pF
CREG
4.7 µF
RRGL
7.15 kΩ
27pF
b/a
FCA038
RON-HOOK
DSW
1N4148
BUX86
(MPSA42
)
Fig.15 Typical application.
Objective specification
In case of low line current in voltage regulation mode.
Only required in current regulation mode.
To improve EMC performance; necessary for stability.
To improve stability only in current regulation mode.
RPD
20 kΩ
Dprot
1N4148
UBA1706
(1)
(2)
(3)
(4)
(1)
MPSA42
100 kΩ
handbook, full pagewidth
TNSW
TNON-HOOK
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
PACKAGES OUTLINE
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
D
SOT340-1
E
A
X
c
HE
y
v M A
Z
24
13
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
12
bp
e
detail X
w M
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
2.0
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
8.4
8.0
5.4
5.2
0.65
7.9
7.6
1.25
1.03
0.63
0.9
0.7
0.2
0.13
0.1
0.8
0.4
8
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
SOT340-1
1999 Jun 04
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
93-09-08
95-02-04
MO-150AG
24
o
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
If wave soldering is used the following conditions must be
observed for optimal results:
SOLDERING
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
1999 Jun 04
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
25
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3),
SO, SOJ
suitable
suitable(2)
suitable
suitable
suitable
LQFP, QFP, TQFP
not recommended(3)(4)
suitable
SSOP, TSSOP, VSO
not recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 Jun 04
26
Philips Semiconductors
Objective specification
Cordless telephone line interface
UBA1706
NOTES
1999 Jun 04
27
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Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,
Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA,
Tel. +48 22 612 2831, Fax. +48 22 612 2327
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
© Philips Electronics N.V. 1999
SCA 65
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
465008/02/pp28
Date of release: 1999 Jun 04
Document order number:
9397 750 05276