CAT5271 Dual 256-Position I2C Compatible Digital Potentiometer The CAT5271 is a dual 256−position digitally programmable linear taper potentiometer ideally suited for replacing mechanical potentiometers and variable resistors. The wiper settings are controlled through an I2C−compatible digital interface. Upon power−up, the wiper assumes a midscale position and may be repositioned anytime after the power is stable. The device can be programmed to go to a shutdown state during operation. The CAT5271 operates from 2.7 V to 5.5 V, while consuming less than 2 mA. This low operating current, combined with a small package footprint, makes the CAT5271 ideal for battery−powered portable applications. The CAT5271, designed as a pin for pin replacement for the AD5243, is offered in the 10−lead MSOP package and operates over the −40°C to +85°C industrial temperature range. http://onsemi.com MSOP−10 R, Z SUFFIX CASE 846AE MARKING DIAGRAM Features • • • • • • • • • Dual 256−position End−to−End Resistance: 50 kW, 100 kW I2C Compatible Interface Power−on Preset to Midscale Single Supply 2.7 V to 5.5 V Low Temperature Coefficient 100 ppm/°C Low Power, IDD 2 mA max Wide Operating Temperature −40°C to +85°C RoHS−compliant MSOP−10 Package (3 mm x 4.9 mm) 1 1 ANCC = 50 kW ANCE = 100 kW Y = Production Year Y = (Last Digit) M = Production Month M = (1 − 9, A, B, C) R = Revision Typical Applications • Potentiometer Replacement • Transducer Adjustment of Pressure, Temperature, Position, • • ANCE YMR ANCC YMR Chemical, and Optical Sensors RF Amplifier Biasing Gain Control and Offset Adjustment PIN CONNECTIONS B1 1 A1 W2 GND W1 B2 A2 SDA VDD SCL (Top View) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2009 September, 2009 − Rev. 1 1 Publication Order Number: CAT5271/D CAT5271 VCC A1 I2C Interface Wiper Control Register 1 SCL SDA W1 B1 A2 Wiper Control Register 2 W2 B2 GND Figure 1. Functional Block Diagram Table 1. ORDERING INFORMATION Part Number Resistance CAT5271ZI−50−GT3 50 kW CAT5271ZI−00−GT3 100 kW Temperature Range Package Shipping† −40°C to 85°C MSOP−10 (Pb−Free) 3000/Tape & Reel 3000/Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Table 2. PIN FUNCTION DESCRIPTION Pin No. Pin Name Description 1 B1 B1 Terminal 2 A1 A1 Terminal 3 W2 W2 Terminal 4 GND Digital Ground 5 VDD Positive Power Supply 6 SCL Serial Clock Input 7 SDA Serial Data Input / Output 8 A2 A2 Terminal 9 B2 B2 Terminal 10 W1 W1 Terminal Table 3. ABSOLUTE MAXIMUM RATINGS (Note 1) Rating VDD to GND Value Unit −0.3 to 6.5 V A1, B1, W1, A2, B2, W2 Voltage to GND VDD IMAX ±20 mA 0 to 6.5 V −40 to +85 °C 150 °C −65 to +150 °C 300 °C Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJMAX) Storage Temperature Lead Temperature (Soldering, 10 sec) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. http://onsemi.com 2 CAT5271 Table 4. ELECTRICAL CHARACTERISTICS: 50 kW and 100 kW Versions VDD = 2.7 V to 5.5 V; VA = VDD; VB = 0 V; –40°C < TA < +85°C; unless otherwise noted. (Note 2) Test Conditions Symbol Min Typ (Note 3) Max Unit Resistor Differential Nonlinearity (Note 4) RWB, VA = no connection R−DNL −1 ±0.1 +1 LSB Resistor Integral Nonlinearity (Note 4) RWB, VA = no connection R−INL −2 ±0.4 +2 LSB −20 Parameter DC CHARACTERISTICS — RHEOSTAT MODE Nominal Resistor Tolerance (Note 5) TA = 25°C nRAB Resistance Temperature Coefficient VAB = VDD, Wiper = no connection nRAB/nT VDD = 5 V, IW = ±3 mA RW Wiper Resistance +20 100 VDD = 3 V, IW = ±3 mA % ppm/°C 50 120 100 250 W DC CHARACTERISTICS — POTENTIOMETER DIVIDER MODE N Resolution 8 Bits LSB Differential Nonlinearity (Note 6) DNL −1 ±0.1 +1 Integral Nonlinearity (Note 6) INL −1 ±0.4 +1 100 LSB Voltage Divider Temperature Coefficient Code = 0x80 nVW/nT ppm/°C Full−Scale Error Code = 0xFF VWFSE −3 −1 0 LSB Zero−Scale Error Code = 0x00 VWZSE 0 1 3 LSB VA,B,W GND VDD V RESISTOR TERMINALS Voltage Range (Note 7) Capacitance (Note 8) A, B f = 1 MHz, measured to GND, Code = 0 x 80 CA,B 45 pF Capacitance (Note 8) W f = 1 MHz, measured to GND, Code = 0 x 80 CW 60 pF VA = VB = VDD/2 ICM 1 nA Common−Mode Leakage (Note 8) DIGITAL INPUTS Input Logic High VDD = 5 V VIH Input Logic Low VDD = 5 V VIL Input Logic High VDD = 3 V VIH VDD = 3 V VIL 0.3VDD V VIN = 0 V or 5 V IIL ±1 mA 5.5 V Input Logic Low Input Current 0.7 x VDD V 0.3VDD 0.7 x VDD V V POWER SUPPLIES VDD RANGE Power Supply Range Supply Current Power Dissipation (Note 8) Power Supply Sensitivity 2.7 VIH = 5 V or VIL = 0 V IDD 2 mA VIH = 5 V or VIL = 0 V, VDD = 5 V PDISS 0.3 0.2 mW nVDD = +5 V ±10%, Code = Midscale PSS ±0.05 %/% DYNAMIC CHARACTERISTICS (Notes 8 and 10) Bandwidth –3 dB Total Harmonic Distortion VW Settling Time (50 kW/100 kW) RAB = 50 kW / 100 kW, Code = 0x80 BW 100/40 kHz VA =1 V rms, VB = 0 V, f = 1 kHz, RAB = 10 kW THDW 0.05 % VA = 5 V, VB = 0 V, ±1 LSB error band tS 2 ms 2. VA applies to both A1 and A2, VB applies to both B1 and B2. 3. Typical specifications represent average readings at +25°C and VDD = 5 V. 4. Resistor position nonlinearity error R−INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R−DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 5. VAB = VDD, Wiper (VW) = no connect. 6. INL and DNL are measured at VW with the digital potentiometer configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 7. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 8. Guaranteed by design and not subject to production test. 9. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance. 10. All dynamic characteristics use VDD = 5 V. http://onsemi.com 3 CAT5271 Table 5. CAPACITANCE TA = 25°C, f = 1.0 MHz, VDD = 5 V Symbol CI/O (Note 11) Test Input/Output Capacitance (SDA, SCL) Conditions Max Units VI/O = 0V 8 pF Max Units Table 6. POWER UP TIMING (Notes 11 and 12) Symbol Parameter tPUR Power−up to Read Operation 1 ms tPUW Power−up to Write Operation 1 ms Max Units Wiper Response Time After Power Supply Stable 50 ms Wiper Response Time: SCL falling edge after last bit of wiper position data byte to wiper change 20 ms Max Units 400 kHz 11. This parameter is tested initially and after a design or process change that affects the parameter. 12. tPUR and t PUW are delays required from the time VCC is stable until the specified operation can be initiated. Table 7. DIGITAL POTENTIOMETER TIMING Symbol tWRPO tWR Parameter Min Table 8. A.C. CHARACTERISTICS VDD = +2.7 V to +5.5 V, −40°C to +85°C unless otherwise specified. Symbol Parameter Min Typ fSCL Clock Frequency tHIGH Clock High Period 600 ns tLOW Clock Low Period 1300 ns tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 600 ns tHD:STA Start Condition Hold Time 600 ns tSU:DAT Data in Setup Time 100 ns tHD:DAT Data in Hold Time 0 ns tSU:STO Stop Condition Setup Time 600 ns Time the bus must be free before a new transmission can start 1300 ns tBUF tR SDA and SCL Rise Time 300 ns tF SDA and SCL Fall Time 300 ns tDH Data Out Hold Time 100 ns TI Noise Suppression Time Constant at SCL, SDA Inputs 50 ns tAA SCL Low to SDA Data Out and ACK Out 1 ms http://onsemi.com 4 CAT5271 TYPICAL CHARACTERISTICS 0.03 0.1 0.02 0 DNL ERROR (LSB) ERROR (LSB) 0.01 0 −0.01 −0.02 −0.1 INL −0.2 −0.3 −0.03 −0.4 −0.04 −0.05 0 32 64 96 128 160 192 224 −0.5 256 0 32 64 96 128 160 192 TAP TAP Figure 2. Differential Non−Linearity, VDD = 5.6 V Figure 3. Integral Non−Linearity, VDD = 5.6 V 120 6 100 5 224 256 5.6 V VDD = 2.6 V 4.0 V Vw (V) 60 3.3 V 3 40 3.3 V 2 20 0 5.0 V 4 5.6 V 4.0 V 0 50 100 VDD = 2.6 V 1 150 200 0 250 0 52 104 156 TAP TAP Figure 4. Wiper Resistance at Room Temperature Figure 5. Wiper Voltage 400 350 T = 90°C 300 ISB (nA) Rw (W) 80 T = −45°C 250 T = 25°C 200 150 100 2 3 4 5 VDD (V) Figure 6. Standby Current http://onsemi.com 5 6 208 260 CAT5271 TYPICAL CHARACTERISTICS 0.4 102.15 102.10 102.05 0.2 D (%) R (kW) 102.00 101.95 101.90 0 101.85 101.80 −0.2 −50 −20 10 40 70 101.75 −50 100 −20 10 40 70 TEMPERATURE (°C) TEMPERATURE (°C) Figure 7. Change in End−to−End Resistance Figure 8. End−to−End Resistance vs. Temperature 0 100 30 −6 25 VDD = 5 V PSRR (dB) A (dB) −12 VDD = 3 V −18 −24 −30 −36 20 VDD = 5 V 15 VDD = 3 V 10 5 1 10 100 1000 0 1 10 100 f (KHz) f (KHz) Figure 9. Gain vs. Bandwidth (Tap 0x80) Figure 10. PSRR http://onsemi.com 6 1000 CAT5271 Basic Operation The CAT5271 is a dual 256−position digitally controlled potentiometer. When power is first applied, the wipers assume a mid−scale position. Once the power supply is stable, the wipers may be repositioned via the I2C compatible interface. The equation for determining the digitally programmed output resistance between W and B is R WB + D R AB ) R W 256 where D is the decimal equivalent of the binary code loaded in the 8−bit Wiper register, RAB is the end−to−end resistance, and RW is the wiper resistance contributed by the on resistance of the internal switch. In summary, if RAB = 100 kW and the A terminal is open circuited, the following output resistance RWB will be set for the indicated Wiper register codes: Programming: Variable Resistor Rheostat Mode The resistance between terminals A and B, RAB, has a nominal value of 50 kW or 100 kW and has 256 contact points accessed by the wiper terminal, plus the B terminal contact. Data in the 8−bit Wiper register is decoded to select one of these 256 possible settings. The wiper’s first connection is at the B terminal, corresponding to control position 0x00. Ideally this would present a 0 W between the Wiper and B, but just as with a mechanical rheostat there is a small amount of contact resistance to be considered, there is a wiper resistance comprised of the RON of the FET switch connecting the wiper output with its respective contact point. In CAT5271 this ‘contact’ resistance is typically 50 W. Thus a connection setting of 0x00 yields a minimum resistance of 50 W between terminals W and B. For a 100 kW device, the second connection, or the first tap point, corresponds to 441 W (RWB = RAB/256 + RW = 390.6 + 50 W) for data 0x01. The third connection is the next tap point, is 831 W (2 x 390.6 + 50 W) for data 0x02, and so on. Figure 11 shows a simplified equivalent circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. Table 9. CODES AND CORRESPONDING RWB RESISTANCE FOR RAB = 100 kW, VDD = 5 V RS RWB (W) Output State 255 99,559 Full Scale (RAB – 1 LSB + RW) 128 50,050 Midscale 1 441 1 LSB 0 50 Zero Scale (Wiper Contact Resistance) R WA(D) + 256 * D R AB ) R W 256 RS (eq. 2) For RAB = 100 kW and the B terminal open circuited, the following output resistance RWA will be set for the indicated Wiper register codes. RS Table 10. CODES AND CORRESPONDING RWA RESISTANCE FOR RAB = 100 kW, VDD = 5 V W RS D (Dec.) Be aware that in the zero−scale position, the wiper resistance of 50 W is still present. Current flow between W and B in this condition should be limited to a maximum pulsed current of no more than 20 mA. Failure to heed this restriction can cause degradation or possible destruction of the internal switch contact. Similar to the mechanical potentiometer, the resistance of the DPP (Digitally Programmed Potentiometer) between the wiper W and terminal A also produces a digitally controlled complementary resistance RWA. When these terminals are used, the B terminal can be opened. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is A Wiper Register and Decoder (eq. 1) B Figure 11. CAT5271 Equivalent DPP Circuit D (Dec.) RWA (W) Output State 255 441 Full Scale 128 50,050 Midscale 1 99,659 1 LSB 0 100,050 Zero Scale Typical device to device resistance matching is lot dependent and may vary by up to ±20%. http://onsemi.com 7 CAT5271 ESD Protection Power−up Sequence Digital Input Because ESD protection diodes limit the voltage compliance at terminals A, B, and W (see Figure 12), it is recommended that VDD/GND be powered before applying any voltage to terminals A, B, and W. The ideal power−up sequence is: GND, VDD, digital inputs, and then VA/B/W. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD/GND. LOGIC GND Power Supply Bypassing Good design practice employs compact, minimum lead length layout design. Leads should be as direct as possible. It is also recommended to bypass the power supplies with quality low ESR Ceramic chip capacitors of 0.01 mF to 0.1 mF. Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors can also be applied at the supplies to suppress transient disturbances and low frequency ripple. As a further precaution digital ground should be joined remotely to the analog ground at one point to minimize the ground bounce. W, A, B Potentiometer GND VDD Figure 12. ESD Protection Networks VDD C3 10 mF Terminal Voltage Operating Range The CAT5271 VDD and GND power supply define the limits for proper 3−terminal digital potentiometer operation. Signals or potentials applied to terminals A, B or the wiper must remain inside the span of VDD and GND. Signals which attempt to go outside these boundaries will be clamped by the internal forward biased diodes. + C1 0.1 mF CAT5271 GND Figure 14. Power Supply Bypassing VDD W, A, B CAT5271 LOGIC GND Figure 13. http://onsemi.com 8 CAT5271 I2C Bus Protocol is logic high, then a Read instruction is performed. If the bit is logic low, then the Write command is executed. After the Master sends a START condition and the slave address byte, the CAT5271 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address. The following defines the features of the I2C bus protocol: 1. Data transfer may be initiated only when the bus is not busy. 2. During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5271 will be considered a slave device in all applications. Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT5271 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8−bit byte. When the CAT5271 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5271 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. START Condition The START condition precedes all commands to the device, and is defined as a high to low transition of SDA when SCL is high. The CAT5271 monitors the SDA and SCL lines and will not respond until this condition is met. STOP Condition A low to high transition of SDA when SCL is high determines the STOP condition. All operations must end with a STOP condition. Write Operation In the Write mode, the Master device sends the START condition and the slave address information to the Slave device. After the Slave generates an acknowledge, the Master sends the instruction byte. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the wiper register. The CAT5271 acknowledges once more and the Master generates the STOP condition. Device Addressing The bus Master begins a transmission by sending a START condition. The Master then sends the address of the particular slave device it is requesting. The seven most significant bits of the 8−bit slave address are fixed as 0101111 for the CAT5271. The next bit (R/W) selects between the type of the instruction Read or Write. If the bit tHIGH tF tLOW tR tLOW SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH SDA OUT Figure 15. Bus Timing Diagram http://onsemi.com 9 tBUF CAT5271 SDA SCL START CONDITION STOP CONDITION Figure 16. Start/Stop Condition SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE Figure 17. Acknowledge Condition http://onsemi.com 10 CAT5271 INSTRUCTION AND REGISTER DESCRIPTION The remainder of the bits in the instruction byte are don’t care bits. SLAVE ADDRESS BYTE The first byte sent to the CAT5271 from the master/processor is called the Slave Address Byte. The most significant seven bits of the slave address are a device type identifier. For the CAT5271, these bits are fixed at 0101111. The following bit (R/W) selects between a Read or a Write operation. If the bit is logic high, then a Read instruction is performed. If the bit is low, then the Write command is executed. Read Operation In the read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences. There is no potentiometer channel selection bit in the Read command. The addressed channel is the one that is previously selected in the write mode. If it desired to read the potentiometer wiper register values of both channels, the first potentiometer must be addressed in write mode and then change to read mode to read the first channel value. After that, the user must return the device to write mode with the second potentiometer selected and read the second potentiometer wiper register value in read mode. It is not necessary for users to issue the third data byte in write mode for subsequent read operation. INSTRUCTION BYTE Write and Read instructions are respectively three and two bytes in length. The basic sequence of the two instructions is illustrated in Table 11 and 12. Write Operation In the write instruction, the second byte first bit (A0) selects between the potentiometer 1 and 2: a logic low is for the potentiometer 1, and a logic high is for potentiometer 2. The following bit (SD) is the shutdown bit. A logic high causes an open circuit at terminal A while shorting the wiper terminal W to terminal B. The “shutdown” operation does not change the contents of the wiper register. When the shutdown bit, SD, goes back to a logic low, the previous wiper position is restored. Also during shutdown, new settings can be programmed. As soon as the device is returned from shutdown, the wiper position is set according to the wiper register value. Wiper Control The CAT5271 contains two 8−bit Wiper Control Register (WCR). The Wiper Control Register output is decoded to select one of 256 switches along its resistor array. The contents of the WCR may be written by the host via Write instruction. The Wiper Control Registers are a volatile register that loses its contents when the CAT5271 is powered−down. Upon power−up, the wiper is set to midscale and may be repositioned anytime after the power has become stable. Table 11. Write S 0 1 0 1 1 1 1 W A A0 SD Slave Address Byte X X X X X X A D7 D6 D5 Instruction Byte D4 D3 D2 D1 D0 D2 D1 D0 A P Data Byte SDA 0 S T A R T 1 0 1 1 1 1 SD A0 R/W X X X X D7 X X A C K D6 D5 D4 D3 A S C T K O P A C K Slave Address Byte Instruction Byte Data Byte Table 12. READ S 0 1 0 1 1 1 1 R A D7 D6 D5 Slave Address Byte SDA S T A R T 0 1 0 1 1 D4 D3 D2 D1 D0 D2 D1 D0 A P N A C K S T O P Data Byte 1 1 R/W D7 D6 D5 D4 D3 A C K Slave Address Byte Data Byte Legend S= P= A= D= R= W= Start Stop Acknowledge Data bit Read (bit is 1 for Read instruction) A0 = Potentiometer Channel (1 or 2) Select Bit SD = Shut Down: 0: normal operation 1: wiper is parked at B terminal and terminal A is open circuit. X = Don’t Care Write (bit is 0 for Write instruction) http://onsemi.com 11 CAT5271 PACKAGE DIMENSIONS MSOP 10, 3x3 CASE 846AE−01 ISSUE O SYMBOL MIN NOM A E E1 MAX 1.10 A1 0.00 0.05 0.15 A2 0.75 0.85 0.95 b 0.17 0.27 c 0.13 0.23 D 2.90 3.00 3.10 E 4.75 4.90 5.05 E1 2.90 3.00 3.10 0.50 BSC e L 0.40 0.60 L1 0.95 REF L2 0.25 BSC θ 0º 0.80 8º TOP VIEW DETAIL A D A A2 A1 e b c SIDE VIEW END VIEW q L2 Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-187. L L1 DETAIL A http://onsemi.com 12 CAT5271 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: [email protected] N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 13 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative CAT5271/D