a I2C®-Compatible 256-Position Digital Potentiometers AD5241/AD5242 FEATURES 256 Position 10 k, 100 k, 1 M Low Tempco 30 ppm/C Internal Power ON Midscale Preset Single Supply 2.7 V to 5.5 V or Dual Supply 2.7 V for AC or Bipolar Operation I2C-Compatible Interface with Reaback Capability Extra Programmable Logic Outputs APPLICATIONS Multimedia, Video and Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Line Impedance Matching FUNCTIONAL BLOCK DIAGRAM A1 Wiper position programming defaults to midscale at system power ON. Once powered, the VR wiper position is programmed by an I2C-compatible 2-wire serial data interface. Both parts have available two extra programmable logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system. O1 O2 AD5241 SHDN VDD RDAC REGISTER 1 REGISTER 2 VSS ADDR DECODE SDA SCL GND 8 SERIAL INPUT REGISTER AD0 A1 GENERAL DESCRIPTION The AD5241/AD5242 provides a single-/dual-channel, 256position digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. For AD5242, the fixed A-to-B terminal resistance of 10 kΩ, 100 kΩ or 1 MΩ has a 1% channel-to-channel matching tolerance. Nominal temperature coefficient of both parts is 30 ppm/°C. W1 B1 PWR-ON RESET AD1 W1 B1 A2 W2 B2 SHDN O1 O2 REGISTER VDD RDAC REGISTER 1 RDAC REGISTER 2 VSS ADDR DECODE AD5242 1 SDA SCL GND 8 SERIAL INPUT REGISTER AD0 PWR-ON RESET AD1 The AD5241/AD5242 is available in surface-mount (SO-14/-16) packages and, for ultracompact solutions, TSSOP-14/-16 packages. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C. For 3-wire, SPI-compatible interface applications, please refer to AD5200, AD5201, AD5203, AD5204, AD5206, AD5231*, AD5232*, AD5235*, AD7376, AD8400, AD8402, and AD8403 products. *Nonvolatile digital potentiometer. I2C is a registered trademark of Philips Corporation. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 AD5241/AD5242–SPECIFICATIONS 10 k, 100 k, 1 M VERSION Parameter Symbol (VDD = 3 V 10% or 5 V 10%, VA = +VDD, VB = 0 V, –40C < TA < +85C unless otherwise noted.) Conditions DC CHARACTERISTICS, RHEOSTAT MODE (Specifications apply to all VRs.) Resistor Differential Nonlinearity 2 R-DNL RWB, VA = NC Resistor Integral Nonlinearity2 R-INL RWB, VA = NC Nominal Resistor Tolerance ∆R TA = 25°C, RAB = 10 kΩ ∆R TA = 25°C, RAB = 100 kΩ/1 MΩ Resistance Temperature Coefficient RAB/∆T VAB = VDD, Wiper = No Connect Wiper Resistance RW IW = VDD /R, VDD = 3 V or 5 V DC CHARACTERISTICS, POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.) Resolution N Differential Nonlinearity3 DNL Integral Nonlinearity3 INL Voltage Divider Temperature Coefficient ∆VW/∆T Code = 80H Full-Scale Error VWFSE Code = FFH Zero-Scale Error VWZSE Code = 00H RESISTOR TERMINALS Voltage Range4 Capacitance5 A, B Capacitance5 W Common-Mode Leakage VA, B, W CA, B CW ICM DIGITAL INPUTS Input Logic High (SDA and SCL) Input Logic Low (SDA and SCL) Input Logic High (AD0 and AD1) Input Logic Low (AD0 and AD1) Input Logic High Input Logic Low Input Current Input Capacitance5 VIH VIL VIH VIL VIH VIL IIL CIL DIGITAL OUTPUT Output Logic Low (SDA) Output Logic Low (O1 and O2) Output Logic High (O1 and O2) Three-State Leakage Current (SDA) Output Capacitance5 VOL VOL VOL VOH IOZ COZ IOL = 3 mA IOL = 6 mA ISINK = 1.6 mA ISOURCE = 40 µA VIN = 0 V or 5 V POWER SUPPLIES Power Single-Supply Range Power Dual-Supply Range Positive Supply Current Negative Supply Current Power Dissipation6 Power Supply Sensitivity VDD RANGE VDD/SS RANGE IDD ISS PDISS PSS VSS = 0 V Total Harmonic Distortion BW_10 kΩ BW_100 kΩ BW_1 MΩ THDW VW Settling Time tS Resistor Noise Voltage eN_WB RAB = 10 kΩ, Code = 80H RAB = 100 kΩ, Code = 80H RAB = 1 MΩ, Code = 80H VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz VA = VDD, VB = 0 V, ± 1 LSB Error Band, RAB = 10 kΩ RWB = 5 kΩ, f = 1 kHz DYNAMIC CHARACTERISTICS5, 7, 8 Bandwidth –3 dB Min Typ1 Max Unit –1 –2 –30 –30 ± 0.4 ± 0.5 +1 +2 +30 +50 LSB LSB % % ppm/°C Ω 30 60 8 –1 –2 –1 0 ± 0.4 ± 0.5 5 –0.5 0.5 VSS f = 1 MHz, Measured to GND, Code = 80H f = 1 MHz, Measured to GND, Code = 80H VA = VB = VW VDD = 5 V VDD = 5 V VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 120 +1 +2 0 1 VDD V pF pF nA VDD + 0.5 +0.3 VDD VDD 0.8 VDD 0.6 1 V V V V V V µA pF 0.4 0.6 0.4 V V V V µA pF 45 60 1 0.7 VDD –0.5 2.4 0 2.1 0 3 4 3 2.7 ± 2.3 VIH = 5 V or VIL = 0 V VSS = –2.5 V, VDD = +2.5 V VIH = 5 V or VIL = 0 V, VDD = 5 V –0.01 –2– Bits LSB LSB ppm/°C LSB LSB ±1 8 5.5 ± 2.7 0.1 50 +0.1 –50 0.5 250 +0.002 +0.01 V V µA µA µW %/% 650 69 6 0.005 kHz kHz kHz % 2 µs 14 nV√Hz REV. A AD5241/AD5242 Parameter Symbol Conditions Min Typ1 Max Unit 400 kHz µs 5, 9 INTERFACE TIMING CHARACTERISTICS (Applies to all parts. ) SCL Clock Frequency fSCL tBUF Bus Free Time Between t1 STOP and START tHD; STA Hold Time (Repeated START) t2 After this period the first clock pulse is generated. tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU; STA Setup Time for START Condition t5 t6 tHD; DAT Data Hold Time tSU; DAT Data Setup Time t7 tR Rise Time of Both t8 SDA and SCL Signals tF Fall Time of Both SDA and SCL Signals t9 tSU; STO Setup Time for STOP Condition t10 0 1.3 600 1.3 0.6 600 ns 300 µs µs ns ns ns ns 300 ns 50 900 100 NOTES 1 Typicals represent average readings at 25°C, VDD = 5 V. 2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 10 test circuit. 3 INL and DNL are measured at V W with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V A = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 9 test circuit. 4 Resistor terminals A, B, W have no limitations on polarity with respect to each other. 5 Guaranteed by design and not subject to production test. 6 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation. 7 Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 8 All dynamic characteristics use V DD = 5 V. 9 See timing diagram for location of measured values. Specifications subject to change without notice. REV. A –3– AD5241/AD5242 Thermal Resistance θJA SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W SOIC (SO-16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W Maximum Junction Temperature (TJ max) . . . . . . . . . . 150°C Package Power Dissipation PD = (TJ max – TA)/θJA Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperatures R-14, R-16, RU-14, RU-16 (Vapor Phase, 60 sec) . . 215°C R-14, R-16, RU-14, RU-16 (Infrared, 15 sec) . . . . . . 220°C ABSOLUTE MAXIMUM RATINGS * (TA = 25°C, unless otherwise noted) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 , +7 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V , –7 V VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD AX–BX, AX–WX, BX–WX at 10 kΩ in TSSOP-14 . . . ± 5.0 mA* AX–BX, AX–WX, BX–WX at 100 kΩ in TSSOP-14 . . ± 1.5 mA* AX–BX, AX–WX, BX–WX at 1 MΩ in TSSOP-14 . . . ± 0.5 mA* Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . 0 V, 7 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C *Max Current increases at lower resistance and different packages. ORDERING GUIDE Model Number of Channels End to End RAB () Temperature Range (C) Package Description Package Option #Devices per Container AD5241BR10 AD5241BR10-REEL7 AD5241BRU10-REEL7 AD5241BR100 AD5241BR100-REEL7 AD5241BRU100-REEL7 AD5241BR1M AD5241BR1M-REEL7 AD5241BRU1M-REEL7 AD5242BR10 AD5242BR10-REEL7 AD5242BRU10-REEL7 AD5242BR100 AD5242BR100-REEL7 AD5242BRU100-REEL7 AD5242BR1M AD5242BR1M-REEL7 AD5242BRU1M-REEL7 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 10 k 10 k 10 k 100 k 100 k 100 k 1M 1M 1M 10 k 10 k 10 k 100 k 100 k 100 k 1M 1M 1M –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 –40 to +85 SO-14 SO-14 TSSOP-14 SO-14 SO-14 TSSOP-14 SO-14 SO-14 TSSOP-14 SO-16 SO-16 TSSOP-16 SO-16 SO-16 TSSOP-16 SO-16 SO-16 TSSOP-16 R-14 R-14 RU-14 R-14 R-14 RU-14 R-14 R-14 RU-14 R-16A R-16A RU-16 R-16A R-16A RU-16 R-16A R-16A RU-16 56 1000 1000 56 1000 1000 56 1000 1000 48 1000 1000 48 1000 1000 48 1000 1000 NOTES 1. The AD5241/AD5242 die size is 69 mil × 78 mil, 5,382 sq. mil. Contains 386 transistors for each channel. Patent Number 5495245 applies. 2. TSSOP packaged units are only available in 1,000-piece quantity Tape and Reel. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5241/AD5242 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– WARNING! ESD SENSITIVE DEVICE REV. A AD5241/AD5242 AD5241 PIN CONFIGURATION AD5242 PIN CONFIGURATION A1 1 14 O1 O1 1 16 A2 W1 2 13 NC A1 2 15 W2 B1 3 12 O2 W1 3 11 VSS B1 4 10 DGND SCL 6 9 AD1 SHDN 6 SDA 7 8 AD0 SCL 7 10 AD1 SDA 8 9 VDD 4 SHDN 5 AD5241 TOP VIEW (Not to Scale) 14 B2 AD5242 13 O2 TOP VIEW VDD 5 (Not to Scale) 12 VSS NC = NO CONNECT AD5241 PIN FUNCTION DESCRIPTIONS 11 DGND AD0 AD5242 PIN FUNCTION DESCRIPTIONS Pin Mnemonic Description Pin Mnemonic Description 1 2 3 4 A1 W1 B1 VDD 1 2 3 4 5 SHDN O1 A1 W1 B1 VDD 5 Resistor Terminal A1 Wiper Terminal W1 Resistor Terminal B1 Positive power supply, specified for operation from 2.2 V to 5.5 V. Active low, asynchronous connection of the Wiper W to Terminal B, and open circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD if not used. Serial Clock Input Serial Data Input/Output Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Common Ground Negative power supply, specified for operation from 0 V to –2.7 V. Logic Output Terminal O2 No Connect Logic Output Terminal O1 6 SHDN 7 8 9 SCL SDA AD0 10 AD1 11 12 DGND VSS 13 14 15 16 O2 B2 W2 A2 Logic Output Terminal O1 Resistor Terminal A1 Wiper Terminal W1 Resistor Terminal B1 Positive power supply, specified for operation from 2.2 V to 5.5 V. Active low, asynchronous connection of the Wiper W to Terminal B, and open circuit of Terminal A. RDAC register contents unchanged. SHDN should tie to VDD if not used. Serial Clock Input Serial Data Input/Output Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Programmable address bit for multiple package decoding. Bits AD0 and AD1 provide four possible addresses. Common Ground Negative power supply, specified for operation from 0 V to –2.7 V. Logic Output Terminal O2 Resistor Terminal B2 Wiper Terminal W2 Resistor Terminal A2 6 7 8 SCL SDA AD0 9 AD1 10 11 DGND VSS 12 13 14 O2 NC O1 REV. A –5– AD5241/AD5242 t8 SDA t1 t8 t9 t2 SCL t4 t2 P t3 S t7 t5 t 10 S t6 P Figure 1. Detail Timing Diagram Data of AD5241/AD5242 is accepted from the I2C bus in the following serial format: S 0 1 0 1 1 AD1 AD0 R/W A/B RS A SD SLAVE ADDRESS BYTE O1 O2 X X X A D7 D6 D5 INSTRUCTION BYTE D4 D3 D2 D1 D0 A P DATA BYTE where: S = Start Condition P = Stop Condition A = Acknowledge X = Don’t Care AD1, AD0 = Package pin programmable address bits. Must be matched with the logic states at pins AD1 and AD0. R/W = Read Enable at High and output to SDA. Write Enable at Low. A/B = RDAC sub address select. ‘0’ for RDAC1 and ‘1’ for RDAC2. RS = Midscale reset, active high. SD = Shutdown in active high. Same as SHDN except inverse logic. O1, O2 = Output logic pin latched values. D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits. 9 1 1 9 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 A/B R/W RS SD O1 O2 X X X ACK BY AD5241 START BY MASTER D7 D6 D5 D4 D3 D2 ACK BY AD5241 FRAME 1 SLAVE ADDRESS BYTE FRAME 2 INSTRUCTION BYTE FRAME 3 DATA BYTE D1 D0 ACK BY AD5241 STOP BY MASTER Figure 2. Writing to the RDAC Serial Register 9 1 1 9 SCL SDA 0 1 0 1 1 AD1 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0 ACK BY AD5241 START BY MASTER NO ACK BY MASTER STOP BY FRAME 2 MASTER DATA BYTE FROM PREVIOUSLY SELECTED RDAC REGISTER IN WRITE MODE FRAME 1 SLAVE ADDRESS BYTE Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode –6– REV. A Typical Performance Characteristics–AD5241/AD5242 0.50 VDD = 2.7V VDD = 5.5V VDD = 2.7V 0.5 VDD /VSS = 2.7V/0V 0 –0.5 VDD = 2.7V VDD = 5.5V VDD = 2.7V POTENTIOMETER MODE INTEGRAL NONLINEARITY – LSB RHEOSTAT MODE DIFFERENTIAL NONLINEARITY – LSB 1 VDD /VSS = 5.5V/0V, 2.7V 0.25 VDD /VSS = 2.7V 0.00 VDD /VSS = 2.7V/0V, 5.5V/0V –0.25 –1 –0.50 0 32 64 96 128 160 CODE – Decimal 192 224 256 0 32 128 160 192 224 256 TPC 4. INL vs. Code 10000 1 VDD = 2.7V TA = 25C VDD /VSS = 2.7V/0V NOMINAL RESISTANCE – k VDD = 2.7V VDD = 5.5V VDD = 2.7V 0.5 0 VDD /VSS = 5.5V/0V, 2.7V –0.5 0 32 64 96 128 160 192 224 1M 1000 100k 100 10k 10 1 –40 –1 256 –20 0 CODE – Decimal TPC 2. RINL vs. Code 20 40 TEMPERATURE – C 80 60 TPC 5. Nominal Resistance vs. Temperature 10000 0.25 VDD = 2.7V VDD = 5.5V VDD = 2.7V IDD - SUPPLY CURRENT – A POTENTIOMETER MODE DIFFERENTIAL NONLINEARITY – LSB 96 CODE – Decimal TPC 1. RDNL vs. Code RHEOSTAT MODE INTEGRAL NONLINEARITY – LSB 64 0.13 VDD /VSS = 2.7V/0V, 5.5V/0V, 2.7V 0.00 –0.13 VDD = 5V 1000 VDD = 3V 100 10 VDD = 2.5V 1 –0.25 0 32 64 96 128 160 192 224 0 256 CODE – Decimal TPC 3. DNL vs. Code REV. A 1 2 3 INPUT LOGIC VOLTAGE – V 4 TPC 6. Supply Current vs. Logic Input Voltage –7– 5 AD5241/AD5242 100 0.1 RAB = 10k VDD = 5.5V TA = 25C 90 WIPER RESISTANCE – SHUTDOWN CURRENT – A 80 0.01 VDD /VSS = 2.7V/0V 70 60 50 VDD /VSS = 2.7V/0V 40 30 VDD /VSS = 5.5V/0V 20 0.001 –40 0 –20 40 20 60 10 –3 80 –2 –1 TPC 7. Shutdown Current vs. Temperature 2 3 4 5 6 300 VDD /VSS = 2.7V/0V TA = 25C 60 10M VERSION A – VDD /VS S = 5.5V/0V CODE = FF 250 50 IDD – SUPPLY CURRENT A POTENTIOMETER MODE TEMPCO – ppm/ C 1 TPC 10. Incremental Wiper Contact vs. VDD/VSS 70 10k VERSION 40 100k VERSION 30 20 10 0 D B – VDD /VSS = 3.3V/0V CODE = FF 200 A C – VDD /VSS = 2.5V/0V CODE = FF 150 D – VDD /VSS = 5.5V/0V CODE = 55 E – VDD /VSS = 3.3V/0V CODE = 55 100 E B F – VDD /VSS = 2.5V/0V CODE = 55 –10 50 F C –20 –30 0 16 32 48 64 80 96 112 0 10 128 100 FREQUENCY – kHz CODE – Decimal TPC 8. ⌬VWB/⌬T Potentiometer Mode Tempco 1000 TPC 11. Supply Current vs. Frequency 6 120 VDD /VSS = 2.7V/0V TA = 25C 100 100k VERSION FFH 0 80 –6 60 –12 40 –18 GAIN – dB RHEOSTAT MODE TEMPCO – ppm/ C 0 COMMON MODE – Volts TEMPERATURE – C 20 0 80H 40H 20H 10H –24 08H –30 04H –20 –36 02H 10k VERSION –42 –40 01H 10M VERSION –48 –60 –54 100 –80 0 16 32 48 64 80 96 112 128 CODE – Decimal TPC 9. ⌬RWB/⌬T Rheostat Mode Tempco 1k 10k FREQUENCY – Hz 100k 1M TPC 12. AD5242 10 kΩ Gain vs. Frequency vs. Code –8– REV. A AD5241/AD5242 6 6 FFH 0 80H –6 GAIN – dB GAIN – dB 10H –24 08H –30 04H –36 40H –12 20H –18 80H –6 40H –12 FFH 0 20H –18 10H –24 08H –30 04H –36 02H –42 02H –42 01H –48 01H –48 –54 100 1k 10k FREQUENCY – Hz –54 100 100k TPC 13. AD5242 100 kΩ Gain vs. Frequency vs. Code OPERATION The AD5241/AD5242 provides a single-/dual-channel, 256position digitally controlled variable resistor (VR) device. The terms VR, RDAC, and programmable resistor are commonly used interchangeably to refer to digital potentiometer. To program the VR settings, refer to the Digital Interface section. Both parts have an internal power ON preset that places the wiper in midscale during power-on, which simplifies the fault condition recovery at power-up. In addition, the shutdown SHDN pin of AD5241/AD5242 places the RDAC in an almost zero power consumption state where Terminal A is open circuited and the Wiper W is connected to Terminal B, resulting in only leakage current being consumed in the VR structure. During shutdown, the VR latch contents are maintained when the RDAC is inactive. When the part is returned from shutdown, the stored VR setting will be applied to the RDAC. A SHDN SWSHDN D7 D6 D5 D4 D3 D2 D1 D0 R N SW 2–1 R N SW 2–2 RDAC LATCH & DECODER PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation The nominal resistance of the RDAC between Terminals A and B are available in 10 kΩ, 100 kΩ, and 1 MΩ. The final two or three digits of the part number determine the nominal resistance value, e.g. 10 kΩ = 10; 100 kΩ = 100; 1 MΩ = 1 M. The nominal resistance (RAB) of the VR has 256 contact points accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assume a 10 kΩ part is used; the wiper’s first connection starts at the B terminal for data 00H. Since there is a 60 Ω wiper contact resistance, such connection yields a minimum of 60 Ω resistance between terminals W and B. The second connection is the first tap point corresponds to 99 Ω (RWB = RAB /256 + RW = 39 + 60) for data 01H. The third connection is the next tap point representing 138 Ω (39 × 2 + 60) for data 02H and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10021 Ω [RAB – 1 LSB + RW]. Figure 4 shows a simplified diagram of the equivalent RDAC circuit where the last resistor string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance. RWB ( D ) = D × R AB + RW 256 (1) where: R RAB /2N D SW0 B 100k The general equation determining the digitally programmed resistance between W and B is: SW1 R 10k FREQUENCY – Hz TPC 14. AD5242 1 MΩ Gain vs. Frequency vs. Code W R 1k is the decimal equivalent of the binary code between 0 and 255 which is loaded in the 8-bit RDAC register. RAB is the nominal end-to-end resistance. DIGITAL CIRCUITRY OMITTED FOR CLARITY RW is the wiper resistance contributed by the on-resistance of the internal switch. Figure 4. AD5241/AD5242 Equivalent RDAC Circuit Again, if RAB = 10 kΩ and A terminal can be either open circuit or tied to W, the following output resistance at RWB will be set for the following RDAC latch codes. REV. A –9– AD5241/AD5242 which can be simplified to D (DEC) RWB () Output State 255 128 1 0 10021 5060 99 60 Full-Scale (RWB – 1 LSB + RW) Midscale 1 LSB Zero-Scale (Wiper Contact Resistance) Note that in the zero-scale condition a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum current of no more than ± 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. Output State 255 128 1 0 99 5060 10021 10060 Full-Scale Midscale 1 LSB Zero-Scale where D is decimal equivalent of the binary code between 0 to 255 which is loaded in the 8-bit RDAC register. For more accurate calculation including the effects of wiper resistance, VW can be found as: VW (D )= DIGITAL INTERFACE 2-Wire Serial Bus The 2-wire I2C serial bus protocol operates as follows: 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high, Figure 2. The following byte is the Slave Address Byte, Frame 1, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). The slave whose address corresponds to the transmitted address will respond by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. If the R/W bit is low, the master will write to the slave device. PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Unlike the polarity of VDD – VSS, which must be positive, voltage across A–B, W–A, and W–B can be at either polarity provided that VSS is powered by a negative supply. If ignoring the effect of the wiper resistance for approximation, connecting A terminal to 5 V and B terminal to ground produces an output voltage at the wiper-to-B starting at zero volt up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal AB divided by the 256 position of the potentiometer divider. Since AD5241/AD5242 can be supplied by dual supplies, the general equation defining the output voltage at VW with respect to ground for any valid input voltage applied to Terminals A and B is: D 256 − D VA + VB 256 256 (5) Referring to Figures 2 and 3, the first byte of AD5241/AD5242 is a Slave Address Byte. It has a 7-bit slave address and a R/W bit. The 5 MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow users to use up to four of these devices on one bus. The typical distribution of the nominal resistance RAB from channel-to-channel matches within ± 1% for AD5242. Deviceto-device matching is process lot dependent and it is possible to have ± 30% variation. Since the resistance element is processed in thin film technology, the change in RAB with temperature has no more than 30 ppm/°C temperature coefficient. VW (D) = RWB (D ) RWA (D ) VA + VB RAB RAB The AD5241/AD5242 are controlled via an I2C-compatible serial bus. The RDACs are connected to this bus as slave devices. For RAB = 10 kΩ and B terminal can be either open circuit or tied to W. The following output resistance RWA will be set for the following RDAC latch codes. RWA () (4) Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors RWA, RWB, and not the absolute values; therefore, the temperature drift reduces to 5 ppm/°C. (2) D (DEC) D VAB + VB 256 where RWB(D) and RWA(D) can be obtained from Equations 1 and 2. Similar to the mechanical potentiometer, the resistance of the RDAC between the Wiper W and Terminal A also produces a digitally controlled resistance RWA. When these terminals are used, the B terminal can be opened or tied to the wiper terminal. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is: RWA ( D ) = 256 – D × R AB + RW 256 VW (D) = (3) 2. A Write operation contains an extra Instruction Byte more than the Read operation. Such Instruction Byte, Frame 2, in Write mode follows the Slave Address Byte. The MSB of the Instruction Byte labeled A/B is the RDAC subaddress select. A “low” selects RDAC1 and a “high” selects RDAC2 for the dual-channel AD5242. Set A/B to low for AD5241. The second MSB, RS, is the Midscale reset. A logic high of this bit moves the wiper of a selected RDAC to the center tap where RWA = RWB. The third MSB, SD, is a shutdown bit. A logic high on SD causes the RDAC open circuit at Terminal A while shorting wiper to Terminal B. This operation yields almost a 0 Ω in rheostat mode or zero volt in potentiometer mode. This SD bit serves the same function as the SHDN pin except SHDN pin reacts to active low. The following two –10– REV. A AD5241/AD5242 bits are O2 and O1. They are extra programmable logic output that users can use to drive other digital loads, logic gates, LED drivers, and analog switches, etc. The three LSBs are DON’T CARE. See Figure 2. 3. After acknowledging the Instruction Byte, the last byte in Write mode is the Data Byte, Frame 3. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an “Acknowledge” bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL, Figure 2. 4. Unlike the Write mode, the Data Byte follows immediately after the acknowledgment of the Slave Address Byte in the Read mode, Frame 2. Data is transmitted over the serial bus in sequences of nine clock pulses (slight difference with the Write mode, there are eight data bits followed by a “No Acknowledge” bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL, Figure 3. 5. When all data bits have been read or written, a STOP condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see Figure 2). In Read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse which goes high to establish a STOP condition (see Figure 3). A repeated Write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the Write cycle, each Data byte will update the RDAC output. For example, after the RDAC has acknowledged its Slave Address and Instruction Bytes, the RDAC output will be updated. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the Write mode has to start a whole new sequence with a new Slave Address, Instruction, and Data Bytes transferred again. Similarly, a repeated Read function of the RDAC is also allowed. MULTIPLE DEVICES ON ONE BUS Figure 5 shows four AD5242 devices on the same serial bus. Each has a different slave address since the state of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a fully I2C-compatible interface. Note, a device will be addressed properly only if the bit information of AD0 and AD1 in the Slave Address Byte matches with the logic inputs at pins AD0 and AD1 of that particular device. 5V RP RP SDA MASTER LEVEL-SHIFT FOR BIDIRECTIONAL INTERFACE While most old systems may be operated at one voltage, a new component may be optimized at another. When they operate the same signal at two different voltages, a proper method of levelshifting is needed. For instance, one can use a 3.3 V E2PROM to interface with a 5 V digital potentiometer. A level-shift scheme is needed in order to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E2PROM. Figure 6 shows one of the techniques. M1 and M2 can be N-Ch FETs 2N7002 or low threshold FDV301N if VDD falls below 2.5 V. VDD2 = 5V VDD2 = 3.3V RP G RP S RP RP D SDA1 SDA2 G M1 S SCL1 D SCL2 M2 3.3V E2PROM 5V AD5242 Figure 6. Level-Shift for Different Voltage Devices Operation VDD MP IN 1 2 O1 DATA IN FRAME 2 OF WRITE MODE O1 MN VSS Figure 7. Output Stage of Logic Output O1 READBACK RDAC VALUE AD5241/AD5242 allows user to read back the RDAC values in Read Mode. However, for AD5242 dual channel device, the channel of interest is the one that is previously selected in Write Mode. In the case that users need to read the RDAC values of both channels in AD5242, they can program the first subaddress in the Write Mode and then change to the Read Mode to read the first channel value. After that, they can change back to the Write Mode with the second subaddress and finally read the second channel value in the Read Mode again. Note that it is not necessary for users to issue the Frame 3 Data Byte in the Write Mode for subsequent readback operation. Users should refer to Figures 2 and 3 for the programming format. ADDITIONAL PROGRAMMABLE LOGIC OUTPUT AD5241/AD5242 features additional programmable logic outputs, O1 and O2, which can be used to drive digital load, analog switches, and logic gates. The logic states of O1 and O2 can be programmed in Frame 2 of the Write Mode (see Figure 2). Figure 7 shows the output stage O1 where the logic levels are equal to the supply levels and the current driving capability reaches tenths of mA. SCL SDA SCL VDD SDA SCL VDD SDA SCL VDD SDA SCL AD1 AD1 AD1 AD1 AD0 AD0 AD0 AD0 AD5242 AD5242 AD5242 AD5242 All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 8. This applies to digital input pins SDA, SCL, and SHDN. Figure 5. Multiple AD5242 Devices on One Bus REV. A –11– AD5241/AD5242 A,B,W 340 LOGIC VSS VSS Figure 9. ESD Protection of Resistor Terminals Figure 8. ESD Protection of Digital Pins Test Circuits Test Circuits 1 to 9 define the test conditions used in the product specification table. 5V OP279 DUT A V VIN V+ = VDD 1LSB = V+/2N OFFSET GND W B W A VMS VOUT DUT B OFFSET BIAS Test Circuit 6. Noninverting Gain Test Circuit 1. Potentiometer Divider Nonlinearity Error (INL, DNL) NO CONNECT A DUT A +15V IW W VIN W DUT OP42 OFFSET GND B VMS 2.5V Test Circuit 2. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL) –15V Test Circuit 7. Gain vs. Frequency RSW = DUT VMS2 0.1V ISW CODE = DUT A W H W I W = VDD /RNOMINAL VW VOUT B B 0.1V ISW B VMS1 RW = [VMS1 – VMS2]/I W VSS TO VDD Test Circuit 3. Wiper Resistance Test Circuit 8. Incremental ON Resistance VA NC V+ = VDD ±10% VDD PSRR (dB) = 20 LOG A V+ W PSS (%/%) = B VMS% VMS ( VDD ) VDD DUT VDD% VSS A GND B VMS W I CM VCM NC Test Circuit 9. Common-Mode Leakage Current Test Circuit 4. Power Supply Sensitivity (PSS, PSRR) A DUT B 5V W OP279 OFFSET GND VOUT OFFSET BIAS Test Circuit 5. Inverting Gain –12– REV. A AD5241/AD5242 DIGITAL POTENTIOMETER SELECTION GUIDE Part Number Number of VRs Terminal per Voltage Package1 Range Interface Data Control2 Nominal Resistance (k) Resolution (Number of Wiper Positions) Power Supply Current (IDD) Packages Comments AD5201 1 ± 3 V, +5.5 V 3-Wire 10, 50 33 40 µA µSOIC-10 Full AC Specs, Dual Supply, Pwr-On-Reset, Low Cost AD5220 1 5.5 V Up/Down 10, 50, 100 128 40 µA PDIP, SO-8, µSOIC-8 No Rollover, Pwr-On-Reset AD7376 1 ± 15 V, +28 V 3-Wire 10, 50, 100, 1000 128 100 µA PDIP-14, SOL-16, TSSOP-14 Single 28 V or Dual ± 15 V Supply Operation AD5200 1 ± 3 V, +5.5 V 3-Wire 10, 50 256 40 µA µSOIC-10 Full AC Specs, Dual Supply, Pwr-On-Reset AD8400 1 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA SO-8 Full AC Specs AD5241 1 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SO-14, TSSOP-14 I2C-Compatible, TC < 50 ppm/°C AD5231* 1 ±2.75 V, +5.5 V 3-Wire 10, 50, 100 1024 10 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability AD5222 2 ± 3 V, +5.5 V Up/Down 10, 50, 100, 1000 128 80 µA SO-14, TSSOP-14 No Rollover, Stereo, Pwr-OnReset, TC < 50 ppm/°C AD8402 2 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SO-14, TSSOP-14 Full AC Specs, nA Shutdown Current AD5232 2 ±2.75 V, +5.5 V 3-Wire 10, 50, 100 256 10 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability AD5242 2 ± 3 V, +5.5 V 2-Wire 10, 100, 1000 256 50 µA SO-16, TSSOP-16 I2C-Compatible, TC < 50 ppm/°C AD5262* 2 ± 5 V, +12 V 3-Wire 20, 50, 200 256 60 µA TSSOP-16 Medium Voltage Operation, TC < 50 ppm/°C AD5203 5.5 V 3-Wire 10, 100 64 5 µA PDIP, SOL-24, TSSOP-24 Full AC Specs, nA Shutdown Current 4 AD5233* 4 ±2.75 V, +5.5 V 3-Wire 10, 50, 100 64 10 µA TSSOP-16 Nonvolatile Memory, Direct Program, I/D, ± 6 dB Settability AD5204 4 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, TSSOP-24 Full AC Specs, Dual Supply, Pwr-On-Reset AD8403 4 5.5 V 3-Wire 1, 10, 50, 100 256 5 µA PDIP, SOL-24, TSSOP-24 Full AC Specs, nA Shutdown Current AD5206 6 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 60 µA PDIP, SOL-24, TSSOP-24 Full AC Specs, Dual Supply, Pwr-On-Reset AD5260 1 ± 5 V, +15 V 3-Wire 20, 50, 200 256 60 µA TSSOP-14 TC < 50 ppm/°C AD5207 2 ± 3 V, +5.5 V 3-Wire 10, 50, 100 256 40 µA TSSOP-14 Full AC Specs, SVO AD5235 2 ±2.75 V, +5.5 V 3-Wire 25, 250 1024 20 µA TSSOP-16 Nonvolatile Memory, TC < 50 ppm/°C NOTES *Future product, consult factory for latest status. 1 VR stands for variable resistor. This term is used interchangeably with RDAC, programmable resistor, and digital potentiometer. 2 3-wire interface is SPI- and microwire-compatible. 2-wire interface is I 2C-compatible. REV. A –13– AD5241/AD5242 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 16-Lead TSSOP (RU-16) 14-Lead TSSOP (RU-14) 0.201 (5.10) 0.193 (4.90) 14 0.201 (5.10) 0.193 (4.90) 8 16 9 0.177 (4.50) 0.169 (4.30) 0.177 (4.50) 0.169 (4.30) 0.256 (6.50) 0.246 (6.25) 1 0.256 (6.50) 0.246 (6.25) 7 1 PIN 1 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 8 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.0433 (1.10) MAX 0.006 (0.15) 0.002 (0.05) 8 0 0.028 (0.70) 0.020 (0.50) SEATING PLANE 8 0.0256 (0.65) 0.0118 (0.30) 0.0079 (0.20) 0 BSC 0.0075 (0.19) 0.0035 (0.090) 14-Lead SOIC (R-14) 16-Lead SOIC (R-16A) 0.3444 (8.75) 0.3367 (8.55) 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.3937 (10.00) 0.3859 (9.80) 14 8 1 7 0.050 (1.27) BSC 0.0688 (1.75) 0.0532 (1.35) 0.0098 (0.25) 0.0040 (0.10) 0.028 (0.70) 0.020 (0.50) 0.2440 (6.20) 0.2284 (5.80) 0.1574 (4.00) 0.1497 (3.80) PIN 1 0.0196 (0.50) 45 0.0099 (0.25) 8 0.0192 (0.49) SEATING 0.0099 (0.25) 0 0.0500 (1.27) 0.0138 (0.35) PLANE 0.0160 (0.41) 0.0075 (0.19) 16 9 1 8 0.050 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) –14– 0.2440 (6.20) 0.2284 (5.80) 0.0688 (1.75) 0.0532 (1.35) 0.0196 (0.50) 45 0.0099 (0.25) 8 0.0192 (0.49) SEATING 0 0.0500 (1.27) 0.0099 (0.25) PLANE 0.0138 (0.35) 0.0160 (0.41) 0.0075 (0.19) REV. A AD5241/AD5242 Revision History Location Page Data Sheet changed from REV. 0 to REV. A. Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to FUNCTIONAL BLOCK DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Additions to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Edits to Figures 1, 2, 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Addition of Readback RDAC Value and Additional Programmable Logic Output sections, and addition of new Figure 7 (which changed succeeding figure numbers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Additions/edits to DIGITAL POTENTIOMETER SELECTION GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 REV. A –15– –16– PRINTED IN U.S.A. C00926–0–2/02(A)