FM24V05 512Kb Serial 3V F-RAM Memory Features 512K bit Ferroelectric Nonvolatile RAM Organized as 65,536 x 8 bits High Endurance 100 Trillion (1014) Read/Writes 10 year Data Retention NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 3.4 MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Description The FM24V05 is a 512Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 10 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Device ID Device ID reads out Manufacturer ID & Part ID Low Voltage, Low Power Operation Low Voltage Operation 2.0V – 3.6V Active Current < 150 A (typ. @ 100KHz) 90 A Standby Current (typ.) 5 A Sleep Mode Current (typ.) Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC Package a hardware drop-in replacement. The devices are available in industry standard 8-pin SOIC package using a familiar two-wire (I2C) protocol. Both devices incorporate a read-only Device ID that allows the host to determine the manufacturer, product density, and product revision. The devices are guaranteed over an industrial temperature range of 40°C to +85°C. Pin Configuration The FM24V05 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers write endurance orders of magnitude higher than EEPROM. Also, F-RAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. These capabilities make the FM24V05 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. A0 A1 A2 1 8 VDD 2 7 3 6 VSS 4 5 WP SCL SDA Pin Name A0-A2 SDA SCL WP VDD VSS Function Device Select Address Serial Data/address Serial Clock Write Protect Supply Voltage Ground The FM24V05 provides substantial benefits to users of serial EEPROM, yet these benefits are available in This product conforms to specifications per the terms of the Ramtron standard warranty. The product has completed Ramtron’s internal qualification testing and has reached production status. Cypress Semiconductor Corporation • Document Number: 001-84462 Rev. *B 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 29, 2013 FM24V05 - 512Kb I2C FRAM Counter Address Latch 8K x 64 FRAM Array 8 SDA Serial to Parallel Converter Data Latch 8 SCL WP Control Logic A0-A2 Device ID and Serial Number Figure 1. FM24V05 Block Diagram Pin Description Pin Name A0-A2 Type Input SDA I/O SCL Input WP Input VDD VSS Supply Supply Pin Description Device Select Address 0-2: These pins are used to select one of up to 8 devices of the same type on the same two-wire bus. To select the device, the address value on the two pins must match the corresponding bits contained in the slave address. The address pins are pulled down internally. Serial Data/Address: This is a bi-directional pin for the two-wire interface. It is open-drain and is intended to be wire-OR‟d with other devices on the two-wire bus. The input buffer incorporates a Schmitt trigger for noise immunity and the output driver includes slope control for falling edges. An external pull-up resistor is required. Serial Clock: The serial clock pin for the two-wire interface. Data is clocked out of the part on the falling edge, and into the device on the rising edge. The SCL input also incorporates a Schmitt trigger input for noise immunity. Write Protect: When tied to VDD, addresses in the entire memory map will be writeprotected. When WP is connected to ground, all addresses may be written. This pin is pulled down internally. Supply Voltage Ground Document Number: 001-84462 Rev. *B Page 2 of 17 FM24V05 - 512Kb I2C FRAM Overview Two-wire Interface The FM24V05 is a family of serial F-RAM memory devices. The memory array is logically organized as a 65,536 x 8 bit memory array and is accessed using an industry standard two-wire (I2C) interface. Functional operation of the F-RAM is similar to serial EEPROM. The major difference between the FM24V05 and serial EEPROM is F-RAM‟s superior write performance. The FM24V05 employs a bi-directional two-wire bus protocol using few pins or board space. Figure 2 illustrates a typical system configuration using the FM24V05 in a microcontroller-based system. The industry standard two-wire bus is familiar to many users but is described in this section. Memory Architecture When accessing the FM24V05, the user addresses 65,536 locations each with 8 data bits. These data bits are shifted serially. The 65,536 addresses are accessed using the two-wire protocol, which includes a slave address (to distinguish other non-memory devices) and a 2-byte address. All 16 address bits are used by the decoder for accessing the memory. The access time for memory operation is essentially zero beyond the time needed for the serial protocol. That is, the memory is read or written at the speed of the two-wire bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. That is, by the time a new bus transaction can be shifted into the part, a write operation will be complete. This is explained in more detail in the interface section below. Users expect several obvious system benefits from the FM24V05 due to its fast write cycle and high endurance as compared with EEPROM. However there are less obvious benefits as well. For example in a high noise environment, the fast-write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. By convention, any device that is sending data onto the bus is the transmitter while the target device for this data is the receiver. The device that is controlling the bus is the master. The master is responsible for generating the clock signal for all operations. Any device on the bus that is being controlled is a slave. The FM24V05 always is a slave device. The bus protocol is controlled by transition states in the SDA and SCL signals. There are four conditions including start, stop, data bit, or acknowledge. Figure 3 illustrates the signal conditions that specify the four states. Detailed timing diagrams are shown in the electrical specifications section. VDD Rmin = 1.1 Kohm Rmax = tR/Cbus Microcontroller SDA SCL FM24V05 A0 A1 A2 SDA SCL FM24V05 A0 A1 A2 Figure 2. Typical System Configuration Note that it is the user‟s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. Document Number: 001-84462 Rev. *B Page 3 of 17 FM24V05 - 512Kb I2C FRAM SCL SDA 7 Stop (Master) Start (Master) 6 Data bits (Transmitter) 0 Data bit Acknowledge (Transmitter) (Receiver) Figure 3. Data Transfer Protocol Stop Condition A stop condition is indicated when the bus master drives SDA from low to high while the SCL signal is high. All operations using the FM24V05 should end with a stop condition. If an operation is in progress when a stop is asserted, the operation will be aborted. The master must have control of SDA (not a memory read) in order to assert a stop condition. Start Condition A start condition is indicated when the bus master drives SDA from high to low while the SCL signal is high. All commands should be preceded by a start condition. An operation in progress can be aborted by asserting a start condition at any time. Aborting an operation using the start condition will ready the FM24V05 for a new operation. If during operation the power supply drops below the specified VDD minimum, the system should issue a start condition prior to performing another operation. Data/Address Transfer All data transfers (including addresses) take place while the SCL signal is high. Except under the two conditions described above, the SDA signal should not change while SCL is high. Acknowledge The acknowledge takes place after the 8th data bit has been transferred in any transaction. During this state the transmitter should release the SDA bus to allow the receiver to drive it. The receiver drives the SDA signal low to acknowledge receipt of the byte. If the receiver does not drive SDA low, the condition is a no-acknowledge and the operation is aborted. The receiver would fail to acknowledge for two distinct reasons. First is that a byte transfer fails. In this case, the no-acknowledge ceases the current operation so that the part can be addressed again. This allows the last byte to be recovered in the event of a communication error. Document Number: 001-84462 Rev. *B Second and most common, the receiver does not acknowledge to deliberately end an operation. For example, during a read operation, the FM24V05 will continue to place data onto the bus as long as the receiver sends acknowledges (and clocks). When a read operation is complete and no more data is needed, the receiver must not acknowledge the last byte. If the receiver acknowledges the last byte, this will cause the FM24V05 to attempt to drive the bus on the next clock while the master is sending a new command such as stop. Slave Address The first byte that the FM24V05 expects after a start condition is the slave address. As shown in Figure 4, the slave address contains the device type or slave ID, the device select address bits, a page address bit, and a bit that specifies if the transaction is a read or a write. Bits 7-4 are the device type (slave ID) and should be set to 1010b for the FM24V05. These bits allow other function types to reside on the 2-wire bus within an identical address range. Bits 3-1 are the device select address bits. They must match the corresponding value on the external address pins to select the device. Up to eight FM24V05 devices can reside on the same two-wire bus by assigning a different address to each. Bit 0 is the read/write bit. R/W=1 indicates a read operation and R/W=0 indicates a write operation. High Speed Mode (HS-mode) The FM24V05 supports a 3.4MHz high speed mode. A master code (0000 1XXXb) must be issued to place the device into high speed mode. Communication between master and slave will then be enabled for speeds up to 3.4MHz. A stop condition will exit HSmode. Single- and multiple-byte reads and writes are supported. See Figures 10 and 11 for HS-mode timings. Page 4 of 17 FM24V05 - 512Kb I2C FRAM Memory Operation Device Select Slave ID 1 0 1 0 A2 A1 A0 R/W 7 6 5 4 3 2 1 0 Figure 4. Slave Address Addressing Overview After the FM24V05 (as receiver) acknowledges the slave address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The complete 16-bit address is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch -either a newly written value or the address following the last access. The current address will be held for as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24V05 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing. After the last address (FFFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After the address information has been transmitted, data transfer between the bus master and the FM24V05 can begin. For a read operation the FM24V05 will place 8 data bits on the bus then wait for an acknowledge from the master. If the acknowledge occurs, the FM24V05 will transfer the next sequential byte. If the acknowledge is not sent, the FM24V05 will end the read operation. For a write operation, the FM24V05 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. The FM24V05 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of F-RAM technology. These improvements result in some differences between the FM24V05 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a slave address, then a memory address. The bus master indicates a write operation by setting the LSB of the slave address (R/W bit) to a „0‟. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from FFFFh to 0000h. Unlike other nonvolatile memory technologies, there is no effective write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write is complete is unnecessary and will always return a ready condition. Internally, an actual memory write occurs after the 8 th data bit is transferred. It will be complete before the acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using start or stop condition prior to the 8th data bit. The FM24V05 uses no page buffering. The memory array can be write-protected using the WP pin. This feature is available only on FM24V05 devices. Setting the WP pin to a high condition (VDD) will write-protect all addresses. The FM24V05 will not acknowledge data bytes that are written to protected addresses. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP to a low state (V SS) will deactivate this feature. WP is pulled down internally. Figures 5 and 6 below illustrate a single-byte and multiple-byte write cycles. Document Number: 001-84462 Rev. *B Page 5 of 17 FM24V05 - 512Kb I2C FRAM Start By Master S Stop Address & Data Slave Address 0 A Address MSB By FM24V05 A Address LSB A Data Byte A P Acknowledge Figure 5. Single Byte Write Start Stop Address & Data By Master S Slave Address 0 A Address MSB By FM24V05 A Address LSB A Data Byte A Data Byte A P Acknowledge Figure 6. Multiple Byte Write Read Operation There are two basic types of read operations. They are current address read and selective address read. In a current address read, the FM24V05 uses the internal address latch to supply the address. In a selective read, the user performs a procedure to set the address to a specific value. Current Address & Sequential Read As mentioned above the FM24V05 uses an internal latch to supply the address for a read operation. A current address read uses the existing value in the address latch as a starting place for the read operation. The system reads from the address immediately following that of the last operation. To perform a current address read, the bus master supplies a slave address with the LSB set to a „1‟. This indicates that a read operation is requested. After receiving the complete slave address, the FM24V05 will begin shifting out data from the current address on the next clock. The current address is the value held in the internal address latch. Beginning with the current address, the bus master can read any number of bytes. Thus, a sequential read is simply a current address read with multiple byte transfers. After each byte the internal address counter will be incremented. Each time the bus master acknowledges a byte, this indicates that the FM24V05 should read out the next sequential byte. Document Number: 001-84462 Rev. *B There are four ways to properly terminate a read operation. Failing to properly terminate the read will most likely create a bus contention as the FM24V05 attempts to read out additional data onto the bus. The four valid methods are: 1. 2. 3. 4. The bus master issues a no-acknowledge in the 9th clock cycle and a stop in the 10th clock cycle. This is illustrated in the diagrams below. This is preferred. The bus master issues a no-acknowledge in the 9th clock cycle and a start in the 10th. The bus master issues a stop in the 9th clock cycle. The bus master issues a start in the 9th clock cycle. If the internal address reaches FFFFh, it will wrap around to 0000h on the next read cycle. Figures 7 and 8 below show the proper operation for current address reads. Selective (Random) Read There is a simple technique that allows a user to select a random address location as the starting point for a read operation. This involves using the first three bytes of a write operation to set the internal address followed by subsequent read operations. To perform a selective read, the bus master sends out the slave address with the LSB set to 0. This specifies a write operation. According to the write protocol, the bus master then sends the address bytes that are loaded into the internal address latch. After the FM24V05 acknowledges the address, the bus master issues a start condition. This simultaneously aborts Page 6 of 17 FM24V05 - 512Kb I2C FRAM the write operation and allows the read command to be issued with the slave address LSB set to a „1‟. The Start By Master operation is now a current address read. No Acknowledge Address Stop S Slave Address By FM24V05 1 A Data Byte Acknowledge 1 P Data Figure 7. Current Address Read Start By Master Address No Acknowledge Acknowledge Stop S Slave Address By FM24V05 1 A Data Byte A Acknowledge Data Byte 1 P Data Figure 8. Sequential Read Start Address By Master Start No Acknowledge Address Stop S Slave Address 0 A Address MSB A Address LSB By FM24V05 A S Slave Address 1 A Data Byte 1 P Data Acknowledge Figure 9. Selective (Random) Read Start Start & Enter HS-mode Address HS-mode command By Master S 0 0 0 0 1 X X By FM24V05 1 X S No Acknowledge Stop & Exit HS-mode Slave Address 1 A No Acknowledge Data Byte 1 P Data Acknowledge Figure 10. HS-mode Current Address Read Start Start & Enter HS-mode HS-mode command By Master S 0 0 0 0 1 X X By FM24V05 X 1 S Slave Address 0 A Stop & Exit HS-mode Address & Data Address MSB No Acknowledge A Address LSB A Data Byte A P Acknowledge Figure 11. HS-mode Byte Write Document Number: 001-84462 Rev. *B Page 7 of 17 FM24V05 - 512Kb I2C FRAM 5. 6. 7. Sleep Mode A low power mode called Sleep Mode is implemented on both FM24V05 devices. The device will enter this low power state when the Sleep command 86h is clocked-in. Sleep Mode entry can be entered as follows: 1. 2. 3. 4. The master sends Reserved Slave ID 0x86 The FM24V05 sends an ACK. The master sends STOP to ensure the device enters sleep mode. Once in sleep mode, the device draws IZZ current, but the device continues to monitor the I2C pins. Once the master sends a Slave Address that the FM24V05 identifies, it will “wakeup” and be ready for normal operation within tREC (400 s max.). As an alternative method of determining when the device is ready, the master can send read or write commands and look for an ACK. While the device is waking up, it will NACK the master until it is ready. The master sends a START command. The master sends Reserved Slave ID 0xF8 The master sends the I2C-bus slave address of the slave device it needs to identify. The last bit is a „Don‟t care‟ value (R/W bit). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). The master sends a Re-START command. Start Address By Master S Rsvd Slave ID (F8) By FM24V05 A Address Start Slave Address X A S Rsvd Slave ID (86) Stop A P Acknowledge Figure 12. Sleep Mode Entry Document Number: 001-84462 Rev. *B Page 8 of 17 FM24V05 - 512Kb I2C FRAM 5. 6. Device ID The FM24V05 devices incorporate a means of identifying the device by providing three bytes of data, which are manufacturer, product ID, and die revision. The Device ID is read-only. It can be accessed as follows: 1. 2. 3. 4. The master sends Reserved Slave ID 0xF9 The Device ID Read can be done, starting with the 12 manufacturer bits, followed by the 9 part identification bits, and then the 3 die revision bits. The master ends the Device ID read sequence by NACKing the last byte, thus resetting the slave device state machine and allowing the master to send the STOP command. 7. The master sends a START command. The master sends Reserved Slave ID 0xF8 The master sends the I2C-bus slave address of the slave device it needs to identify. The last bit is a „Don‟t care‟ value (R/W bit). Only one device must acknowledge this byte (the one that has the I2C-bus slave address). The master sends a Re-START command. Note: The reading of the Device ID can be stopped anytime by sending a NACK command. Start Address By Master No Acknowledge Acknowledge Address Start Stop S Rsvd Slave ID (F8) A Slave Address By FM24V05 A S Rsvd Slave ID (F9) A Data Byte A Data Byte A Data Byte 1 Data Acknowledge Figure 13. Read Device ID Manufacturer ID 11 10 9 8 7 6 5 4 Product ID 3 2 1 0 8 Ramtron 0 0 0 0 0 0 0 7 6 5 4 Density 0 0 1 0 0 0 0 1 3 Die Rev. 2 1 0 2 1 0 0 0 0 0 Variation 1 N 0 0 0 Figure 14. Manufacturer and Product ID Density: 01h=128Kb, 02h=256Kb, 03h=512Kb, 04=1Mb Variation: Product ID bit 4 = S/N, Product ID bit 0 = reserved The 3-byte hex code for an FM24V05 will be: Document Number: 001-84462 Rev. *B 0x00 0x43 0x00 Page 9 of 17 P FM24V05 - 512Kb I2C FRAM Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) Package Moisture Sensitivity Level Ratings -1.0V to +4.5V -1.0V to +4.5V and VIN < VDD+1.0V * -55 C to +125 C 260 C 2.5kV 1.25kV 200V MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD =2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units VDD Main Power Supply 2.0 3.3 3.6 V IDD VDD Supply Current @ SCL = 100 kHz 175 A @ SCL = 1 MHz 400 A @ SCL = 3.4 MHz 1000 A ISB Standby Current 90 150 A IZZ Sleep Mode Current 5 8 A ILI Input Leakage Current ±1 A ILO Output Leakage Current ±1 A VIL Input Low Voltage -0.3 0.3 VDD V VIH Input High Voltage 0.7 VDD VDD + 0.3 V VOL1 Output Low Voltage (IOL = 2 mA, VDD ≥ 2.7V) 0.4 V VOL2 Output Low Voltage (IOL = 150 A) 0.2 V RIN Address Input Resistance (WP, A2-A0) For VIN = VIL (max) 50 K For VIN = VIH (min) 1 M Notes 1 2 2 3 3 4 Notes 1. SCL toggling between VDD-0.2V and VSS, other inputs VSS or VDD-0.2V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins. 4. The input pull-down circuit is stronger (50K ) when the input voltage is below VIL and weak (1M ) when the input voltage is above VIH. Document Number: 001-84462 Rev. *B Page 10 of 17 FM24V05 - 512Kb I2C FRAM AC Parameters (TA = -40 C to + 85 C, VDD =2.0V to 3.6V unless otherwise specified) F/S-mode HS-mode (CL<500pF) (CL<100pF) Symbol Parameter Min Max Min Max fSCL SCL Clock Frequency 0 1.0 0 3.4 tLOW Clock Low Period 500 160 tHIGH Clock High Period 260 60 tAA SCL Low to SDA Data Out Valid 450 130 tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tR tF tSU:STO tDH tSP Bus Free Before New Transmission Start Condition Hold Time Start Condition Setup for Repeated Start Data In Hold Data In Setup Input Rise Time Input Fall Time Stop Condition Setup Data Output Hold (from SCL @ V IL) Noise Suppression Time Constant on SCL, SDA 0.5 260 260 0 50 0.3 160 160 0 10 120 120 80 80 260 0 160 0 50 5 Units MHz ns ns ns s ns ns ns ns ns ns ns ns ns Notes 1 3 2 2 Notes: All SCL specifications as well as start and stop conditions apply to both read and write operations. 1. The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to fSCL (max). 2. This parameter is periodically sampled and not 100% tested. 3. In HS-mode and VDD < 2.7V, the tSU:DAT (min.) spec is 15ns. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter CI/O Input/Output Capacitance (SDA) CIN Input Capacitance Min - Max 8 6 Units pF pF Notes 1 1 Notes 1. This parameter is periodically sampled and not 100% tested. Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.0V to 3.6V) Symbol Parameter tVR VDD Rise Time tVF VDD Fall Time tPU Power Up (VDD min) to First Access (Start condition) tPD Last Access (Stop condition) to Power Down (VDD min) tREC Recovery Time from Sleep Mode Notes 1. 2. Min 50 100 250 0 - Max 400 Units s/V s/V s s s Notes 1,2 1,2 This parameter is characterized and not 100% tested. Slope measured at any point on VDD waveform. Power Cycle Timing tVR VDD tVF VDD min. tPD tPU Access Allowed Document Number: 001-84462 Rev. *B Page 11 of 17 FM24V05 - 512Kb I2C FRAM AC Test Conditions Input Pulse Levels Input rise and fall times Input and output timing levels Equivalent AC Test Load Circuit 0.1 VDD to 0.9 VDD 10 ns 0.5 VDD 3.6V 1.8 Kohm Output Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant datasheet sections. These diagrams illustrate the timing parameters only. 100 pF Read Bus Timing tR ` tF t HIGH t SP t LOW t SP SCL t SU:SDA 1/fSCL t BUF t HD:DAT t SU:DAT SDA Start t DH t AA Stop Start Acknowledge Write Bus Timing t HD:DAT SCL t HD:STA t SU:STO t SU:DAT t AA SDA Start Data Retention (TA = -40 C to +85 C) Parameter Data Retention Document Number: 001-84462 Rev. *B Stop Start Min 10 Acknowledge Max - Units Years Notes Page 12 of 17 FM24V05 - 512Kb I2C FRAM Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Recommended PCB Footprint 7.70 3.90 ±0.10 3.70 6.00 ±0.20 2.00 0.65 1.27 Pin 1 4.90 ±0.10 1.27 0.33 0.51 0.25 0.50 1.35 1.75 0.10 0.25 0.19 0.25 45 0.10 mm 0-8 0.40 1.27 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. SOIC Package Marking Scheme XXXXXXX-P R LLLLLZ RICYYWW Legend: XXXXXXX = part number, P = package type R = rev code, LLLLL = lot code, Z = Package code RIC = Ramtron Int‟l Corp, YY = year, WW = work week = Pb-free Example: FM24V05, “Green”/RoHS SOIC Rev. A, Lot 67989, SOIC Year 2013, Work Week 07 Pb-free FM24V05-G A 67989S RIC1307 Document Number: 001-84462 Rev. *B Page 13 of 17 FM24V05 - 512Kb I2C FRAM Revision History Revision 1.0 1.1 2.0 Date 8/22/2008 2/2/2009 5/25/2010 2.1 3.0 11/22/2011 1/30/2012 Summary Initial Release Added tape and reel ordering information. Changed to Pre-Production status. Updated ESD ratings. Changed part marking scheme. Expanded CRC check description. Removed S/N option. Changed to Production status. Ordering Information Part Number Features FM24V05-G FM24V05-GTR Device ID Device ID Document Number: 001-84462 Rev. *B Operating Voltage 2.0-3.6V 2.0-3.6V Package 8-pin “Green”/RoHS SOIC 8-pin “Green”/RoHS SOIC, Tape & Reel Page 14 of 17 FM24V05 - 512Kb I2C FRAM Appendix A - Errata for FM24V05 Errata Number 001 Date January 12, 2011 (Updated Jan. 2012) Product FM24V05 The FM24V05 devices have a problem with the sleep mode function. Some devices will not exit sleep at Vdd voltages within the specified operating range. Worst case is at high V DD (3.6V). The failing voltage will be lower at cold temperatures. This does not affect operation if the sleep function is not used. There is an effective screen that is implemented at final test. A temporary part number has been assigned for customers who use sleep mode. Customers who require sleep mode should order the FM24V05-G. The part will be marked with a triangle to the right of the part mark. An example of the mark is as follows: XXXXXXX-PT RLLLLLLLL RIC YYWW No Sleep Mode Screen FM24V05-G A9646447 RIC1011 Sleep Mode Screen FM24V05-G A9646447 RIC1011 This errata will remain in effect until the sleep function is fixed. UPDATE: Ramtron has implemented a screen such that all devices comply with the datasheet specifications without exception over all operating temperature and voltage conditions. Therefore the above errata no longer applies. The starting date code for errata-free devices is 1204. (YY=12, WW=04) Document Number: 001-84462 Rev. *B Page 15 of 17 FM24V05 - 512Kb I2C FRAM Document History Document Title: FM24V05 512Kb Serial 3V F-RAM Memory Document Number: 001-84462 Revision ECN Orig. of Change Submission Date Description of Change ** 3902204 GVCH 02/25/2013 New Spec *A 3985098 GVCH 05/09/2013 Removed FM24VN05 part number related information Updated SOIC package marking scheme *B 4014247 GVCH 05/29/2013 Document Number: 001-84462 Rev. *B Added Appendix A - Errata for FM24V05 Page 16 of 17 FM24V05 - 512Kb I2C FRAM Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive psoc.cypress.com/solutions Clocks & Buffers cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support RAMTRON is a registered trademark and NoDelay™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semiconductor Corporation, 2011-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-84462 Rev. *B Page 17 of 17