CYPRESS CY7C199C

CY7C199C
256K (32K x 8) Static RAM
Features
General Description
• Fast access time: 12 ns
The CY7C199C is a high-performance CMOS Asynchronous
SRAM organized as 32K by 8 bits that supports an
asynchronous memory interface. The device features an
automatic power-down feature that significantly reduces
power consumption when deselected.
• Wide voltage range: 5.0V ± 10% (4.5V to 5.5V)
• CMOS for optimum speed/power
• TTL–compatible Inputs and Outputs
See the Truth Table in this data sheet for a complete
description of read and write modes
• 2.0V Data Retention
• Low CMOS standby power
• Automated Power-down when deselected
• Available in Pb-free and non Pb-free 28-pin (300-Mil)
Molded SOJ, 28-pin (300-Mil) DIP and 28-pin TSOP I
packages
Logic Block Diagram
32K x 8
RAM
Array
ARRAY
Sense Amps
Row Decoder
Input Buffer
I/Ox
CE
Column Decoder
WE
Power
Down
Circuit
OE
X
A
X
Product Portfolio
12 ns
15 ns
20 ns
Maximum Access Time
12
15
20
ns
Maximum Operating Current
85
80
75
mA
Maximum CMOS Standby Current (L)
500
Unit
µA
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05408 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 3, 2006
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CY7C199C
Pin Layout and Specifications
28 DIP (6.9 x 35.6 x 3.5 mm)
OE
A1
A2
A3
A4
WE
VCC
A5
A6
A7
A8
A9
A10
A11
A5
1
28
VCC
A6
2
27
WE
A7
3
26
A4
A8
4
25
A3
A9
5
24
A2
A10
6
23
A1
A11
7
22
OE
A12
8
21
A0
A13
9
20
CE
A14
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
VSS
14
15
I/O3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 TSOP I (8 x 13.4 mm)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0
CE
I/O7
I/O6
I/O5
I/O4
I/O3
VSS
I/O2
I/O1
I/O0
A14
A13
A12
28 SOJ
Document #: 38-05408 Rev. *C
A5
1
28
VCC
A6
2
27
WE
A7
3
26
A4
A8
4
25
A3
A9
5
24
A2
A10
6
23
A1
A11
7
22
OE
A12
8
21
A0
A13
9
20
CE
A14
10
19
I/O7
I/O0
11
18
I/O6
I/O1
12
17
I/O5
I/O2
13
16
I/O4
VSS
14
15
I/O3
Page 2 of 13
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CY7C199C
Pin Description
Pin
Type
Description
DIP
SOJ
TSOP I
1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
21, 23, 24, 25, 26
1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
21, 23, 24, 25, 26
2, 3, 4, 5, 8, 9, 10, 11, 12,
13, 14, 15, 16, 17, 28
AX
Input
Address Inputs
CE
Control
Chip Enable
20
20
27
I/OX
Input or
Output
Data
Input/Outputs
11, 12, 13, 15, 16, 17,
18, 19
11, 12, 13, 15, 16, 17, 18,
19
18, 19, 20, 22, 23, 24, 25,
26
OE
Control
Output Enable
22
22
1
VCC
Supply
Power (5.0V)
28
28
7
VSS
Supply
Ground
14
14
21
WE
Control
Write Enable
27
27
6
Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.)
Parameter
Description
Value
Unit
TSTG
Storage Temperature
–65 to +150
°C
TAMB
Ambient Temperature with Power Applied (i.e., case temperature)
–55 to +125
°C
VCC
Core Supply Voltage Relative to VSS
–0.5 to +7.0
V
VIN, VOUT
DC Voltage Applied to any Pin Relative to VSS
–0.5 to VCC + 0.5
IOUT
Output Short-Circuit Current
20
VESD
Static Discharge Voltage (per MIL-STD-883, Method 3015)
> 2001
V
ILU
Latch-up Current
> 200
mA
V
mA
Operating Range
Range
Ambient Temperature (TA)
Voltage Range (VCC)
0°C to 70°C
5.0V ± 10%
–40°C to 85°C
5.0V ± 10%
Commercial
Industrial
DC Electrical Characteristics Over the Operating Range [2]
12 ns
Parameter
Description
Condition
15 ns
20 ns
Min.
Max.
Min.
Max.
Min.
Max.
Unit
VIH
Input HIGH Voltage
2.2
VCC + 0.3
2.2
VCC + 0.3
2.2
VCC + 0.3
V
VIL
Input LOW Voltage
–0.5
0.8
–0.5
0.8
–0.5
0.8
V
VOH
Output HIGH Voltage VCC = Min., IOH = –4.0 mA
2.4
VOL
Output LOW Voltage VCC = Min., IOL = 8.0 mA
IIX
Input Leakage
Current
GND ≤ VI ≤ VCC
–5
+5
–5
+5
IOZ
Output Leakage
Current
GND ≤ VI ≤ VCC, Output
Disabled
–5
+5
–5
+5
ICC
VCC Operating
Supply Current
VCC = Max., IOUT = 0 mA,
f = FMAX = 1/tRC
85
ISB1
Automatic CE
Max. VCC, CE ≥ VIH, VIN ≥
Power-down Current VIH or VIN ≤ VIL, f = FMAX
TTL Inputs
30
ISB2
Automatic CE
Max. VCC, CE ≥ VCC – 0.3V,
Power-down Current VIN ≥ VCC – 0.3V, or VIN ≤
0.3V, f = 0
CMOS Inputs
2.4
0.4
L
0.4
V
0.4
V
–5
+5
µA
–5
+5
µA
80
75
mA
30
30
mA
10
10
L
2.4
10
500
mA
10
mA
µA
Note:
2. VIL (min) = –2.0V for pulse durations of less than 20 ns.
Document #: 38-05408 Rev. *C
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CY7C199C
Capacitance[3]
Max.
Parameter
Description
CIN
Input Capacitance
COUT
Output Capacitance
Conditions
ALL – PACKAGES
Unit
TA = 25°C, f = 1 MHz,
VCC = 5.0V
8
pF
8
Thermal Resistance[4]
Parameter
Description
ΘJA
Thermal Resistance
(Junction to Ambient)
ΘJC
Thermal Resistance
(Junction to Case)
Conditions
Still Air, soldered on a 3 × 4.5
square inch, two–layer printed
circuit board
TSOP I
SOJ
DIP
Unit
88.6
79
69.33
°C/W
21.94
41.42
31.62
AC Test Loads and Waveforms
R1
VCC
C1
INCLUDING
JIG AND
SCOPE
output load
R1
VCC
C2
R2
INCLUDING
JIGAND
SCOPE
(a)
ALL INPUT PULSES
3.0V
R2
GND
10%
90%
90%
10%
≤ 1V/ns
≤ 1V/ns
(b)
output load for tHZOE, tHZCE, tHZWE
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
Rth
VT
Notes:
3. Tested initially and after any design or process change that may affect these parameters.
4. Test Conditions assume a transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
Document #: 38-05408 Rev. *C
Page 4 of 13
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CY7C199C
AC Test Conditions
C1
C2
R1
Parameter
Capacitor 1
Capacitor 2
Resistor 1
Description
Nom.
30
5
480
R2
RTH
VTH
Resistor 2
Resistor Thevenin
Voltage Thevenin
255
167
1.73
Unit
pF
Ω
V
AC Electrical Characteristics[5, 6, 7]
12 ns
Parameter
Description
Min
15 ns
Max
12
Min
20 ns
Max
15
Min
Max
tRC
Read Cycle Time
tAA
Address to Data Valid
tOHA
Data Hold from Addres Change
tACE
CE to Data Valid
tDOE
OE to Data Valid
tLZOE
OE to Low Z
tHZOE
OE to High Z
tLZCE
CE to Low Z
tHZCE
CE to High Z
tPU
CE to Power-up
tPD
CE to Power-down
tWC
Write Cycle Time
12
15
20
ns
tSCE
CE to Write End
9
10
15
ns
tAW
Address Set-up to Write End
9
10
15
ns
tHA
Address Hold from Write End
0
0
0
ns
tSA
Address Set-up to Write Start
0
0
0
ns
tPWE
WE Pulse Width
8
9
15
ns
tSD
Data Set-up to Write End
8
9
10
ns
tHD
Data Hold from Write End
0
0
0
ns
tHZWE
WE LOW to High Z
tLZWE
WE HIGH to Low Z
12
3
15
3
12
3
7
0
5
3
7
5
ns
ns
ns
ns
20
10
3
ns
ns
9
7
3
9
0
15
7
ns
9
7
12
20
3
0
ns
ns
0
3
0
ns
20
15
5
0
3
20
Unit
ns
ns
ns
Notes:
5. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
6. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any
of these signals can terminate the write. The input data set–up and hold timing should be referenced to the leading edge of the signal that terminates the write.
7. tHZOE, tHZCE, tHZWE are specified as in part (b) of the A/C Test Loads. Transitions are measured ± 200 mV from steady state voltage.
Document #: 38-05408 Rev. *C
Page 5 of 13
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CY7C199C
Data Retention Characteristics[8]
ALL
Parameter
Description
VDR
VCC for Data Retention
ICCDR
Data Retention Current
tCDR
Chip Deselect to Data
Retention Time
tR
Operation Recovery Time
Condition
VCC = VDR=2.0V, CE ≥ VCC – 0.3V,
VIN ≥ VCC – 0.3V or VIN ≤ 0.3V
Min.
Max.
Unit
2.0
–
V
–
150
µA
0
–
ns
200
–
µs
Timing Waveforms
Data Retention Waveform
VCC
DATA RETENTION MODE
tCDR
tR
CE
Read Cycle No. 1[11, 10]
tRC
Address
tAA
tOHA
Data Out
Previous Data Valid
Data Valid
Notes:
8. L-version only.
9. Device is continuously selected. OE = VIL = CE.
10. WE is HIGH for Read Cycle.
Document #: 38-05408 Rev. *C
Page 6 of 13
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CY7C199C
Timing Waveforms (continued)
Read Cycle No. 2[11, 12]
tRC
Address
CE
tHZCE
tACE
OE
tDOE
tHZOE
tLZOE
High Z
High Z
Data Out
VCC
Current
Data Valid
tLZCE
tPU
ICC
tPD
50%
ISB
50%
Write Cycle No. 1 (WE Controlled)[13, 14, 15]
tWC
Address
tSCE
CE
tAW
tSA
tHA
tPWE
WE
OE
tHD
tHZOE
Data In/Out
Undefined
see footnotes
tSD
Data-In Valid
Notes:
11. This cycle is OE Controlled and WE is HIGH read cycle.
12. Address valid prior to or coincident with CE transition LOW.
13. This cycle is WE controlled, OE is HIGH during write.
14. Data In/Out is high impedance if OE = VIH.
15. During this period the I/Os are in output state and input signals should not be applied.
Document #: 38-05408 Rev. *C
Page 7 of 13
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CY7C199C
Timing Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[14, 16, 17]
tWC
Address
tSCE
CE
tSA
tHA
tAW
WE
tSD
Data In/Out
High Z
tHD
High Z
Data-In Valid
Write Cycle No. 3 (WE Controlled, OE Low)[18]
t WC
Address
tSCE
CE
tAW
tHA
tPWE
tSA
WE
tSD
Data
In/Out
Undefined
tHD
Undefined
See Footnotes
Data-In Valid
see footnotes
tHZWE
tLZWE
Notes:
16. This cycle is CE controlled.
17. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
18. The cycle is WE controlled, OE LOW. The minimum write cycle time is the sum of tHZWE and tSD.
Document #: 38-05408 Rev. *C
Page 8 of 13
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CY7C199C
Truth Table
CE
WE
OE
Input/Output
Mode
Power
H
X
X
High Z
Deselect/Power-Down
Standby (ISB)
L
H
L
Data Out
Read
Active (ICC)
L
L
X
Data In
Write
Active (ICC)
L
H
H
High Z
Deselect
Active (ICC)
Ordering Information
Speed
12
Ordering Code
CY7C199C–12VC
Package
Name
51-85031
CY7C199C–12VXC
15
28-pin (300-Mil) Molded SOJ
Operating
Range
Commercial
28-pin (300-Mil) Molded SOJ (Pb-Free)
CY7C199C–12ZXC
51-85071
28-pin TSOP I (Pb-Free)
CY7C199C–12VI
51-85031
28-pin (300-Mil) Molded SOJ
Industrial
CY7C199C–15PC
51-85014
28-pin (300-Mil) DIP
Commercial
CY7C199C–15PXC
CY7C199C–15ZC
28-pin (300-Mil) DIP (Pb-Free)
51-85071
CY7C199C–15ZXC
CY7C199C–15VC
20
Package Type
28-pin TSOP I
28-pin TSOP I (Pb-Free)
51-85031
28-pin (300-Mil) Molded SOJ
CY7C199C–15VXC
28-pin (300-Mil) Molded SOJ (Pb-Free)
CY7C199CL–15VC
28-pin (300-Mil) Molded SOJ
CY7C199CL–15VXC
28-pin (300-Mil) Molded SOJ (Pb-Free)
CY7C199C–15VI
51-85031
28-pin (300-Mil) Molded SOJ
Industrial
CY7C199C–20ZXI
51-85071
28-pin TSOP I (Pb-Free)
Industrial
Document #: 38-05408 Rev. *C
Page 9 of 13
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CY7C199C
Package Diagrams
28-pin TSOP 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
Document #: 38-05408 Rev. *C
Page 10 of 13
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CY7C199C
Package Diagrams (continued)
28-pin (300-Mil) Molded SOJ (51-85031)
NOTE :
1. JEDEC STD REF MO088
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE
MIN.
MAX.
3. DIMENSIONS IN INCHES
DETAIL
A
EXTERNAL LEAD DESIGN
PIN 1 ID
14
1
0.291
0.300
15
0.330
0.350
0.013
0.019
28
OPTION 1
0.697
0.713
A
Document #: 38-05408 Rev. *C
0.014
0.020
OPTION 2
SEATING PLANE
0.120
0.140
0.050
TYP.
0.026
0.032
0.007
0.013
0.004
0.025 MIN.
0.262
0.272
51-85031-*C
Page 11 of 13
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CY7C199C
Package Diagrams (continued)
28-pin (300-Mil) PDIP (51-85014)
SEE LEAD END OPTION
14
1
DIMENSIONS IN INCHES [MM] MIN.
MAX.
REFERENCE JEDEC MO-095
0.260[6.60]
0.295[7.49]
15
PACKAGE WEIGHT: 2.15 gms
28
0.030[0.76]
0.080[2.03]
SEATING PLANE
1.345[34.16]
1.385[35.18]
0.290[7.36]
0.325[8.25]
0.120[3.05]
0.140[3.55]
0.140[3.55]
0.190[4.82]
0.115[2.92]
0.160[4.06]
0.015[0.38]
0.060[1.52]
0.090[2.28]
0.110[2.79]
0.009[0.23]
0.012[0.30]
0.055[1.39]
0.065[1.65]
3° MIN.
0.310[7.87]
0.385[9.78]
0.015[0.38]
0.020[0.50]
SEE LEAD END OPTION
LEAD END OPTION
51-85014-*D
(LEAD #1, 14, 15 & 28)
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05408 Rev. *C
Page 12 of 13
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C199C
Document History Page
Document Title: CY7C199C 256K (32K x 8) Static RAM
Document Number: 38-05408
REV.
ECN No.
Issue
Date
Orig. of
Change
Description of Change
**
129233
09/11/03
HGK
New Data Sheet
*A
129697
09/15/03
KKV
Minor change:
Move Product Portfolio from page 4 to page 1
Move Truth table from page 9 to page 3
*B
341574
See ECN
PCI
Added Lead-Free part to Ordering info on Page #10
*C
492500
See ECN
NXR
Removed 25 ns speed bin
Changed the description of IIX from Input Load Current to Input Leakage
Current in DC Electrical Characteristics table
Removed IOS parameter from DC Electrical Characteristics table
Updated the ordering information table
Document #: 38-05408 Rev. *C
Page 13 of 13
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