CS8130 Semiconductor Corporation Multi-Standard Infrared Transceiver Features General Description • Adds IR port to standard UART • IrDA, HPSIR, ASK (CW) & TV remote The CS8130 is an infrared transceiver integrated circuit. The receive channel includes on-chip high gain PIN diode amplifier, IrDA, HPSIR, ASK & TV remote compatible decoder, and data pulse stretcher. The transmit path includes IrDA, HPSIR, ASK & TV remote compatible encoder, and LED driver. The computer data port is standard UART TxD and RxD compatible, and operates from 1200 to 115200 baud. compatible • 1200bps to 115kbps data rate • Programmable Tx LED power • Programmable Rx threshold level • Power down modes • Direct, no modulation, mode • Tiny 5x7mm 20 pin SSOP package • +2.7V to +5.5V supply External PIN diode and transmit LED are required. A control mode is provided to allow easy UART programming of different modes. The CS8130 operates from power supplies of +2.7V to +5.5V. Ordering Information: CS8130-CS 0° to 70°C CDB8130 Evaluation kit +Supply +Supply VA+ VD+ 8 PINA PINC 12 11 6 13 Threshold Detect/Decode PIN Diode Preamplifier 7 RESET RXD RxD Demodulator 16 FORM/BSY CTS +Supply LED1C 1 LED Driver 1 LED2C 4 LED Driver 2 14 Data/Control Decoder FIFO Modulator 15 3 TGND2 Baud Rate Generator 2 TGND1 5 AGND Preliminary Product Information Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 20-pin SSOP 19 EXTCLK 17 10 18 9 XTALIN XTALOUT TXD STANDARD UART TxD D/C DTR PWRDN 20 CLKFR DGND This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice. Copyright Crystal Semiconductor Corporation 1994 (All Rights Reserved) JUN ’94 DS134PP2 1 CS8130 TRANSMITTER DRIVER CHARACTERISTICS (TA = 25 °C; All V+ = 3.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = V+; unless otherwise specified) Parameter Symbol Output capacitance (Note 1) Output rise time (10% to 90%) tr Output fall time (90% to 10%) tf Overshoot over final current On resistance Off leakage current Output current (each driver) (Note 2) Output jitter relative a jitter free input clock Notes: 1. Typical LED junction capacitance is 20pF. 2. 50% duty cycle, max pulse width 165 µs (3/16 of (1/1200 bps + Min Typ Max Units - 10 20 20 - TBD 50 50 25 0.5 20 250 200 pF ns ns % Ω µA mA ns 5%)). RECEIVER CHARACTERISTICS (TA = 25 °C; All V+ = 3.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = V+; unless otherwise specified) Parameter Symbol Min Typ Max Units Input capacitance (Note 3) 10 TBD pF Input noise current 11 pA/rtHz Maximum signal input current from detector 2 mA Maximum DC input current (typically sunlight) 200 µA Input current detection thresholds RS4-0=00000: 7.8 nA (Programmable with a 5 bit value) RS4-0=00001: 15.6 nA 16.4 23.4 30.4 nA (Min, Max = Typical ±30%) RS4-0=00010: " ↓ ↓ ↓ (Note 4) ↓ nA 169.5 242.2 314.9 RS4-0=11110: nA 175 250 325 RS4-0=11111: Bandpass filter response High Pass -3dB: 35 kHz Low Pass -3dB: 700 kHz 5 10 ms Receiver power up time With high (200µA) dc ambient 0.3 1 ms With normal (2µA) dc ambient Turn-around time, with receiver on continuously (Note 5) 5 10 ms EMI rejection of system (0.5MHz to 100MHz). (Note 6) 3 V/m Notes: 3. Typical PIN diode junction capacitance is 50pF. 4. The ±30% tolerance covers chip-to-chip variation. The temperature coefficient of the receiver threshold setting is low. Current detection thresholds are above the DC ambient condition. Settings of RS4-0 of less than 00010 are not practical because of noise. 5. Turn-around time is the time taken for the PIN diode receiver to recover from the IR energy from the transmitter. The remote end of the link must wait for this time after receiving data before transmitting a reply. This time may be reduced to <1 ms by good IR shielding from the transmit LED to the PIN diode. 6. This is a system specification. A metal shield over the PIN diode and CS8130 is recommended to ensure system compliance. Specifications are subject to change without notice. 2 DS134PP2 CS8130 POWER SUPPLY SPECIFICATIONS (TA = 25°C; V+ = 3.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = V+, Note 7) Parameter Symbol Min Typ Max Units Power Supply Voltage 2.7 3.0 5.5 V Power Supply Current - All functions enabled (Note 8) 2.5 mA Power Supply Current - All functions disabled (Note 9) 1 µA Power Supply Current - Receiver only enabled (Note 8) 2.5 mA Power Supply Current - Transmit only enabled (Note 10) 0.5 mA Oscillator Power Supply Current low power mode: 0.5 mA normal power mode: 1.5 mA Data & State Retention Supply Voltage 2 V Notes: 7. Power supply current specifications are with the supply at 3.0V. For approximate consumption at +5.0V, multiply the above currents by 1.667. 8. Oscillator in low power mode, does not include LED current. Subtract oscillator current if using an external clock to run the CS8130. 9. Floating digital inputs will not cause the power supply to increase beyond the specification. 10. Does not include LED current, does include oscillator current in low power mode. RECOMMENDED OPERATING CONDITIONS (All voltages with respect to 0V) Parameter Symbol Min Typ Max Units TA 0 -40 25 - 70 85 °C °C Symbol Min Typ Max Units VIH VIL VOH VOL 2.0 VD-0.3 - - COUT CIN - 5 5 0.8 0.3 0.2 0.2 - V V V V µA µA pF pF Operating Ambient Temperature Data and State Retention Temperature (In Power Down) DIGITAL PIN CHARACTERISTICS (TA = 25°C, Supply = 3.0V) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage at IO = -2.0mA Low-level Output Voltage at IO = 2.0mA Output Leakage Current in Hi-Z state Input Leakage Current Output Capacitance Input Capacitance DS134PP2 (Digital Inputs) 3 CS8130 ABSOLUTE MAXIMUM RATINGS (All voltages with respect to 0V) Parameter Symbol Min Power Supplies -0.3 Input Current Except Supply Pins & Driver Pins Input Voltage -0.3 Ambient temperature (Power Applied) -55 Storage Temperature -65 2000 ESD using human body model (100pF with series 1.5kΩ) Warning: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Max Units 6.0 ±10 VD+0.3 +125 +150 - V mA V °C °C V SWITCHING CHARACTERISTICS (TA = 25 °C; All V+ = 3.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = V+; unless otherwise specified) Parameter Symbol Min Typ Max Units XTALIN frequencies CLKFR pin low: 3.6864 MHz (Note 11) CLKFR pin high: 1.8432 MHz XTALIN duty cycle 45 50 55 % Crystal Oscillator start up time 25 ms Notes: 11. In normal oscillator mode, the crystal is internally loaded with 20 pF, which is the standard loading at which the crystal frequency is tuned. In low power oscillator mode, the internal loading on the crystal is reduced to approximately 5pF. The crystal frequency will therefore increase by about 0.03% in low power mode. 4 DS134PP2 CS8130 Ferrite Bead 10 Ω +3.0V supply + 0.1 µF To LED 0.1 µF VA+ 10 µF TGND1, 2 VD+ AGND PINC RXD RxD PINA FORM/BSY EXTCLK CTS PIN Diode + Supply LED2 LED1 XTALIN 47 µF + CS8130 XTALOUT R1 TBD Ω 3.6864 MHz or 1.8432 MHz. Can also use an external clock at 3.6864 MHz or 1.8432 MHz UART TXD TxD D/C DTR LED1C R2 TBD Ω RTS LED2C Use: LED1/R1 or:LED1/R1 & R2 or: LED1/R1 & LED2/R2 RESET TGND1 TGND2 For 2 LED, +5V supply systems, connect 2 LEDs in series. Use R1 & R2 to give programmable output level. PWRDN DGND System Control CLKFR CLKFR low for 3.6864 MHz clock CLKFR high for 1.8432 MHz clock Figure 1. Recommended Connection Diagram DS134PP2 5 CS8130 OVERVIEW The CS8130 is an infrared transceiver I.C. The receive channel includes on-chip high gain PIN diode amplifier, IrDA, HP-SIR, 500 kHz Amplitu de Shift Keyin g (ASK) & TV remote compatible decoder, and data pulse stretcher. The transmit path includes IrDA, HPSIR, 500 kHz ASK & TV remote compatible encoder, and LED drivers. The computer data port is standard UART TxD and RxD compatible, and operates from 1200 to 115200 baud. An on-chip baud rate generator is provided. External PIN diode and transmit LED(s) are required. A control mode is provided to allow easy UART programming of different modes. The CS8130 operates from power supplies of +2.7 V to +5.5 V. The device is supplied in a 20pin SSOP package Serial Infrared (SIR) Physical Layer Link Specification, Version 1.0, April 27 1994). Figure 2 shows the format of Mode 1. A pulse of IR energy indicates a logic ’0’. No IR indicates a logic ’1’. The pulse can be from 3/16 of a bit cell time at 115200 (~1.6 µs), to 3/16 of a bit cell time at 2400 bps (~78 µs). The width of the pulse may be fixed at 1.6µs for all baud rates, or may scale with the baud rate. The initial baud rate for IrDA is 9600 bps, with a negotiated baud rate possibility of 2400 to 115200 bps. Mode 2 500 kHz ASK Figure 3 shows the infrared data format for Mode 2. This is a Carrier Wave (CW) type system, where the presence of a 500kHz carrier is treated as a ’0’, and absence of a carrier is treated as a ’1’. Normally used baud rates are 9600 bps, 19.2 kbps and 38.4 kbps. Mode 3 38 kHz ASK (TV remote mode) FUNCTIONAL DESCRIPTION The following pages describe the detailed operation of the CS8130. IR Data Formats The CS8130 supports three infrared data transmission formats: IrDA/HPSIR, 500kHz ASK and 38kHz ASK (TV Remote). There is also a direct access mode, which bypasses the CS8130 encoder and decoders, and gives direct access to the IR raw data. This mode is for situations where the encoding and/or decoding is done externally. Modes may be set independently for transmit and receive, although this would be unusual. Mode 1 IrDA/HP-SIR The CS8130 is designed to allow easy realization of an IrDA compatible IR port (see IrDA 6 Figure 4 shows the infrared data format for Mode 3, the TV remote control mode. This is similar to Mode 2, except that the modulation frequency is ~38kHz. The IR bit rate is approximately 2400 bps. Both modulation frequency and bit rate vary significantly for different manufacturer and model remote controls. Mode 4 Direct Access Mode In Mode 4, the IR transmission tracks directly what is present on the TXD pin. A logic ’1’ means that the LED is off, a logic ’0’ means that the LED is on. Care must be taken to ensure that the LED is not ’on’ continuously, otherwise the LED may be damaged. In Mode 4, received IR is compared against the programmed threshold. The resulting logic output is routed directly to the RXD pin. A logic ’1’ means no IR is detected, a logic ’0’ means IR is being detected. If a IR carrier is being received, DS134PP2 CS8130 1 0 1 TXD TRANSMITTER On Off * LED Output B Light No Light PIN Input RECEIVER ** RXD A: 1/baud rate B: 3/16 of 1/115200 or 3/16 of A (selectable) C: 3/16 of 1/115200 to 3/16 of A C * LED1C and LED2C go low to turn on LED. ** RXD output is delayed from the PIN diode input by A (1 bit). A Figure 2. Infra Red Data Format Mode 1 (IRDA/HPSIR) 1 0 1 TXD TRANSMITTER On Off LED Output B Light No Light PIN Input RECEIVER C RXD A: 1/baud rate B: 1/527kHz C: 1/500kHz +/- 10% A Figure 3. Infra Red Data Format Mode 2 (500kHz ASK) 1 0 1 TXD Data * TRANSMITTER On Off LED Output B Light No Light PIN Input C RECEIVER RXD Data * A: 1/2400 B: 1/38.4kHz C: 1/40kHz +/- 10% These numbers are typical values. TV Remote Bit Rate and Modulation Frequency are programmable. A * The timing of data on the RXD and TXD pins is faster than shown here Figure 4. Infra Red Data Format 3 (TV Remote, 38kHz ASK) DS134PP2 7 CS8130 then the RXD pin will oscillate at the carrier frequency. Transmit Path Data for transmission is input to the CS8130 on the TXD pin. The selected modulation scheme is then applied to the data, and the resulting signals are used to drive the LED. There are 2 LED output pins: LED1C and LED2C. They are open drain outputs, which pull down to TGND or float. The LED is connected via resistors to both LED1C and LED2C. The current level flowing through the LED is determined by the external resistors. Normally, LED1C is used to drive the LED. If additional current is needed, (for example for TV remote operation), then the second driver may be enabled. The amount of ’boost’ current is determined by the external resistor connected to the LED2C pin. put pulse timing. However, the CS8130 now has to be programmed with the desired number of bits per character, which for IrDA compliance, is 8. Alternatively, the CS8130 can generate output pulses based entirely on individual transitions on TXD, with no knowledge of which bit is the start bit. Thus a 1 to 0 transition will generate a pulse based on that transition edge. If TXD is low for multiple successive bits, then the CS8130 will generate pulses based on its internal clock. Therefore there is the possibility of jitter in the output pulses of N*271 ns. N can be 0, 1 2....., depending on the difference in frequency between the UART baud rate clock and the CS8130 clock. Clearly, if the CS8130 and its associated UART are running from the same clock, the possibility of jitter is eliminated. Mode 2 (ASK) Transmit Choices For larger amounts of IR output, it may be preferable to use two LEDs, rather than drive a large current through one LED. For a +3V supply system using two LEDs, each one is connected, via a resistor, to each driver output. For a +5V supply system, 2 LEDS may be connected in series, and then routed to each driver via 2 resistors, one for each driver. This minimizes the power dissipation in the resistors. Mode 1 Transmit Choices In Mode 1 (IrDA), the pulse width may be fixed at 1.6 µs, or set to 3/16 of the bit period. Either of these settings will meet the IrDA standard, but fixed 1.6 µs pulses will save power at lower baud rates. In addition, there is a choice which affects the output pulse jitter. The default state causes the CS8130 to look for the start bit on TXD. All subsequent LED transitions for that character are timed relative to the internal baud rate clock. Therefore there will be no jitter in the LED out8 The modulation frequency is determined by the modulator divider registers. For nominal 500 kHz, use a divide value of 6, which yields a modulation frequency of 527 kHz. Mode 3 (TV Remote) Transmit Choices During transmission of IR, the start and stop bits present in the incoming data from the UART are stripped off (see Figure 5). The remaining data bits are then sent out at ~2400 bps. Since there should be no gaps in the transmitted data, the input data is buffered in a 22-character location FIFO. Characters can be received on the TXD pin while the previous characters are being transmitted. To prevent overflow, a hardware handshake mechanism is provided. If the FIFO is one character away from being full, the FORM/BSY pin is brought high, indicating that the UART should not send any more data. Once another character has been transmitted, FORM/BSY pin is brought low, indicating to the UART that it is OK to send another character. DS134PP2 CS8130 The modulation frequency is determined by the modulator divider registers. The transmit bit rate is determined by the TV Remote transmit bit rate divider. The UART to CS8130 baud rate must be set to at least 20% faster than the transmit bit rate. the format of incoming data. If high, then the incoming data is in IrDA/HPSIR format. If low, the data is in ASK format which matches the programmed modulation frequency. Receive Path For Mode 1a, a logic circuit is set to only look for pulse widths of 1.6µs. For Mode 1b, a logic circuit looks for pulses of 3/16 of the set baud rate bit period. For Mode 1c, a logic circuit looks for pulse widths of ≥1.6 µs, but ≤3/16 of the set baud rate bit period. Mode 1 (IrDA) Receive Choices A PIN diode is attached to the PINA and PINC pins. Compensation for the DC ambient light is applied to the photocurrent from the diode. The change in photocurrent from ambient is amplified and compared to a threshold value. If the photocurrent is greater than the set threshold, the output is set to ’light’. If the photocurrent is less than the set threshold, the output is set to ’no light’. The threshold current is programmable. This allows users to make the tradeoff between noise immunity and the reliable transmission distance of the link. The PIN diode amplifier has a bandpass filter characteristic, to limit the effects of IR interference. The resulting logic signal is further qualified, depending on the IR format selected. Mode 2 (ASK) Receive Choices For Mode 2, a logic circuit looks for sequences of ’light’ and ’no light’ which matches the expected 500kHz carrier. The modulator divider registers must be set to 6. The ASK receive timing sensitivity register should be set to 0, yielding a valid incoming frequency range of 461 kHz to 614 kHz. The RXD data transitions will lag behind the infrared activity by 3 modulation cycles. This allows the modulation detect circuit time to verify the correct modulation frequency. An autodetect feature is provided. If autodetect mode is enabled, and transmit TV remote mode is disabled, the FORM/BSY output pin indicates Start Bit TXD* Stop Bit 1 0 1 1 0 0 0 1 TXD* A B C FORM/BSY 1/2400 LED OUTPUT 1 0 1 1 0 A 0 0 1 1 0 0 1 1 B 0 0 0 ON OFF 1 C * TXD Baud rate can be set from 4800 to 115200 bps Figure 5. Mode 3 (TV Remote) Transmit Data Format DS134PP2 9 CS8130 Mode 3 (TV remote) Receive Choices ing register to a rate which is less than 80% of the UART baud rate. The CS8130 will now start sampling the demodulated infrared data at the TV remote receive sample rate. The stream of samples will be assembled into characters, with a start bit and a stop bit, and will be transmitted to the UART via RXD at the UART baud rate. The system software can then concatenate successive characters and reconstruct the incoming bit stream. The modulation frequency must be set into the modulator divider registers. The tolerance on the expected frequency must be programmed into the Receive ASK Timing Sensitivity (RATS) register. The RATS register sets the time window that the demodulator will accept for the period of valid data. Since the RATS register specifies time windows which are negative (e.g. 1000b (8) = +0.27 µs to -4.61 µs), then the modulation frequency must be set to lower than the desired nominal setting. For example, with RATS set to 1000 (8), and the desired nominal frequency being 38 kHz, then set the modulation divider registers to 35.10 kHz. With these settings, the demodulator will accept any frequency from 34.78 kHz to 41.88 kHz as valid. Smaller RATS register settings will result in tighter tolerance on the accepted receive modulation frequency. Changes in the RATS register settings must be accompanied by changes in the modulation frequency register to keep the nominal desired frequency in the center of the valid frequency band. "Programmed T period" mode requires that the bit period of the bursts of modulated carrier be known. This period is programmed into the TV remote receive timing registers. The UART to CS8130 baud rate must be set to at least 20% greater than 1/T. The CS8130 will now use the edges of the demodulated incoming infrared data to indicate each bit state. For continuous periods of low or high, the CS8130 will sample the level in the center of each incoming bit period (using T as the bit period). Any transition will reset the timer that is used for the sampling process, thereby eliminating errors caused by the sample timing being different to the incoming bit period. Characters are assembled and sent to the UART every 8 bits (see Figure 6). There are two TV remote receive data modes: "oversampled" mode and "programmed T period" mode. For "oversampled" mode, first choose the UART to CS8130 baud rate, typically 115.2 kbps. Then set the TV remote receive tim- LIGHT INPUT 1 0 1 1/2400 1 0 0 1 1 1 If the T period is not known, it is possible to measure T by using "oversampled" mode, and 0 0 1 1 0 0 1 0 0 1 LIGHT NO LIGHT RXD* 1 RXD* 0 1 1 0 0 1 1 8 data bits Start Bit Stop Bit *RXD Baud rate can be set from 4800 to 115200 bps Figure 6. Mode 3 (TV remote) Receive Data Format 10 DS134PP2 CS8130 then switch to "programmed T period" mode to reduce processing overhead in the host CPU. external clock, then RESET low can be short (>1 µs). Clock Generation Power Down The primary clock required is 3.6864 MHz. This may be generated by attaching a 3.6864 MHz crystal to the XTALIN and XTALOUT pins. In this case, the EXTCLK pin becomes an output, and may be used to drive external devices. If this is not required, power may be saved by disabling the EXTCLK output. The CLKFR pin should be connected to DGND, which causes the clock circuits to be configured for 3.6864 MHz operation. When the PWRDN pin is brought low, all internal logic is stopped, including the crystal oscillator. The power consumption in power down mode is very low (<1 µA). When the PWRDN pin is brought high, the crystal oscillator will start. If using the crystal oscillator, allow 25 ms for oscillator start up after bringing PWRDN high, before trying to use the CS8130. The control register status will not be changed by toggling PWRDN. The oscillator has a low power mode. This reduces the internal crystal loading capacitance on XTALOUT and XTALIN. The selection of this mode is via a bit in Control Register #4. Since the loading capacitance is reduced, then the crystal frequency will increase by approximately 0.03%. Alternatively, a 3.6864 MHz clock may be input into the EXTCLK pin, in which case XTALIN must be grounded, and XTALOUT is left floating. The CLKFR pin must be connected to DGND. If only a 1.8432 MHz clock is available, then it may be input into the EXTCLK pin and the CLKFR pin connected to VD+. This causes the CS8130 to double the incoming 1.8432 MHz clock to 3.6864 MHz for internal use. XTALIN must be grounded, and the XTALOUT pin is left floating. The CS8130 automatically sets the direction of the EXTCLK pin. If the crystal oscillator is running when RESET goes high, then EXTCLK becomes an output. Since the crystal oscillator can take up to 25 ms to start, then it follows that RESET must be held low, with PWRDN high and power applied, for at least 25 ms. If using an DS134PP2 Control Register #1 allows for individual disabling and enabling of the transmit and receive sections of the CS8130. The CS8130 also goes into power down if both transmit enable and receive enable bits are false, and the D/C pin is brought high. This allows control of power down in a pod environment, where access to the PWRDN pin is difficult. In this mode, it is possible to select, via a control register bit, whether the crystal oscillator remains running, or is powered off. If the oscillator remains running, then it consumes power, but offers instant wake up. If the oscillator is powered off, then it consumes no power, but will take 25 ms to start up. The PWRDN pin must always be ’high’ or ’low’. If this pin is allowed to float, excessive power consumption may occur. All other digital inputs may be allowed to float without causing excessive power consumption in the CS8130 in power down mode. The RXD and FORM/BSY output pins may be programmed to be high, low or float in power down. This allows maximum flexibility in different applications. 11 CS8130 Reset register is always accessible, independent of the state of the shadow bit. The shadow bit must be written to 0 to enable access to registers 0 through 15. Bringing the RESET pin low will force the internal logic, including the control registers, into a known state, provided the PWRDN pin is high. RESET is disabled if the PWRDN pin is low. The reset state is given in each register definition table. RESET must be low for >25 ms if using the crystal oscillator (see Clock Generation above). The following tables define the detailed function of all the registers inside the CS8130. Control Register Definitions The various control registers within the CS8130 may be written by setting the D/C pin to low, and sending characters from the UART to the TXD pin. The characters are interpreted as a 4bit address field and a 4-bit data field, as shown in Figure 7. After the control character is received and written into the control register, it is optionally echoed back out the RXD pin. The baud rate used for this control mode is whatever is currently set in the baud rate register. If the "load baud rate" bit is written to, then the new baud rate takes effect after the character has been echoed back, if echo is enabled. Otherwise, the new baud rate is effective immediately. One of the control registers contains a shadow register set enable bit, which effectively becomes the MSB of the 5-bit register address. Hence there are 31 4-bit registers. The shadow bit must be written to a 1 to allow access to the registers with addresses 16 through 31. The shadow bit Start Bit TXD Data CD0 CD1 CD2 Stop Bit Address CD3 AD0 AD1 AD2 AD3 D/C Start Bit RXD Data CD0 CD1 CD2 Stop Bit Address CD3 AD0 AD1 AD2 AD3 Figure 7. Control Mode Timing 12 DS134PP2 CS8130 Control Data Byte Format BIT D7 D6 D5 D4 D3 D2 D1 D0 AD3 AD2 AD1 AD0 CD3 CD2 CD1 CD0 NAME AD3-0 Register Address (4 bits of transmitted address + MSB, which is the shadow (SHDW) bit state [Control Reg #3]. All registers have 4 data bits). CD3-0 Control Data VALUE 0_0000 0_0001 0_0010 0_0011 0_0100 0_0101 0_0110 0_0111 0_1000 0_1001 0_1010 0_1011 0_1100 0_1101 0_1110 0_1111 1_0000 1_0001 1_0010 1_0011 1_0100 1_0101 1_0110 1_0111 1_1000 1_1001 1_1010 1_1011 1_1100 1_1101 1_1110 1_1111 FUNCTION 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Control register #1 Control register #2 Transmit Mode Register #1 Transmit Mode Register #2 Output Power register Receive Mode register Receive Sensitivity register #1 Receive Sensitivity register #2 Baud Rate Divider register #1 Baud Rate Divider register #2 Modulator Divider register #1 Modulator Divider register #2 Digital Output Pin Control register Control Register #3 Reserved Status register (read only) TV Remote Receive Sample Rate & T Period Divider TV Remote Receive Sample Rate & T Period Divider TV Remote Receive Sample Rate & T Period Divider TV Remote Transmit Bit Rate Divider #1 TV Remote Transmit Bit Rate Divider #2 Control Register #4 Reserved Reserved ASK Receive Timing Sensitivity register Reserved Reserved Reserved CS8130 Revision Level register (Read Only) Reserved Reserved (Resets to 1111; must not be changed) Reserved (Resets to 1111; must not be changed) Contains control register data. It is essential that all reserved registers and bits are not changed from their reset state. If reserved bits are changed, then internal test modes may be invoked, which may change some input pins to output pins, and may completely change the definition of some functions and signals. Reserved bits in registers, and reserved registers, may not return a known state when read, and should be ignored. Registers 28 and 15 are read only. Other non-reserved registers are write only. The CS8130 can be set to echo back register write commands to verify correct reception of the control settings. DS134PP2 13 CS8130 Register 0, Control Register #1 D3 D2 D1 D0 Register ECHO 0 RXEN TXEN Reset (R) 0 0 0 0 BIT ECHO RXEN NAME Echo Control Characters Receiver Enable TXEN Transmitter Enable VALUE 0 1 0 1 0 1 FUNCTION R Do not echo control characters Echo control characters. R Receiver disabled Receiver enabled R Transmitter disbabled Transmitter enabled VALUE 0 1 0 1 FUNCTION R Auto detect receive format disabled Auto detect receive format enabled R Do not load new baud rate count value Load new baud rate count value Register 1, Control Register #2 D3 D2 D1 Register 0 0 AUTD Reset (R) 0 0 0 BIT AUTD LODB NAME Receiver auto detect mode enable Load Baud Rate Counter D0 LODB 0 The LODB bit resets to 0 automatically. 14 DS134PP2 CS8130 Register 2, Transmit Mode Register #1 D3 D2 D1 Register DIR TVR PWID Reset (R) 0 0 0 BIT DIR NAME Direct Mode Enable TVR TV Remote Mode Enable Select Pulse Width PWID MODU D0 MODU 0 VALUE 0 1 0 1 0 1 0 1 Select Modulation Method R R R R FUNCTION Mode 4 Direct access mode disabled Mode 4 Direct access mode enabled Mode 3 TV remote mode disabled Mode 3 TV remote mode enabled Set pulse width to 1.6 µS Set pulse width to 3/16 of the bit period Mode 1 IrDA pulse modulation enabled Mode 2 Amplitude modulated carrier modulation Register 3, Transmit Mode Register #2 D3 D2 D1 D0 Register 0 CHSY BC1 BC0 Reset (R) 0 1 1 BIT CHSY BC1-0 0 NAME Character/bit synchronized Number of bits per character (only needed if CHSY = 1) VALUE 0 1 00 01 10 11 0 1 2 3 FUNCTION Bits are transmitted based on TXD bit transitions R Bits are transmitted timed from the start bit 6 data bits per character 7 data bits per character R 8 data bits per character 9 data bits ( 8 data, 1 parity) per character 0 1 2 3 FUNCTION R No LED output enabled LED1C output only enabled LED2C output only enabled Both LED1C and LED2C outputs enabled Register 4, Output Power Register D3 D2 D1 D0 Register 0 0 OP1 OP0 Reset (R) 0 0 0 0 BIT OP1-0 DS134PP2 NAME Output Power Level VALUE 00 01 10 11 15 CS8130 Register 5, Receive Mode Register D3 Register Reset (R) BIT RTVR, RMOD, RWIDS, RWIDL D2 D1 D0 RTVR RMOD RWIDS RWIDL 0 0 1 1 NAME Receive Mode VALUE 0000 0001 0010 0011 0100 1000 1100 FUNCTION 0 Mode 2 Amplitude modulated carrier mode 1 Mode 1a IRDA - fixed 1.6µs pulse 2 Mode 1b IRDA - variable 3/16 bit cell time pulse 3 R Mode 1c IRDA - Any width pulse from 1.6µs to 3/16 bit cell time 4 Mode 4 Direct access mode 8 Mode 3 TV remote mode, oversampling receive 12 Mode 3 TV remote mode, timed bit cell receive All other combinations are reserved Register 6, Receive Sensitivity Register #1 D3 D2 D1 D0 Register RS3 RS2 RS1 RS0 Reset (R) 0 1 1 1 Register 7, Receive Sensitivity Register #2 D3 D2 D1 D0 Register 0 0 0 RS4 Reset (R) 0 0 0 0 BIT RS4-0 NAME Receive threshold setting. VALUE 00000 00001 " 00111 " 11110 11111 FUNCTION 0 7.8 nA nominal receive threshold 1 15.6 nA nominal receive threshold " " 7 R 62.5 nA nominal receive threshold " " 30 242.2 nA nominal receive threshold 31 250 nA nominal receive threshold Threshold settings of less than 20nA should not be used because background noise will cause the apparent occurrence of constant signal. 16 DS134PP2 CS8130 Register 8, Baud Rate Divider Register #1 D3 D2 D1 D0 Register BR3 BR2 BR1 BR0 Reset (R) 0 1 1 1 Register 9, Baud Rate Divider Register #2 D3 D2 D1 D0 Register BR7 BR6 BR5 BR4 Reset (R) 0 0 0 1 BIT BR7-0 NAME Baud Rate Divider Value (BRD). BRD=(3.6864E6/ (16*BR))-1, where BRD = divider value and BR = desired baud rate. VALUE 01011111 00101111 00010111 00001011 00001001 00000010 00000001 FUNCTION 95 2400 bps 47 4800 bps 23 R 9600 bps 11 19.2 kbps 5 38.4 kbps 2 76.8 kbps 1 115.2 kbps Register 10, Modulator Divider Register #1 D3 D2 D1 D0 Register MD3 MD2 MD1 MD0 Reset (R) 0 1 1 0 Register 11, Modulator Divider Register #2 D3 D2 D1 D0 Register MD7 MD6 MD5 MD4 Reset (R) 0 0 0 0 BIT MD7-0 NAME Modulator Divider Value (MD). MD=(3.6864E6/FR)1, where MD = divider value and FR = desired modulation frequency. VALUE 01100000 96 38 kHz 00000110 6 R 527kHz FUNCTION The transmitted modulation frequency will be exact. The receive carrier detection frequency can be slightly different from the programmed frequency (see Receive ASK Carrier Timing Register). DS134PP2 17 CS8130 Register 12, Output Pin Control Register D3 Register Reset (R) BIT RXDT RXDH FORT FORH D2 RXDT RXDH 0 1 D1 FORT 0 D0 FORH 1 NAME RXD output pin three-state enable RXD output pin high/low enable FORM/BSY output pin three-state enable FORM/BSY output pin high/low enable VALUE 0 1 0 1 0 1 R In In In R In R In In 0 1 In power down, FORM/BSY will go low, if FORT = 0 R In power down, FORM/BSY will go high, if FORT = 0 VALUE 0 1 FUNCTION R Enable access to registers 0 though 15 Enable access to shadow registers (16 through 31) VALUE 0 FUNCTION Oscillator not running, using external clock input, oscillator circuit is powered down. Oscillator running, EXTCLK is an output, if enabled. R No error A framing error has occurred since the last read of this bit. Resets after read R IrDA pulse style data format detected Amplitude modulated carrier style data format detected power power power power power power down, down, down, down, down, down, FUNCTION RXD will go high or low. RXD will float. RXD will go low, if RXDT = 0 RXD will go high, if RXDT = 0 FORM/BSY will go high or low. FORM/BSY will float. Register 13, Control Register #3 D3 D2 D1 Register 0 0 0 Reset (R) 0 0 BIT SHDW 0 D0 SHDW 0 NAME Shadow register set enable Register 15, Status Register D3 D2 Register 0 OSCR Reset (R) 0 BIT OSCR D1 D0 ERR DMOD 0 0 NAME Oscillator running flag ERR Framing error flag 1 0 1 DMOD Detected Modulation Type 0 1 To read this register, write 0000 to address 15. Independent of the setting of the ECHO bit, the CS8130 will transmit the above contents, with an address field of 1111. 18 DS134PP2 CS8130 Register 16, TV Remote Receive Timing Register #1 D3 Register Reset (R) D2 D1 TVR3 TVR2 TVR1 1 1 1 D0 TVR0 1 Register 17, TV Remote Receive Timing Register #2 D3 D2 Register TVR7 TVR6 Reset (R) 1 1 D1 TVR5 1 D0 TVR4 1 Register 18, TV Remote Receive Timing Register #3 D3 Register Reset (R) BIT TVR11-0 D2 TVR11 TVR10 0 1 D1 TVR9 1 NAME TV remote mode receiver timing register TVR = (3.6864E6 * T) -1 where T = the incoming bit period, and TVR = this register value. D0 TVR8 1 VALUE 000000000000 000000000001 ↓ 011111111111 ↓ 111111111111 FUNCTION 0 1 ↓ 2047R ↓ 4095 T = 271 ns T = 542 ns ↓ T = 555 µs (1800 bps) ↓ T = 1.11 ms For TV remote receive "oversampled" mode, this register value determines the input data sample rate. The sample rate is 3.6864 MHz divided by this register value. The sample rate should be set to as fast as possible, to give the best resolution on the incoming data edges, but should be less than 80% of the main UART communication baud rate. For TV remote receive "programmed T period" mode, this register sets the expected incoming bit cell time (T). The main UART communications rate must be set to at least 20% greater than 1/T. DS134PP2 19 CS8130 Register 19, TV Remote Transmit Bit Rate Divider Register #1 D3 Register Reset (R) D2 D1 TBR3 TBR2 TBR1 1 1 1 D0 TBR0 1 Register 20, TV Remote Transmit Bit Rate Divider Register #2 D3 D2 Register TBR7 TBR6 Reset (R) 0 1 BIT TBR7-0 D1 D0 TBR5 1 TBR4 1 NAME TV remote mode transmit bit rate register TBR= (3.6864E6/(16*RATE)) -1 where TBR is this register value & RATE is the desired transmit bit rate. VALUE 01111111 127 R FUNCTION RATE = 1800 bps Register 21, Control Register #4 D3 Register Reset (R) BIT OSCE OSCL EXCK SRES 20 D2 D1 OSCE OSCL EXCK 0 0 0 NAME Disable crystal oscillator in D/C controlled power down state Set oscillator in low power mode Disable external clock output driver Software Reset D0 SRES 0 VALUE 0 1 0 1 0 1 0 1 FUNCTION R In D/C controlled power down state, crystal oscillator stays running. In D/C controlled power down state, crystal oscillator stops. R Oscillator in normal power, high accuracy, mode. Oscillator in low power, medium accuracy mode. R If crystal is used, enable clock output driver If crystal is used, disable clock output driver (Hi-Z) R Normal operation Causes a software reset, which forces all registers into their reset state. If ECHO is true, then the echo will occur at the current baud rate, before the baud rate changes to the default value. DS134PP2 CS8130 Register 24, Receive ASK Timing Sensitivity Register D3 Register Reset (R) BIT RAT3-0 D2 D1 RAT3 RAT2 RAT1 0 0 0 D0 RAT0 0 NAME Receiver ASK Timing Sensitivity. Timing window = +0.27 µs to -RAT(2/3.6864E06) - 0.27 µs VALUE 0000 0001 0010 ↓ 1111 0 R +0.27 1 +0.27 2 +0.27 ↓ 15 +0.27 FUNCTION µs to -0.27 µs window (500 kHz ASK mode) µs to -0.54 - 0.27 µs window µs to -1.08 - 0.27 µs window ↓ µs to -8.14 - 0.27 µs window The timing window is relative to the modulation divider register nominal setting. Register 28, CS8130 Silicon Revision Register D3 Register BIT REV3-0 D2 D1 REV3 REV2 REV1 NAME CS8130 silicon revision level D0 REV0 VALUE 0000 FUNCTION 1st silicon, designed to meet DS134PP2 data sheet, dated June 1994 This register should be read by the CS8130 driver to allow CS8130 future enhancements to be recognized, and incorporated into future versions of the driver. DS134PP2 21 CS8130 Grounding & Layout Optical Components Grounding and layout for the CS8130 are critical, because of the sensitive nature of the PIN diode amplifier. The CS8130 should be over its own dedicated ground plane. The PIN diode should be very close to the PINA and PINC pins. The PIN diode traces should be very short (< 5 mm), and should be surrounded by ground plane. There should be holes in the ground plane provided for mounting a metal shield over the CS8130 and the PIN diode for EMI shielding. The PIN diode and transmit LEDs should be positioned so as to line up the front optical surfaces of the packages. The optical surface of the PIN diode and transmit LED(s) should be positioned 1cm back from the daylight IR filter window inside the case of the equipment. This ensures that direct sunlight does not fall upon the top surface of the PIN diode. TEMIC (Tel: 408 970 5684) provides Telefunken infrared LEDs and PIN diodes which are compatible with the CS8130. Contact Crystal for details of additional qualified LED and PIN diode sources. Example Application Schematics Crystal has prepared some example schematics which demonstrate possible uses for the CS8130. Figure 8 shows a computer or PDA motherboard example, where one UART is used to drive both a wired RS232 COM port and an IR port. Figure 9 shows a pod schematic. This is an external unit which can be plugged into any existing COM port to create an IR port. An evaluation kit, CDB8130, is available from Crystal. This may be used as an example of the correct layout for the CS8130 and the optical components. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2 22 DS134PP2 CS8130 10 Ω 10 µF + 0.1 µF 5 7 BPV23NF 8 12 VA+ VD+ AGND PINA +3V RESET CS8130 RXD FORM/BSY 5.2 Ω (2) 5.2 Ω (2) 1 4 17 3.6864 MHz PINC 47 µF Notes: (1) This circuit has not yet been built and debugged. (2) Choice of LED, power consumption and physical positioning will affect R value. EXTCLK XTALOUT 6 +3V 10 µF 19 XTALIN TSHA5502 + + 0.1 µF TXD LED1C D/C LED2C PWRDN CLKFR 18 11 13 16 14 15 10 9 TGND1 TGND2 DGND 2 3 20 +3V 0.33 µF 1 5 0.33 µF CIA- EN 2 CIA+ 4 0.33 µF VCC 3 SHDN CIB- C2+ MAX562 CIB+ C2- 14 25 24 0.33 µF UART 6 DSR 23 R1IN R1OUT 6 8 CTS 22 R2IN R2OUT 7 2 RXD 21 R3IN R3OUT 8 DB9 1 Serial Connector 9 (COM PORT) 4 DCD 20 R4IN R4OUT 9 RI 19 R5IN R5OUT 10 DTR 18 T1OUT T1IN 11 7 RTS 17 T2OUT T2IN 12 3 TXD 16 T3OUT T3IN 13 5 SG V- RS-232/IR SELECT 15 DSR CTS RXD DCD RI DTR RTS TXD 26 V+ 28 GND 27 0.68 µF UART to both RS232 and IR Port Interface Motherboard Example Schematic 0.33 µF Steven Harris Crystal Semiconductor 5/26/94 Figure 8. IR and RS232 from 1 UART DS134PP2 23 CS8130 10 Ω 10 µF + 0.1 µF 5 7 BPV23NF 8 12 VA+ VD+ AGND EXTCLK PINC TSHA5502 PINA XTALIN 47 µF 5.5 Ω (2) 5.5 Ω (2) 1 4 LED1C +3V 0.33 µF 5 19 0.33 µF VCC CIB- CIA- XTALOUT 17 C2+ 18 C2- 13 11 T1IN 12 T2IN 6 R1OUT 7 R2OUT 8 R3OUT 16 FORM/BSY 14 TXD 15 D/C 11 RESET LED2C PWRDN CLKFR 10 +3V +3V 9 14 MAX562 EN Notes: (1) This circuit has not yet been built and debugged. (2) Choice of LED, power consumption and physical positioning will affect R value. (3) The creation of +3V or +5V supply is not included here. 24 26 V+ 28 GND 27 0.33 µF 25 T1OUT 18 T2OUT 17 23 R1IN 22 R2IN 21 R3IN V- 15 SHDN TGND1 TGND2 DGND 2 3 20 4 CIB+ 3 2 CIA+ 3.6864 MHz RXD +3V +3V 10 µF 1 CS8130 6 + + 0.1 µF 0.68 µF 0.33 µF RXD CTS TXD 2 8 3 DTR RTS 4 7 5 DB9 Serial Connector (COM PORT) 0.33 µF RS232 COM PORT to Infra Red Interface Pod Schematic Steven Harris Crystal Semiconductor 5/26/94 Figure 9. Example Pod Schematic 24 DS134PP2 CS8130 LED1 CATHODE TRANSMIT GROUND 1 TRANSMIT GROUND 2 LED2 CATHODE ANALOG GROUND PIN DIODE ANODE PIN DIODE CATHODE ANALOG SUPPLY CLOCK FREQUENCY POWER DOWN LED1C TGND1 TGND2 LED2C AGND PINA PINC VA+ CLKFR PWRDN 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DGND EXTCLK XTALOUT XTALIN FORM/BSY D/C TXD RXD VD+ RESET DIGITAL GROUND EXTERNAL CLOCK CRYSTAL OUTPUT CRYSTAL INPUT FORMAT/BUSY DATA/CONTROL TRANSMIT DATA RECEIVE DATA DIGITAL SUPPLY RESET Power Supplies VD+ - Digital Positive Supply. Digital positive supply voltage. Nominally +3V VA+ - Analog Positive Supply. Analog positive supply voltage. Nominally +3V. DGND - Digital Ground. Digital ground, 0V, connection. AGND - Analog Ground. Analog ground, 0V, connection. TGND1, TGND2 - Transmitter Grounds. LED Transmitter grounds, 0V, connections. Analog Pins LED1C, LED2C - Transmit LED Cathode. These pins are connected to the transmit LED cathode via resistors. Appropriate resistor choice allows user setting of LED current options. The anode of the LED is connected to the positive supply. PINC - Receiver PIN Diode Cathode Receiver PIN diode cathode. PINA - Receiver PIN Diode Anode. Receiver PIN diode anode. DS134PP2 25 CS8130 Digital Pins RXD - Receiver Data Output Receiver output data. Normally connected to RxD on the UART. TXD - Transmit Data Input Transmitter input data. Normally connected to TxD on the UART. D/C - Data/Control Mode Input The D/C pin determines whether the input data on TXD is treated as data to be transmitted via the LED, or as control information to set up the CS8130 internal registers. The D/C pin also can act as a power down control. FORM/BSY - Received Data Format Output/Busy Signal Output If auto format detect mode is enabled, this pin indicates the format of the incoming data. FORM is low for ASK format data, and high for IRDA/HPSIR format data. In TV remote data mode (Mode 3), this pin becomes a handshake signal to the UART. FORM/BSY low means OK to send a character. FORM/BSY high means "I am busy, do not send another character". PWRDN - Power Down Control Input PWRDN low places the CS8130 into a very low power consumption "off" state. RESET - Reset Input RESET low places all the internal logic into a known state. All the control register bits are forced high or low, as defined in the register definition section. If the crystal oscillator is in use, then RESET must be held low for >25 ms, with PWRDN high and power applied. If an external clock is used, then the RESET pulse can be short (>1 µs). XTALIN, XTALOUT - Crystal Connections To use the internal oscillator, connect either a 3.6864 MHz or a 1.8432 MHz crystal between XTALOUT and XTALIN. If using an external clock, connect XTALIN to DGND. EXTCLK - External Clock Input or Output If no crystal is present on XTALIN and XTALOUT, EXTCLK becomes an input. A 3.6864 MHz or 1.8432 MHz clock should be connected to EXTCLK. XTALIN should be connected to DGND. If a crystal is present on XTALIN and XTALOUT, EXTCLK becomes an output. EXTCLK will output the same frequency as the crystal. The EXTCLK output driver may be disabled to conserve power. CLKFR - Clock Frequency Select Input Tie CLKFR to ground to select a 3.6864 MHz clock. Connect CLKFR to the VD+ pin to select a 1.8432 MHz clock. 26 DS134PP2 20 PIN SSOP 28 PIN SSOP N E SSOP Package Dimensions 1 2 3 TOP VIEW D1 E 11 A2 e A A1 b2 L Seating Plane END VIEW SIDE VIEW INCHES MILLIMETERS Notes: 1. "D" and "E 1 " are reference datums and do not include mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20mm per side. 2. Dimension b does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13mm total in excess of b dimension at maximum material condition. Dambar intrusion shall not reduce dimension b by more than 0.07mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25mm from lead tips. 44 DIM MIN NOM MAX MIN NOM A - - 2.13 - - A1 0.05 0.15 0.25 0.002 A2 1.62 1.75 1.88 0.064 0.070 0.074 b 0.22 0.30 0.38 0.009 D E 7.80 0.084 0.006 0.010 0.012 0.015 2, 3 see other table see other table 7.40 MAX Note 1 8.20 0.291 0.307 0.323 E1 5.00 5.30 5.60 0.197 0.209 0.220 e 0.61 0.65 0.69 0.024 0.026 0.027 L 0.63 0.90 1.03 0.025 N ∝ 4° 0.035 0.040 see other table see other table 0° 1 8° 0° 4° 8° D MILLIMETERS N MIN NOM MAX 20 6.90 7.20 7.50 28 9.90 INCHES MIN NOM MAX 0.272 0.283 0.295 10.20 10.50 0.390 0.402 0.413 Note 1 1 Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation