19-5008; Rev 0; 12/09 TION KIT EVALUA BLE AVAILA IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Features The MAX5969A/MAX5969B provide a complete interface for a powered device (PD) to comply with the IEEE® 802.3af/at standard in a power-over-Ethernet (PoE) system. The MAX5969A/MAX5969B provide the PD with a detection signature, classification signature, and an integrated isolation power switch with inrush current control. During the inrush period, the MAX5969A/MAX5969B limit the current to less than 180mA before switching to the higher current limit (720mA to 880mA) when the isolation power MOSFET is fully enhanced. The devices feature an input UVLO with wide hysteresis and long deglitch time to compensate for twisted-pair cable resistive drop and to assure glitch-free transition during power-on/-off conditions. The MAX5969A/MAX5969B can withstand up to 100V at the input. S IEEE 802.3af/at Compliant S 2-Event Classification S Simplified Wall Adapter Interface S PoE Classification 0 to 5 S 100V Input Absolute Maximum Rating S Inrush Current Limit of 180mA Maximum S Current Limit During Normal Operation Between 720mA and 880mA S Current Limit and Foldback S Legacy UVLO at 36V (MAX5969A) S IEEE 802.3af/at-Compliant, 40V UVLO (MAX5969B) S Overtemperature Protection S Thermally Enhanced, 3mm x 3mm, 10-Pin TDFN The MAX5969A/MAX5969B support a 2-event classification method as specified in the IEEE 802.3at standard and provide a signal to indicate when probed by Type 2 power-sourcing equipment (PSE). The devices detect the presence of a wall adapter power-source connection and allow a smooth switchover from the PoE power source to the wall power adapter. Ordering Information The MAX5969A/MAX5969B also provide a power-good (PG) signal, two-step current limit and foldback, overtemperature protection, and di/dt limit. PART TEMP RANGE UVLO THRESHOLD (V) MAX5969AETB+ -40NC to +85NC 10 TDFN-EP* 35.4 MAX5969BETB+ -40NC to +85NC 10 TDFN-EP* 38.6 +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. The MAX5969A/MAX5969B are available in a space-saving, 10-pin, 3mm x 3mm, TDFN power package. These devices are rated over the -40NC to +85NC extended temperature range. Applications PINPACKAGE Pin Configuration TOP VIEW IEEE 802.3af/at Powered Devices IP Phones, Wireless Access Nodes, IP Security Cameras WiMAXK Base Station VDD 1 DET 2 N.C. 3 I.C. 4 VSS 5 + MAX5969A MAX5969B EP* 10 CLS 9 2EC 8 PG 7 WAD 6 RTN TDFN (3mm × 3mm) IEEE is a registered service mark of the Institute of Electrical and Electronics Engineers, Inc. *EP = EXPOSED PAD. CONNECT TO VSS. WiMAX is a trademark of WiMAX Forum. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX5969A/MAX5969B General Description MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET ABSOLUTE MAXIMUM RATINGS VDD to VSS...........................................................-0.3V to +100V DET, RTN, WAD, PG, 2EC to VSS........................ -0.3V to +100V CLS to VSS...............................................................-0.3V to +6V Maximum Current on CLS (100ms maximum)..................100mA Continuous Power Dissipation (TA = +70NC) (Note 1) 10-Pin TDFN (derate 24.4mW/NC above +70NC) Multilayer Board.........................................................1951mW Package Thermal Resistance (Note 2) BJA. ................................................................................4NC/W BJC.................................................................................9NC/W Operating Temperature Range........................... -40NC to +85NC Maximum Junction Temperature......................................+150NC Storage Temperature Range............................. -65NC to +150NC Soldering Temperature (reflow)..................................... +260NC Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 10 FA 25.5 kI DETECTION MODE Input Offset Current Effective Differential Input Resistance IOFFSET dR VIN = 1.4V to 10.1V (Note 4) VIN = 1.4V up to 10.1V with 1V step, VDD = RTN = WAD = PG = 2EC (Note 5) 23.95 25.00 22.0 22.8 CLASSIFICATION MODE Classification Disable Threshold VTH,CLS VIN rising (Note 6) Classification Stability Time Classification Current 23.6 0.2 ICLASS VIN = 12.5V to 20.5V, VDD = RTN = WAD = PG = 2EC V ms Class 0, RCLS = 619I 0 3.96 Class 1, RCLS = 117I 9.12 11.88 Class 2, RCLS = 66.5I 17.2 19.8 Class 3, RCLS = 43.7I 26.3 29.7 Class 4, RCLS = 30.9I 36.4 43.6 Class 5, RCLS = 21.3I 52.7 63.3 mA TYPE 2 (802.3at) CLASSIFICATION MODE Mark Event Threshold VTHM VIN falling 10.1 Hysteresis on Mark Event Threshold 10.7 11.6 0.84 Mark Event Current IMARK VIN falling to enter mark event, 5.2V P VIN P 10.1V 0.25 Reset Event Threshold VTHR VIN falling 2.8 V V 0.85 mA 4 5.2 V 60 V 0.27 0.55 mA POWER MODE VIN Supply Voltage Range VIN Supply Current IQ Measured at VDD 2 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET (VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) PARAMETER SYMBOL CONDITIONS MIN TYP MAX MAX5969A 34.3 35.4 36.6 MAX5969B 37.2 38.6 40 VIN Turn-On Voltage VON VIN rising VIN Turn-Off Voltage VOFF VIN falling MAX5969A MAX5969B VIN falling from 40V to 20V (Note 8) 30 4.2 7.3 30 tDELAY = minimum PG current pulse width after entering into power mode 80 VIN Turn-On/-Off Hysteresis (Note 7) VIN Deglitch Time VHYST_UVLO tOFF_DLY Inrush to Operating Mode Delay tDELAY Isolation Power MOSFET On-Resistance RON_ISO RTN Leakage Current IRTN_LKG IRTN = 600mA UNITS V V V 120 Fs 96 112 TJ = +25NC 0.5 0.7 TJ = +85NC 0.65 1 I TJ = +125NC 0.8 10 FA VRTN = 12.5V to 30V ms CURRENT LIMIT Inrush Current Limit Current Limit During Normal Operation IINRUSH ILIM Foldback Threshold During initial turn-on period, VRTN = 1.5V 90 135 180 mA After inrush completed, VRTN = 1V 720 800 880 mA VRTN (Note 9) 13 16.5 V VWAD rising, VIN = 14V to 48V (referenced to RTN) 8 LOGIC WAD Detection Threshold VWAD-REF WAD Detection Threshold Hysteresis WAD Input Current 0.725 VWAD = 10V (referenced to RTN) 2EC Sink Current V2EC = 3.5V (referenced to RTN), VSS unconnected 2EC Off-Leakage Current V2EC = 48V PG Sink Current VRTN = 1.5V, VPG = 0.8V, during inrush period PG Off-Leakage Current VPG = 48V 10 V VWAD falling, VRTN = 0V, VSS unconnected IWAD-LKG 9 1 125 1.5 230 3.5 FA 2.25 mA 1 FA 375 FA 1 FA THERMAL SHUTDOWN Thermal-Shutdown Threshold Thermal-Shutdown Hysteresis TSD TJ rising +140 NC TJ falling 28 NC _______________________________________________________________________________________ 3 MAX5969A/MAX5969B ELECTRICAL CHARACTERISTICS (continued) MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET ELECTRICAL CHARACTERISTICS (continued) (VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS, unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3) All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design. The input offset current is illustrated in Figure 1. Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1. Classification current is turned off whenever the device is in power mode. UVLO hysteresis is guaranteed by design, not production tested. A 20V glitch on input voltage that takes VDD below VON shorter than or equal to tOFF_DLY does not cause the MAX5969A/ MAX5969B to exit power-on mode. Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload condition across VDD and RTN. Note Note Note Note Note Note 3: 4: 5: 6: 7: 8: IIN dRi x 1V (VINi + 1 - VINi) = (IINi + 1 - IINi) (IINi + 1 - IINi) IOFFSET x IINi - VINi dRi IINi + 1 dRi IINi IOFFSET VINi 1V VINi + 1 VIN Figure 1. Effective Differential Input Resistance/Offset Current 4 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET SIGNATURE RESISTANCE vs. INPUT VOLTAGE TA = -40NC 25.0 TA = +25NC 24.5 0.1 TA = +85NC 24.0 0 0 2 4 6 2 4 6 8 VIN (V) CLASSIFICATION CURRENT vs. INPUT VOLTAGE CLASSIFICATION SETTLING TIME TA = +25NC -2 2 0 4 VIN 10V/div TA = -40NC 20 CLASS 2 IIN 0A 200mA/div VCLS 1V/div CLASS 1 10 CLASS 0 0 5 10 15 20 TA = +85NC 1.2 0.8 VSS UNCONNECTED V2EC REFERENCED TO RTN VWAD = 14V 0.4 0V RCLS = 30.9I 0 25 30 0 100µs/div 0 10 20 VIN (V) 50 60 150 100 130 110 90 MAX5969A toc09 900 800 CURRENT LIMIT (mA) TA = +85NC 150 MAX5969A toc08 MAX5969A toc07 TA = +25NC 250 IPG (µA) 40 NORMAL OPERATION CURRENT LIMIT vs. RTN VOLTAGE INRUSH CURRENT LIMIT vs. RTN VOLTAGE INRUSH CURRENT LIMIT (mA) 300 200 30 V2EC (V) PG SINK CURRENT vs. PG VOLTAGE TA = -40NC TA = +25NC 1.6 I2EC (mA) IIN (mA) CLASS 3 10 2.0 CLASS 4 30 8 2EC SINK CURRENT vs. 2EC VOLTAGE MAX5969A toc05 50 40 6 VIN (V) MAX5969A toc04 CLASS 5 60 TA = +85NC 0 10 VIN (V) 70 TA = -40NC -4 0 10 8 2 MAX5969A toc06 0.2 4 MAX5969A toc03 25.5 RSIGNATURE (kI) IIN (mA) 0.3 IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD INPUT OFFSET CURRENT (µA) IIN = IVDD + IDET RDET = 24.9kI RTN = 2EC = PG = WAD = VDD -40°C P TA P +85NC 0.4 26.0 MAX5969A toc01 0.5 INPUT OFFSET CURRENT vs. INPUT VOLTAGE MAX5969A toc02 DETECTION CURRENT vs. INPUT VOLTAGE 700 600 500 400 300 70 200 50 100 50 0 10 20 30 VPG (V) 40 50 60 0 10 20 30 VRTN (V) 40 50 60 0 10 20 30 40 50 60 VRTN(V) _______________________________________________________________________________________ 5 MAX5969A/MAX5969B Typical Operating Characteristics (VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.) MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Typical Operating Characteristics (continued) (VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.) INRUSH CONTROL WAVEFORM WITH TYPE 2 CLASSIFICATION ENTERING POWER MODE WITH TYPE 2 CLASSIFICATION MAX5969A toc10 USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI MAX5969A toc11 0V V2EC 50V/div USING TYPICAL APPLICATION CIRCUIT 2EC PULLED UP TO VDD WITH 10kI VRTN 50V/div 0V IRTN 100mA/div 200µs/div V2EC 0V 40V/div VRTN 0V 50V/div IRTN 0A 200mA/div 0A 0V VPG 0V 10V/div VDD 50V/div VDD 0V 50V/div 20ms/div 6 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET PIN NAME 1 VDD Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS. FUNCTION 2 DET 3 N.C. Detection Resistor Input. Connect a signature resistor (RDET = 24.9kI) from DET to VDD. No Connection. Not internally connected. 4 I.C. Internally Connected. Leave unconnected. 5 VSS Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power MOSFET. 6 RTN Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical Application Circuit. 7 WAD Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power source is not used. 8 PG Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC converter while turning on the hot-swap MOSFET switch until the hot-swap switch is fully on. PG current sink is disabled during detection, classification, and in the steady-state power mode. 9 2EC Active-Low 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE, the 2EC current sink is enabled and latched low after the isolation MOSFET is fully on until VIN drops below the UVLO threshold. 2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and RTN. 2EC is not latched if asserted by WAD. 10 CLS Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the desired classification current. See the classification current specifications in the Electrical Characteristics table to find the resistor value for a particular PD classification. –– EP Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS through a resistive path and must be connected to VSS externally. To optimize power dissipation, solder the exposed pad to a large copper power plane. _______________________________________________________________________________________ 7 MAX5969A/MAX5969B Pin Description MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Simplified Block Diagram VDD VDD EN 22.8/22 CLASSIFICATION CLS 1.23V VDD 2EC 5V D SET Q CLR Q D SET Q CLR Q PSE 2 5V REGULATOR 1.23V 1.5mA VDD 11.6V/4V 5V PG 46µA DET 11.6V/10.8V VON/VOFF VDD 230µA VDD THERMAL SHUTDOWN 95ms WAD WAPD R HSON S Q 4V 9V 15V VSS ISWITCH RTN ISOLATION SWITCH VON/VOFF = 38.6V/31V FOR MAX5969B VON/VOFF = 35.4V/31V FOR MAX5969A K x ISWITCH S IREF 1/K I0 135mA I1 760mA MAX5969A MAX5969B MUX 8 _______________________________________________________________________________________ IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET 2-EVENT CLASSIFICATION DETECTION GND VDD RJ-45 AND BRIDGE RECTIFIER 2EC RDET 24.9kI 68nF DET CLS SMAJ58A IN+ PG MAX5969A MAX5969B ENABLE DC-DC CONVERTER WAD 24V/48V BATTERY RCLS -54V GND VSS IN- RTN _______________________________________________________________________________________ 9 MAX5969A/MAX5969B Typical Operating Circuit MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Detailed Description Operating Modes Depending on the input voltage (VIN = VDD - VSS), the MAX5969A/MAX5969B operate in four different modes: PD detection, PD classification, mark event, and PD power. The devices enter PD detection mode when the input voltage is between 1.4V and 10.1V. The device enters PD classification mode when the input voltage is between 12.6V and 20V. The device enters PD power mode once the input voltage exceeds VON. Detection Mode (1.4V ≤ VIN ≤ 10.1V) In detection mode, the PSE applies two voltages on VIN in the range of 1.4V to 10.1V (1V step minimum) and then records the current measurements at the two points. The PSE then computes DV/DI to ensure the presence of the 24.9kω signature resistor. Connect the signature resistor (RDET) from VDD to DET for proper signature detection. The MAX5969A/MAX5969B pull DET low in detection mode. DET goes high impedance when the input voltage exceeds 12.5V. In detection mode, most of the MAX5969A/MAX5969B internal circuitry is off and the offset current is less than 10µA. If the voltage applied to the PD is reversed, install protection diodes at the input terminal to prevent internal damage to the MAX5969A/MAX5969B (see the Typical Application Circuit). Since the PSE uses a slope technique (DV/DI) to calculate the signature resistance, the DC offset due to the protection diodes is subtracted and does not affect the detection process. Classification Mode (12.6V ≤ VIN ≤ 20V) In the classification mode, the PSE classifies the PD based on the power consumption required by the PD. This allows the PSE to efficiently manage power distribution. Class 0 to 5 is defined as shown in Table 1. (The IEEE 802.3af/at standard defines only Class 0 to 4 and Class 5 for any special requirement.) An external resistor (RCLS) connected from CLS to VSS sets the classification current. The PSE determines the class of a PD by applying a voltage at the PD input and measuring the current sourced out of the PSE. When the PSE applies a voltage between 12.6V and 20V, the MAX5969A/MAX5969B exhibit a current characteristic with a value shown in Table 1. The PSE uses the classification current information to classify the power requirement of the PD. The classification current includes the current drawn by RCLS and the supply current of the MAX5969A/MAX5969B so the total current drawn by the PD is within the IEEE 802.3af/at standard figures. The classification current is turned off whenever the device is in power mode. 2-Event Classification and Detection During 2-event classification, a Type 2 PSE probes PD for classification twice. In the first classification event, the PSE presents an input voltage between 12.6V and 20.5V and the MAX5969A/MAX5969B present the programmed load ICLASS. The PSE then drops the probing voltage below the mark event threshold of 10.1V and the MAX5969A/MAX5969B present the mark current (IMARK). This sequence is repeated one more time. Table 1. Setting Classification Current IEEE 802.3at PSE CLASSIFICATION CURRENT SPECIFICATION (mA) MAXIMUM POWER USED BY PD (W) RCLS (I) 0 0.44 to 12.95 615 12.6 to 20 1 0.44 to 3.94 117 12.6 to 20 2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 21 3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31 4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45 5 > 25.5 21.3 12.6 to 20 54 64 — — CLASS VIN* (V) CLASS CURRENT SEEN AT VIN (mA) MIN MAX MIN 0 4 0 5 9 12 8 13 *VIN is measured across the MAX5969A/MAX5969B input VDD to VSS. 10 ������������������������������������������������������������������������������������� MAX IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Alternatively, the 2EC output also serves as a wall adapter detection output when the MAX5969A/MAX5969B are powered by an external wall power adapter. See the Wall Power Adapter Detection and Operation section for more information. Power Mode (Wake Mode) The MAX5969A/MAX5969B enter power mode when VIN rises above the undervoltage lockout threshold (VON). When VIN rises above VON, the MAX5969A/MAX5969B turn on the internal n-channel isolation MOSFET to connect VSS to RTN with inrush current limit internally set to 135mA (typ). The isolation MOSFET is fully turned on when the voltage at RTN is near VSS and the inrush current is reduced below the inrush limit. Once the isolation MOSFET is fully turned on, the MAX5969A/MAX5969B change the current limit to 800mA. The open-drain power-good output (PG) remains low for a minimum of tDELAY until the power MOSFET fully turns on to keep the downstream DC-DC converter disabled during inrush. Undervoltage Lockout The MAX5969A/MAX5969B operate up to a 60V supply voltage with a turn-on UVLO threshold (VON) at 35.4V/38.6V and a turn-off UVLO threshold (VOFF) at 31V. When the input voltage is above VON, the MAX5969A/ MAX5969B enter power mode and the internal MOSFET is turned on. When the input voltage goes below VOFF for more than tOFF_DLY, the MOSFET turns off. Power-Good Output An open-drain output (PG) is used to allow disabling downstream DC-DC converter until the n-channel isolation MOSFET is fully turned on. PG is pulled low to VSS for a period of tDELAY and until the internal isolation MOSFET is fully turned on. The PG is also pulled low when coming out of thermal shutdown. Thermal-Shutdown Protection The MAX5969A/MAX5969B include thermal protection from excessive heating. If the junction temperature exceeds the thermal-shutdown threshold of +140NC, the MAX5969A/MAX5969B turn off the internal power MOSFET and 2EC current sink. When the junction temperature falls below +112NC, the devices enter inrush mode and then return to power mode. Inrush mode ensures the downstream DC-DC converter is turned off as the internal power MOSFET is turned on. Wall Power Adapter Detection and Operation For applications where an auxiliary power source such as a wall power adapter is used to power the PD, the MAX5969A/MAX5969B feature wall power adapter detection. Once the input voltage (VDD - VSS) exceeds the mark event threshold, the MAX5969A/MAX5969B enable wall adapter detection. The wall power adapter is connected from WAD to RTN. The MAX5969A/ MAX5969B detect the wall power adapter when the voltage from WAD to RTN is greater than 9V. When a wall power adapter is detected, the internal n-channel isolation MOSFET turns off, 2EC current sink turns on, and classification current is disabled if VIN is in the classification range. ______________________________________________________________________________________ 11 MAX5969A/MAX5969B When the MAX5969A/MAX5969B are powered by a Type 2 PSE, the 2-event identification output 2EC asserts low after the internal isolation n-channel MOSFET is fully turned on. 2EC current sink is turned off when VDD goes below the UVLO threshold (VOFF) and turns on when VDD goes above the UVLO threshold (VON), unless VDD goes below VTHR to reset the latched output of the Type 2 PSE detection flag. MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Applications Information 2) Use large SMT component pads for power dissipating devices such as the MAX5969A/MAX5969B and the external diodes. Operation with 12V Adapter Layout Procedure Careful PCB layout is critical to achieve high efficiency and low EMI. Follow these layout guidelines for optimum performance: 3) Use short and wide traces for high-power paths. 4) Use the MAX5969 Evaluation Kit layout as a reference. 1) Place the input capacitor, classification resistor, and transient voltage suppressor as close as possible to the MAX5969A/MAX5969B. 2-EVENT CLASSIFICATION (ASSERTED ON) GND VDD RJ-45 AND BRIDGE RECTIFIER RDET 24.9kI 68nF IN+ GND PG DET MAX5969A MAX5969B ENABLE DC-DC CONVERTER WAD CLS SMAJ58A 12V BATTERY RCLS -54V 2EC VSS IN- RTN THIS CIRCUIT ACHIEVES PROPER 2EC LOGIC WHEN BATTERY IS < 12.5V Figure 2. Typical Configuration When Using a 12V Wall Power Adapter 12 ������������������������������������������������������������������������������������� IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET ISOLATED 2-EVENT CLASSIFICATION OUTPUT GND GND 2EC VDD PG PG VAC 24.9kI DET 68nF CLS SMAJ58A VAC WAD MAX5969A MAX5969B 24/48V BATTERY 43.7I VSS -54V GND 33kI 1.37MI RTN RTN 249I 51.5kI 4.7µF 0.1µF ISOLATED +5.3V/2A GND RTN PG ULVO/EN IN UFLG 0.1µF 0.1µF 22µF VCC VCC ISOLATED RTN FB 10kI CS COMP MAX15000 22.1I NDRV GND CS CS RT 1kI 18.1kI 649I 619I 330pF 8.2nF 0.75I 8.06kI 0.1µF 4.99kI VCC 4.99kI 1kI RTN 100pF 33nF 8.06kI 1kI 2.49kI 2.2nF RTN ISOLATED RTN ______________________________________________________________________________________ 13 MAX5969A/MAX5969B Typical Application Circuit MAX5969A/MAX5969B IEEE 802.3af/at-Compliant, Powered Device Interface Controllers with Integrated Power MOSFET Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 TDFN-EP T1033+1 21-0137 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 © 2009 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.