TI TPS2379DDAR

TPS2379
www.ti.com
SLVSB98 – MARCH 2012
IEEE 802.3at PoE High-Power PD Interface with External Gate Driver
Check for Samples: TPS2379
FEATURES
APPLICATIONS
•
•
•
1
2
•
•
•
•
•
•
•
IEEE 802.3at Type-2 Hardware Classification
with Status Flag
Auxiliary Gate Driver for High-power
Expansion
Robust 100 V, 0.5 Ω Hotswap MOSFET
1A (typ.) Operating Current Limit
140 mA (typ.) Inrush Current Limit
DC/DC Converter Enable
15 kV/8 kV System-level ESD Capability
PowerPad™ SO-8 Package
IEEE 802.3at-compliant Devices
Universal Power Over Ethernet (UPOE)
Compliant Devices
Video and VoIP Telephones
Multiband Access Points
Security Cameras
Pico-Base Stations
•
•
•
•
DESCRIPTION
This 8-pin integrated circuit contains all of the features needed to implement an IEEE802.3at type-2 powered
device (PD). The low 0.5 Ω internal switch resistance, combined with the enhanced thermal dissipation of the
PowerPad™ package, enables this controller to continuously handle up to 0.85 A. The TPS2379 supports
higher-power applications through the use of an external pass transistor. It also features a 100 V internal pass
transistor, 140 mA inrush current, type-2 indication, auto-retry fault protection, and an open-drain power-good
output.
1
8
GATE
DEN
2
7
T2P
CLS
3
6
CDB
VSS
4
5
RTN
From Spare
Pairs or
Transformers
From Ethernet
Transformers
VDD
D1
RDEN
TPS2379
RT2P
VDD
C1
DEN
CLS
T2P
CDB
VSS
GATE
RTN
RCLS
RBLST
VC
SS
CBULK
DC/DC Converter
SO-8 PowerPad
Q1
Figure 1. Typical Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPad, PowerPAD are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TPS2379
SLVSB98 – MARCH 2012
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCT INFORMATION (1)
DEVICE
TPS2379
(1)
TA
PACKAGE
MARKING
–40°C to 85°C
DDA
(SO-8 PowerPAD™)
2379
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
ABSOLUTE MAXIMUM RATINGS (1)
over recommended TJ range; voltages with respect to VVSS (unless otherwise noted)
VALUE
Input voltage
MAX
VDD, DEN
–0.3
100
RTN (2)
–0.6
100
(3)
CLS
–0.3
6.5
GATE (3)
–0.3
18
[CDB, T2P] to RTN
–0.3
100
RTN
Sinking current
UNIT
MIN
(4)
V
Internally limited
CDB, T2P
5
DEN
1
Sourcing current CLS
65
mA
2
kV
Human body model
ESD
Charged device model
System level (contact/air) (5)
(1)
(2)
(3)
(4)
(5)
500
V
15
kV
8
TJMAX
mA
Internally limited
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
With I(RTN) = 0
Do not apply voltages to these pins
SOA limited to RTN = 80 V at 1.2 A.
Discharges applied to circuit of Figure 1 between RJ-45, adapter, and output voltage rails per EN61000-4-2, 1999.
THERMAL INFORMATION
TPS2379
THERMAL METRIC
(1)
SO-8 PowerPad™
UNITS
8 PINS
θJA
Junction-to-ambient thermal resistance
45.9
θJCtop
Junction-to-case (top) thermal resistance
51.9
θJB
Junction-to-board thermal resistance
28.8
ψJT
Junction-to-top characterization parameter
8.9
ψJB
Junction-to-board characterization parameter
28.7
θJCbot
Junction-to-case (bottom) thermal resistance
6.7
°C/W
spacer
(1)
2
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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spacer
RECOMMENDED OPERATING CONDITIONS
Voltages with respect to VSS (unless otherwise noted)
MIN
Input voltage range
Sinking current
57
T2P or CDB to RTN
0
57
RTN
0.85
CDB, T2P
2
UNIT
V
A
mA
Ω
60
Junction temperature
(1)
MAX
0
CLS (1)
Resistance
NOM
RTN, VDD
–40
125
°C
Voltage should not be externally applied to this pin.
ELECTRICAL CHARACTERISTICS
40 V ≤ VVDD ≤ 57 V, RDEN = 24.9 kΩ, CDB, CLS, GATE, T2P open; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins.
Typical values are at 25°C. All voltages are with respect to VVSS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VDD = 1.4 V
53.8
56.5
58.3
µA
VDD = 10.1 V, Not in mark
DETECTION (DEN)
Measure ISUPPLY(VDD, RTN, DEN)
Detection current
VPD_DIS
395
410
417
Bias current
DEN open, VVDD = 10.1 V, Measure ISUPPLY, Not in mark
3
4.8
12
Disable threshold
DEN falling
3
3.7
5
50
113
200
1.8
2.17
2.6
RCLS = 243 Ω
9.9
10.6
11.2
RCLS = 137 Ω
17.6
18.6
19.4
RCLS = 90.9 Ω
26.5
27.9
29.3
Hysteresis
µA
V
mV
CLASSIFICATION (CLS)
13 V ≤ VDD ≤ 21 V, Measure IVDD + IDEN + IRTN
RCLS = 1270 Ω
ICLS
Classification current
RCLS = 63.4 Ω
VCL_ON
VDD rising, VCLS ↑
Class lower threshold
VCL_H
VCU_ON
VCU_H
VMSR
Class upper threshold
Hysteresis
38
39.9
42.0
11.9
12.5
13.0
1.4
1.6
1.7
VDD rising, VCLS↓
21
22
23
Hysteresis
0.5
0.78
0.9
mA
V
V
Mark reset threshold
VVDD falling
3
3.9
5
Mark state resistance
2-point measurement at 5 V and 10.1 V
6
10
12
kΩ
Leakage current
VDD = 57 V, VCLS = 0 V, measure ICLS
1
µA
12
V
µA
GATE (Auxiliary Gate Output)
Output high voltage
Sourcing current
Sinking current
8
10
VGATE = 0 V
25
38
60
VGATE = 4 V, VDD = 48→ 25 V
0.6
1.25
1.75
5
23.2
30
150
365
600
0.2
0.42
0.75
Ω
30
µA
VDD = 25 V, VGATE = 0→ 4 V
Current limit delay
mA
µs
PASS DEVICE (RTN)
rDS(ON)
On resistance
Input bias current
VDD = VRTN = 30 V, measure IRTN
Current limit
VRTN =1.5 V
0.85
1
1.2
A
Inrush current limit
VRTN = 2 V, VDD: 20 V → 48 V
100
140
180
mA
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ELECTRICAL CHARACTERISTICS (continued)
40 V ≤ VVDD ≤ 57 V, RDEN = 24.9 kΩ, CDB, CLS, GATE, T2P open; –40°C ≤ TJ ≤ 125°C. Positive currents are into pins.
Typical values are at 25°C. All voltages are with respect to VVSS (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Inrush termination
Percentage of inrush current
Foldback threshold
VRTN rising
Foldback deglitch time
VRTN rising to when current limit changes to inrush current
limit
MIN
TYP
MAX
80%
90%
99%
UNIT
11
12.3
13.6
V
500
800
1500
µs
0.27
0.50
V
CONVERTER DISABLE (CDB)
Output low voltage
ICDB = 2 mA, VRTN = 2 V, VDD: 20 V → 48 V
Minimum voltage, V(VDD
–RTN), for CDB to be valid
VCDB = VDD, ICDB = 1 mA, in inrush
Leakage current
VCDB = 57 V, VRTN = 0 V
3
V
10
µA
0.60
V
10
µA
TYPE 2 PSE INDICATION (T2P)
VT2P
Output low voltage
IT2P = 2 mA, after 2-event classification and inrush is
complete, VRTN = 0 V
Leakage current
VT2P = 57 V, VRTN = 0 V
UVLO rising threshold
VVDD rising
36.3
38.1
40.0
UVLO falling threshold
VVDD falling
30.5
32.0
33.6
0.26
UVLO
VUVLO_R
VUVLO_H
UVLO hysteresis
6.1
V
V
THERMAL SHUTDOWN
TJ↑
Shutdown
135
Hysteresis
145
°C
20
VDD BIAS CURRENT
40 V ≤ VVDD ≤ 57 V
Operating current
Mark
Reset
Idle
Detect
Detect
Mark
285
Class
Between
Ranges
Class
Between
Ranges
Class
Between
Ranges
500
µA
UVLO
Falling
UVLO
Rising
Operating
T2P
open-drain
TYPE 1 PSE
Hardware Class
PoE Startup Sequence
Mark
Class
Between
Ranges
UVLO
Rising
Operating
T2P low
TYPE 2 PSE
Hardware Class
UVLO
Falling
Figure 2. PD Class State Diagram
4
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TPS2379
GATE 8
VDD
PowerPAD™
1
2
DE N
3
CLS
4
VSS
T2P
7
CDB
6
RTN
5
PIN FUNCTIONS
NAME
NO.
I/O
VDD
1
I
DEN
2
I/O
Connect 24.9 kΩ to VDD for detection. Pull to VSS disable pass MOSFET.
CLS
3
O
Connect resistor from CLS to VSS to program classification current.
VSS
4
RTN
5
O
Drain of PoE pass MOSFET.
CDB
6
O
Open-drain converter disable output, active low, referenced to RTN.
T2P
7
O
Active low indicates type 2 PSE connected.
GATE
8
O
Auxiliary gate driver output.
Connect to negative power rail derived from PoE source.
Pad
The PowerPad™ must be connected to VSS. A large fill area is required to assist in heat dissipation.
12V &
10V
VDD
DESCRIPTION
Connect to positive PoE input power rail. Bypass with 0.1 µF to VSS.
1
Detection
Comp.
Class
Comp.
4V
Class
Comp.
VSS
22V &
21.25V
5V & 4V
Mark
Comp.
2.5V
REG.
800ms
800ms
12V
UVLO Comp Output
R
OTSD
VSS
T2P
RTN
6
CDB
R
6V
S
UVLO
Comp.
CLS
Type 2
State Eng.
1 = inrush
0 = current limit
Inrush latch
38.1V &
32V
3
7
Mark Comp Output
Q
DEN
VSS
RTN
S
2
Inrush limit
threshold 1
Q
RTN
1
Current limit
0
threshold
8
GATE
5
RTN
GATE DRIVER
0
High if over
temperauture
I RTN sense
4
Signals referenced to VSS unless otherwise noted
Hotswap
MOSFET
365ms
IRTN sense,1 if < 90% of inrush current limit
Figure 3. Functional Block Diagram
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DETAILED PIN DESCRIPTIONS
The following descriptions refer to the schematic of Figure 1 or Figure 4 and the functional block diagram.
CDB (Converter Disble Bar): This active low output is pulled to RTN when the device is in inrush current limiting,
going open when inrush period has completed once the GATE output has become higher than 6 V. This ensures
that the external pass transistor is enhanced before the load is enabled. It remains in a high impedance state at
all other times. This pin is an open-drain output, and it may require a pullup resistor or other interface to the
downstream load. CDB may be left open if it is not used.
CLS: An external resistor (RCLS in Figure 1) connected between the CLS pin and VSS provides a classification
signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor
whenever the voltage differential between VDD and VSS lies between about 10.9 V and 22 V. The current drawn
by this resistor, combined with the internal current drain of the controller and any leakage through the internal
pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of
the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, plus the power
supplied to the downstream load, should not exceed the maximum power indicated in Table 1.
High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle.
Table 1. Class Resistor Selection
CLASS
MINIMUM POWER
AT PD (W)
MAXIMUM POWER
AT PD (W)
RESISTOR
RCLS (Ω)
0
0.44
12.95
1270
1
0.44
3.84
243
2
3.84
6.49
137
3
6.49
12.95
90.9
4
12.95
25.5
63.4
DEN (Detection and Enable): This pin implements two separate functions. A resistor (RDEN in Figure 1)
connected between VDD and DEN generates a detection signature whenever the voltage differential between VDD
and VSS lies between approximately 1.4 and 10.9V. Beyond this range, the controller disconnects this resistor to
save power. For applications that wish to comply with the requirements of IEEE802.3at, the external resistance
should equal 24.9 kΩ.
If the resistance connected between VDD and DEN is divided into two roughly equal portions, then the application
circuit can disable the PD by grounding the tap point between the two resistances. This action simultaneously
spoils the detection signature and thereby signals the PSE that the PD no longer requires power.
GATE (Auxiliary Gate Driver): This pin allows the connection of an external pass MOSFET in parallel with the
internal pass transistor. The GATE pin enables the external transistor after inrush has completed. Current is
divided between the external MOSFET and the internal transistor as a function of their respective resistances.
The addition of a balancing resistor (RBLST in Figure 1) in series with RTN and the external MOSFET can ensure
desired distribution of the two currents. Whenever the RTN current exceeds the current limit threshold, the GATE
pin will pull low after a 365 µs delay. The GATE pin is pulled low in thermal shutdown. After the controller cools
down, and the inrush cycle is complete, the GATE pin rises again.
RTN: This pin provides the negative power return path for the load. Once VDD exceeds the UVLO threshold, the
internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from exceeding about 140 mA
until the bulk capacitance (CBULK in Figure 1) is fully charged. Inrush ends when the RTN current drops below
about 125 mA. The RTN current is subsequently limited to about 1 A. CDB pulls low to signal the downstream
load that the bulk capacitance is fully charged. If RTN ever exceeds about 12 V for longer than 800 µs, then the
TPS2379 returns to inrush limiting.
T2P (Type-2 PSE Indicator): The controller pulls this pin to RTN whenever type-2 hardware classification has
been observed. The T2P output will return to a high-impedance state if the part enters thermal shutdown, the
pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected. The circuitry that watches for type-2
hardware classification latches its result when the VDD-to-VSS voltage differential rises above the upper
classification threshold. This circuit resets when the VDD-to-VSS voltage differential drops below the mark
threshold. The T2P pin can be left unconnected if it is not used.
6
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VDD: This pin connects to the positive side of the input supply. It provides operating power to the PD controller
and allows monitoring of the input line voltage.
VSS: This is the input supply negative rail that serves as a local ground. The PowerPad™ must be connected to
this pin to ensure proper operation.
PowerPAD
The PowerPad is internally connected to VSS. It should be tied to a large VSS copper area on the PCB to provide
a low resistance thermal path to the circuit board. It is recommended that a clearance of 0.025” be maintained
between VSS and high-voltage signals such as VDD.
TYPICAL CHARACTERISTICS
7
50
6
40
TA = 25°C
Resistance (kΩ)
IVDD (µA)
5
TA = 125°C
4
3
2
Detection Resistance
30
20
10
1
TA = −40°C
0
0
1
2
3
4
5
6
V(VDD−VSS) (V)
7
8
9
0
10
1
2
3
4
5
6
7
8
9
10
V(VDD−VSS) (V)
Figure 4. Detection Bias Current vs PoE Voltage
G002
Figure 5. Detection Resistance vs PoE Voltage
13
22.5
Class Upper Threshold, On
12.5
22
V(VDD−VSS) (V)
V(VDD−VSS) (V)
0
G001
21.5
Class Lower Threshold, On
12
11.5
Class Lower Threshold, Off
Class Upper Threshold, Off
11
21
−50
−25
0
25
50
75
Junction Temperature (°C)
100
10.5
−50
125
−25
G003
Figure 6. Classification Upper Threshold vs Temperature
0
25
50
75
Junction Temperature (°C)
100
125
G004
Figure 7. Classification Lower Threshold vs Temperature
400
4.5
360
Mark Reset Threshold
TA = 25°C
V(VDD−VSS) (V)
IVDD (µA)
320
TA = 125°C
280
240
200
4
3.5
TA = −40°C
160
120
20
25
30
35
40
45
50
55
V(VDD−VSS) (V)
60
3
−50
G009
Figure 8. IVDD Bias Current vs Voltage
−25
0
25
50
75
Junction Temperature (°C)
100
125
G006
Figure 9. Mark Reset Threshold vs Temperature
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TYPICAL CHARACTERISTICS (continued)
0.7
10
Pass FET Resistance (Ω)
Mark Resistance (kΩ)
9.8
9.5
9.2
9
8.8
8.5
−50
−25
0
25
50
75
Junction Temperature (°C)
100
0.6
0.5
0.4
0.3
0.2
−50
125
Figure 10. Mark Resistance vs Temperature
0
25
50
75
Junction Temperature (°C)
100
125
G008
Figure 11. Pass FET Resistance vs Temperature
160
89
Inrush Current Termination (%)
Current Inrush Limit (mA)
−25
G007
150
140
130
120
−50
−25
0
25
50
75
Junction Temperature (°C)
100
88
87
86
85
−50
125
−25
G009
Figure 12. PoE Inrush Current Limit vs Temperature
0
25
50
75
Junction Temperature (°C)
100
125
G010
Figure 13. Inrush Termination Threshold vs Temperature
38.3
1.02
1.01
V(VDD−VSS) (V)
Current Limit (A)
38.28
1
38.26
UVLO Rising Threshold
38.24
38.22
0.99
−50
−25
0
25
50
75
Junction Temperature (°C)
100
38.2
−50
G011
Figure 14. PoE Current Limit vs Temperature
8
125
−25
0
25
50
75
Junction Temperature (°C)
100
125
G012
Figure 15. UVLO Rising Threshold vs Temperature
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TYPICAL CHARACTERISTICS (continued)
32.16
10
32.14
V(GATE−VSS) (V)
V(VDD−VSS) (V)
9.9
32.12
UVLO Falling Threshold
32.1
32.08
Auxilary Gate Voltage
9.8
9.7
32.06
32.04
−50
−25
0
25
50
75
Junction Temperature (°C)
100
125
9.6
−50
G013
Figure 16. UVLO Falling Threshold vs Temperature
−25
0
25
50
75
Junction Temperature (°C)
100
125
G015
Figure 17. Auxiliary Gate Voltage vs Temperature
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DETAILED DESCRIPTION
PoE OVERVIEW
The following text is intended as an aid in understanding the operation of the TPS2379 but not as a substitute for
the IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE),
adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.32008 is referred to as a type 1 device, and devices with high power and enhanced classification will be referred
to as type 2 devices. Standards change and should always be referenced when making design decisions.
The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable by power
sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an
idle state and three operational states of detection, classification, and operation. The PSE leaves the cable
unpowered (idle state) while it periodically looks to see if something has been plugged in; this is referred to as
detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a
valid PD signature is present, the PSE may inquire how much power the PD requires; this is referred to as
classification. The PSE may then power the PD if it has adequate capacity.
Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an
enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL)
classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may
return the default, 13W current-encoded class, or one of four other choices. DLL classification occurs after
power-on and the Ethernet data link has been established.
Once started, the PD must present a maintain power signature (MPS) to assure the PSE that it is still present.
The PSE monitors its output for a valid MPS, and turns the port off if it loses the MPS. Loss of the MPS returns
the PSE to the idle state. Figure 18 shows the operational states as a function of PD input voltage. The upper
half is for IEEE 802.3-2008, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in
the lower half indicate these are the same (e.g., Detect and Class) for both.
Shutdown
Classify
Detect
6.9
Maximum Input
Voltage
Must Turn On byVoltage Rising
Lower Limit Operating Range
Must Turn Off by Voltage Falling
Classification
Upper Limit
Classification
Lower Limit
Detection
Upper Limit
Detection
Lower Limit
IEEE 802-2008
spacer
Normal Operation
42.5
0
30
37
57 PI Voltage (V)
42
Normal Operation
250ms
Transient
Class-Mark
Transition
Mark
20.5
Lower Limit 13W Op.
10.1 14.5
T2 Reset
Range
IEEE 802.3at
2.7
Figure 18. Threshold Voltages
10
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The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input
requirements differ from PSE output requirements to account for voltage drops and operating margin. The
standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation.
IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA568) that may have had AWG 26 conductors. IEEE 802.3at type 2 cabling power loss allotments and voltage
drops have been adjusted for 12.5 Ω power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568,
typically AWG #24 conductors). Table 2 shows key operational limits broken out for the two revisions of the
standard.
Table 2. Comparison of Operational Limits
STANDARD
POWER LOOP
RESISTANCE
(max)
PSE OUTPUT
POWER
(min)
PSE STATIC
OUTPUT VOLTAGE
(min)
PD INPUT
POWER
(max)
20Ω
15.4W
44V
12.95W
37V – 57V
N/A
12.5Ω
30W
50V
25.5W
37V – 57V
42.5V – 57V
IEEE802.3at-2008
802.3at (Type 1)
802.3at (Type 2)
STATIC PD INPUT VOLTAGE
Power ≤12.95W Power >12.95W
The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT),
or between the two spare pairs (4 - 5 and 7 - 8). Power application to the same pin combinations in 1000baseT
systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare
pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges
to accept power from any of the possible PSE configurations. The voltage drops associated with the input
bridges create a difference between the standard limits at the PI and the TPS2379 specifications.
A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements
include the following:
1. Must interpret type 2 hardware classification,
2. Must present hardware class 4,
3. Must implement DLL negotiation,
4. Must behave like a type 1 PD during inrush and startup,
5. Must not draw more than 13W for 80ms after the PSE applies operating voltage (power-up),
6. Must not draw more than 13W if it has not received a type 2 hardware classification or received permission
through DLL,
7. Must meet various operating and transient templates, and
8. Optionally monitor for the presence or absence of an adapter (assume high power).
As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for
changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the
adapter should be individually monitored, typically with an optocoupler.
Threshold Voltages
The TPS2379 has a number of internal comparators with hysteresis for stable switching between the various
states. Figure 19 relates the parameters in the Electrical Characteristics section to the PoE states. The mode
labeled Idle between Classification and Operation implies that the DEN, CLS, and RTN pins are all high
impedance. The state labeled Mark, which is drawn in dashed lines, is part of the new type 2 hardware class
state machine.
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Idle
Classification
Type 1
Mark
Type 2
Functional
State
PD Powered
VDD-VSS
Detection
VCL_H
VMSR
VCL_ON
VCU_H
VUVLO_H
VCU_OFF
VUVLO_R
Note: Variable names refer to Electrical Characteristic Table parameters
Figure 19. Threshold Voltages
PoE Startup Sequence
Current: 100 mA/div
The waveforms of Figure 20 demonstrate detection, classification, and startup from a PSE with type 2 hardware
classification. The key waveforms shown are V(VDD-VSS), V(RTN-VSS), and IPI. IEEE 802.3at requires a
minimum of two detection levels, two class and mark cycles, and startup from the second mark event. VRTN to
VSS falls as the TPS2379 charges CBULK following application of full voltage. In Figure 20, deassertion of the CDB
signal is delayed and used to enable load current as seen in the IPI waveform.
Load enabled using
CDB plus delay
Inrush
IPI
Voltage: 10 V/div
VVDD-VSS
Class
Mark
Detect
VRTN-VSS
Time : 50 ms/div
Figure 20. Startup
Detection
The TPS2379 pulls DEN to VSS whenever V(VDD-VSS) is below the lower classification threshold. When the input
voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in detection,
RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 kΩ (±1%), presents the
correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A valid PD
detection signature is an incremental resistance ( ΔV/ΔI ) between 23.75 kΩ and 26.25 kΩ at the PI.
The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the
parallel combination of RDEN and internal VDD loading. The input diode bridge’s incremental resistance may be
hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is
partially compensated by the TPS2379's effective resistance during detection.
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The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage
into the detection range during the classification sequence. The PD is required to have an incorrect detection
signature in this condition, which is referred to as a mark event (see Figure 20). After the first mark event, the
TPS2379 will present a signature less than 12 kΩ until it has experienced a V(VDD-VSS) voltage below the mark
reset threshold (VMSR). This is explained more fully under Hardware Classification.
Hardware Classification
Hardware classification allows a PSE to determine a PD’s power requirements before powering, and helps with
power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to
determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in
hardware to indicate that it is a high-power device. A type 1 PSE will treat a class 4 device like a class 0 device,
allotting 13 W if it chooses to power the PD. A PD that receives a 2-event class understands that it is powered
from a high-power PSE and it may draw up to 25.5 W immediately after the 80 ms startup period completes. A
type 2 PD that does not receive a 2-event hardware classification may choose to not start, or must start in a 13
W condition and request more power through the DLL after startup. The standard requires a type 2 PD to
indicate that it is underpowered if this occurs. Startup of a high-power PD under 13 W implicitly requires some
form of powering down sections of the application circuits.
The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a
PD if it draws more than its stated Class power, which may be the hardware class or a lower DLL-derived power
level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above
the Table 1 limit, however the average power requirement always applies.
The TPS2379 implements two-event classification. Selecting an RCLS of 63.4 Ω provides a valid type 2
signature. TPS2379 may be used as a compatible type 1 device simply by programming class 0–3 per Table 1.
DLL communication is implemented by the Ethernet communication system in the PD and is not implemented by
the TPS2379.
The TPS2379 disables classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned
off during PD thermal limiting or when DEN is active. The CLS output is inherently current limited, but should not
be shorted to VSS for long periods of time.
Figure 21 shows how classification works for the TPS2379. Transition from state-to-state occurs when
comparator thresholds are crossed (see Figure 18 and Figure 19). These comparators have hysteresis, which
adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with
increasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom,
ending up with a latched type 2 decode along the lower branch that is highlighted. This state results in a low T2P
during normal operation. Once the valid path to type 2 PSE detection is broken, the input voltage must transition
below the mark reset threshold to start anew.
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Idle
Detect
Mark
Reset
Mark
Class
Between
Ranges
Class
Between
Ranges
Class
Between
Ranges
UVLO
Falling
UVLO
Rising
Operating
T2P
open-drain
TYPE 1 PSE
Hardware Class
PoE Startup Sequence
Mark
Class
Between
Ranges
UVLO
Rising
Operating
T2P low
TYPE 2 PSE
Hardware Class
UVLO
Falling
Figure 21. Two-Event Class Internal States
Inrush and Startup
IEEE 802.3at has a startup current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type
2 PSE limits output current to between 400 mA and 450 mA for up to 75 ms after power-up (applying “48 V” to
the PI) in order to mirror type 1 PSE functionality. The type 2 PSE will support higher output current after 75 ms.
The TPS2379 implements a 140 mA inrush current, which is compatible with all PSE types. A high-power PD
must limit its converter startup peak current. The operational current cannot exceed 400 mA for a period of 80 ms
or longer. This requirement implicitly requires some form of powering down sections of the application circuits.
Maintain Power Signature
The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating
voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at
least 75 ms every 325 ms) and an ac impedance lower than 26.3 kΩ in parallel with 0.05 μF. The ac impedance
is usually accomplished by the minimum operating CBULK requirement of 5 μF. When DEN is used to force the
hotswap switch off, the dc MPS will not be met. A PSE that monitors the dc MPS will remove power from the PD
when this occurs. A PSE that monitors only the ac MPS may remove power from the PD.
Startup and Operation
The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides
full voltage to the PD. This prevents the downstream converter circuits from loading the PoE input during
detection and classification. The converter circuits will discharge CBULK while the PD is unpowered. Thus V(VDDRTN) will be a small voltage just after full voltage is applied to the PD, as seen in Figure 20. The PSE drives the PI
voltage to the operating range once it has decided to power up the PD. When VVDD rises above the UVLO turnon threshold (VUVLO-R, ~38 V) with RTN high, the TPS2379 enables the hotswap MOSFET with a ~140 mA
(inrush) current limit as seen in Figure 22. The CDB pin is active while CBULK charges and VRTN falls from VVDD to
nearly VVSS. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches
to the operational level (~1000 mA) and CDB is deasserted to allow downstream converter circuitry to start. The
TPS2379 asserts GATE after inrush is complete to enable an external pass MOSFET if used. In Figure 22, T2P
is active because a type 2 PSE is plugged in.
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50V/div
VVDD-RTN
10V/div
V(GATE -VSS)
Type 1 PSE
50V/div
VT2P-RTN
10V/div
VCDB-RTN
PI powered
Type 2 PSE
Load enabled using
CDB plus delay
Inrush
100mA/div
IPI
Time: 5ms/div
Figure 22. Power Up and Start
PD Hotswap Operation
IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current
versus time template with specified minimum and maximum sourcing boundaries. The peak output current may
be as high as 50 A for 10 μs or 1.75 A for 75 ms. This makes robust protection of the PD device even more
important than it was in IEEE 802.3-2008.
The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and
deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with VRTNVVSS rising as a result. GATE is pulled down about 300 μs after RTN current reaches the current limit level. If
VRTN rises above ~12 V for longer than ~800 μs, the current limit reverts to the inrush value. The 800 μs deglitch
feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of
the hotswap and PSE protection. Figure 23 shows an example of the RTN current profile during VDD to RTN
short circuit when only the internal hotswap MOSFET is used. The hotswap MOSFET goes into current limit,
causing the RTN voltage to increase. Once VRTN exceeds 12V, IRTN which was clamped to the current limit drops
to the level of inrush current limit after 800µs.
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VRTN-VSS > 12V
VRTN-VSS
20V/div
VCDB-VSS
20V/div
VGATE -VSS
5V/div
Inrush
500mA/div
I PI
Time: 200us/div
Figure 23. Response to PD Output Short Circuit Without AUX MOSFET
Figure 24 shows an example of the RTN current profile during VDD to RTN short circuit when the external
MOSFET is used. The circuit is depicted in Figure 1. The current will divide between the internal and external
MOSFETs. During the short circuit, the hotswap MOSFET goes into current limit, causing the RTN voltage to
increase. When the internal MOSFET exceeds current limit for ~300µs, GATE will de-assert and shut off the
auxiliary MOSFET. VRTN will rise quickly and the internal MOSFET will go into current limit for ~800µs (after
VRTN > ~12V) and then IRTN which was clamped to the current limit drops into the inrush current limit.
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V RTN-VSS
20V/div
V RTN-VSS > 12V
V GATE-VSS
5V/div
Inrush
500mA/div
5A/div
IINT
IEXT
Current limit
5A/div
I PI
Time: 200us/div
Figure 24. Response to PD Output Short Circuit with AUX MOSFET
The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or
operation into a VDD -to-RTN short cause high power dissipation in the MOSFET. An over-temperature shutdown
(OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The
hotswap MOSFET will be re-enabled with the inrush current limit when exiting from an over-temperature event.
Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off.
The hotswap switch will be forced off under the following conditions:
1. V(DEN –VSS) < VPD_DIS when VVDD – VVSS is in the operational range,
2. PD is over-temperature, or
3. V(DEN – VSS) PoE UVLO falling threshold (~32 V).
CDB and T2P
CDB (converter disable) is an active-low pin that indicates when the internal hotswap MOSFET is inrush limiting.
CDB de-asserts when inrush is over and can be used to enable a downstream converter to start up. Common
interfaces to the converter controller include the soft start or enable pins.
T2P (type 2 PSE) is an active-low multifunction pin that indicates if (PSE = Type_2) and (PD current limit ≠
Inrush).
The usage of T2P is demonstrated in Figure 27. When PSE applies and PD observes a type 2 hardware
classification, T2P pin is pulled to RTN as a indication of the type of PSE.
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Auxiliary Pass MOSFET Control
The TPS2379 can be used in non-standard applications requiring power significantly above the IEEE802.3at,
type 2 levels. This implementation can be achieved by utilizing all four Ethernet wire pairs and boosting the
TPS2379 hotswap MOSFET operating current limit. Boosting the TPS2379 operating current limit is achieved by
adding an external pass MOSFET to share the total load current with the internal hotswap MOSFET. The
external pass MOSFET is enabled by the GATE pin after the internal hotswap MOSFET inrush is complete. The
GATE pin will de-assert if the TPS2379 internal current limit is exceeded in excess of 300 µs.
A comprehensive high power POE design example is discussed in application report Implementing a 60-W, Endto-End PoE System (literature number SLVA498).
Using DEN to Disable PoE
The DEN pin may be used to turn the PoE hotswap switch off by pulling it to VSS while in the operational state,
or to prevent detection when in the idle state. A low voltage on DEN forces the hotswap MOSFET off during
normal operation.
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APPLICATION INFORMATION
INPUT BRIDGES AND SCHOTTKY DIODES
Using Schottky diodes instead of PN junction diodes for the PoE input bridges will reduce the power dissipation
in these devices by about 30%. There are, however, some things to consider when using them.
The IEEE standard specifies a maximum backfeed voltage of 2.8 V. A 100 kΩ resistor is placed between the
unpowered pairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse
leakage current than PN diodes, making this a harder requirement to meet. To compensate, use conservative
design for diode operating temperature, select lower-leakage devices where possible, and match leakage and
temperatures by using packaged bridges.
Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Setting
reasonable expectations for the temperature range over which the detection signature is accurate is the simplest
solution. Increasing RDEN slightly may also help meet the requirement.
Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. After
exposure to ESD, Schottky diodes may become shorted or leak. Care must be taken to provide adequate
protection in line with the exposure levels. This protection may be as simple as ferrite beads and capacitors.
As a general recommendation, use 1 A or 2 A, 100 V rated discrete or bridge diodes for the input rectifiers.
Protection, D1
A TVS, D1, across the rectified PoE voltage per Figure 1 must be used. A SMAJ58A, or equivalent, is
recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient
voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require additional
protection.
Capacitor, C1
The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 μF to 0.12 μF.
Typically a 0.1 μF, 100 V, 10% ceramic capacitor is used.
Detection Resistor, RDEN
The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.75 kΩ and 26.25 kΩ, or
25 kΩ ± 5%. A resistor of 24.9 kΩ ± 1% is recommended for RDEN.
Classification Resistor, RCLS
Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at
standard. The class power assigned should correspond to the maximum average power drawn by the PD during
operation. Select RCLS according to Table 1. For a high power design, choose class 4 and RCLS = 63.4 Ω.
CDB Pin Interface
The CDB pin can be used to inhibit downstream converter start up by keeping the soft start pin low. Figure 25
shows an example where CDB connects to the SS pin of a UCC3809 DC/DC controller. Since CDB is an opendrain output, it will not affect the soft start capacitor charge time when it de-asserts. Another common use of the
CDB pin is to enable a converter with an active-high enable input. In this case, CDB may require a pullup resistor
to either VDD, or to a bias supply, depending on the requirements of the controller enable pin.
TPS2379
UCC3809
SS
CDB
CSS
RTN
GND
Figure 25. CDB Interface
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GATE Pin Interface
A non-standard PoE system can be designed to meet extended power requirements and retain the PoE benefits
such as protection of non – PoE devices and fault tolerance. Such a solution will not comply with IEEE802.3at
and should be designed and operated as stand-alone system. The TPS2379 GATE pin is used to control an
external pass MOSFET as shown in Figure 26. When inrush is complete, GATE sources 38µA to enable Q1, the
external pass MOSFET. When Q1 is fully enhanced, CDB de-asserts and enables the load. Delaying the deassertion of CDB until Q1 becomes fully enhanced prevents nuisance over-current faults that could occur with
heavy startup loads. A resistor from GATE to VSS is not required to ensure that Q1 turns off; but, if a resistor
from GATE to VSS is used, choose a value large enough so that the GATE sourcing current can fully enhance
Q1.
VC
VDD
R T2P
T2P
CDB
I2379
SS
GATE
VSS
C BULK
IL
RTN
DC/DC Converter
TPS2379
Q1
Q2
RBLST
Figure 26. GATE Interface
EXTERNAL BOOST CIRCUIT (Q1, Q2, and RBLST) CONSIDERATIONS
As discussed above, the IEEE802.3at template bounds the peak PSE output current between 50A for 10 μs and
1.75 A for 75 ms for a two-pair system. In a non-standard, four-pair system these current levels can be assumed
to double. During an overload event, the TPS2379 will limit current to ~1A and the rest of the current will flow
through Q1 and RBLST. Ignoring the ballast resistor and parasitic impedances the current through Q1 could be as
high as 99A.
Actual system level behavior will be influenced by the circuit parasitic impedances, diode bridge impedance,
contact resistances, external MOSFET resistance, and input voltage droop during the overload event. The
impedances act to reduce the peak current as well as drop the voltage across Q1 during the overload event. The
designer must evaluate the overload performance of their system and ensure that the selected external MOSFET
safe operating area (SOA) is not violated during the output overload. The duration of the overload can be
terminated if the input voltage droop to the TPS2379 goes below the UVLO falling threshold (32V typical). When
UVLO occurs, the internal MOSFET is disabled, GATE goes low, and the external MOSFET is disabled. This
shortened overload duration is beneficial when evaluating the external MOSFET SOA performance.
Additional limiting and control of the external output overload current can be achieved by using the ballast
resistor, RBLST. RBLST is used to help balance the internal and external MOSFET load currents, and to implement
external current limiting through the use of Q2. The load current, IL divides between the external Q1 and the
internal pass MOSFET of the TPS2379 as shown in Equation 1.
RBLST + R Q1
I2 379 = IL ´
RBLST + RQ1 + R 2379
(1)
RQ1 is the ON resistance of Q1 and R2379 is the ON resistance of the TPS2379. Q2 can be used to force Q1 to
limit its current when the voltage across RBLST exceeds VBEON of Q2. Further discussion of these details, as well
as additional considerations involving PD classification, are discussed in the application report Implementing a 60
W end-to-end PoE system (literature number SLVA498).
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T2P Pin Interface
IT2P
VC
RT2P
IT2 P-OUT
The T2P pin is an active-low, open-drain output which indicates that a high power source is available. An
optocoupler can interface the T2P pin to circuitry on the secondary side of the converter. A high-gain optocoupler
and a high-impedance (e.g., CMOS) receiver are recommended. Design of the T2P optocoupler interface can be
accomplished as follows:
VOUT
R T2P-OUT
VT2P -OUT
VT2P Low
Indicates
Type 2
T2P From
TPS2379
Figure 27. T2P Interface
1. As shown in Figure 27, let VC = 12 V, VOUT = 5 V, RT2P-OUT = 10 kΩ, VT2P = 260 mV, VT2P-OUT = 400 mV.
spacer
IT2P -OUT =
VOUT - VT2P -OUT 5 - 0.4
=
= 0.46mA
RT2P -OUT
10000
(2)
2. The optocoupler current transfer ratio, CTR, will be needed to determine RT2P. A device with a minimum CTR
of 100% at 1 mA LED bias current, IT2P, is selected. Note that in practice, CTR will vary with temperature,
LED bias current and aging. These variations may require some iteration using the CTR-versus- IDIODE curve
on the optocoupler data sheet.
(a) The approximate forward voltage of the optocoupler diode, VFWLED, is 1.1 V from the data sheet.
(b)
IT2P-OUT 0.46mA
=
= 0.46mA, Select IT2P = 1mA
CTR
1.00
V - VT2P - VFWLED 12 V - 0.26 V - 1.1 V
= C
=
= 10.6kΩ
IT2P
1mA
IT2P-MIN =
RT2P
MM
.
(c) Select
a 10.7 kΩ resistor.
THERMAL CONSIDERATIONS AND OTSD
Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations
assume that the TPS2379 is the only heat source contributing to the PCB temperature rise. It is possible for a
normally operating TPS2379 device to experience an OTSD event if it is excessively heated by a nearby device.
ESD
ESD requirements for a unit that incorporates the TPS2379 have a much broader scope and operational
implications than are used in TI’s testing. Unit-level requirements should not be confused with reference design
testing that only validates the ruggedness of the TPS2379.
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LAYOUT
Printed circuit board layout recommendations are provided in the evaluation module (EVM) documentation
available for this device.
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PACKAGE OPTION ADDENDUM
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19-Apr-2012
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS2379DDA
ACTIVE
SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
TPS2379DDAR
ACTIVE
SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAGLevel-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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