ELPIDA EDD2516ARTA-6B

DATA SHEET
256M bits DDR SDRAM
EDD2516ARTA-6B (16M words × 16 bits)
Specifications
Pin Configurations
• Density: 256M bits
• Organization
 4M words × 16 bits × 4 banks
• Package: 66-pin plastic TSOP (II)
• Power supply: VDD, VDDQ = 2.5V ± 0.2V
• Data rate: 333Mbps (max.)
• Four internal banks for concurrent operation
• Interface: SSTL_2
• Burst lengths (BL): 2, 4, 8
• Burst type (BT):
 Sequential (2, 4, 8)
 Interleave (2, 4, 8)
• /CAS Latency (CL): 2, 2.5
• Precharge: auto precharge operation for each burst
access
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
 Average refresh period: 7.8µs
• Operating ambient temperature range
 TA = 0°C to +70°C
/xxx indicates active low signal.
Features
• Double-data-rate architecture; two data transfers per
clock cycle
• The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
• Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
• Data inputs, outputs, and DM are synchronized with
DQS
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
• Data mask (DM) for write data
66-pin Plastic TSOP(II)
VDD
DQ0
VDDQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VSSQ
DQ7
NC
VDDQ
LDQS
NC
VDD
NC
LDM
/WE
/CAS
/RAS
/CS
NC
BA0
BA1
A10(AP)
A0
A1
A2
A3
VDD
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
NC
VREF
VSS
UDM
/CK
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
(Top view)
A0 to A12
BA0, BA1
DQ0 to DQ15
UDQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address input
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0848E10 (Ver. 1.0)
Date Published December 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005
EDD2516ARTA-6B
Ordering Information
Part number
Mask
version
Organization
(words × bits)
EDD2516ARTA-6B
R
16M × 16
Internal
banks
Data rate
Mbps (max.)
Speed bin
(CL-tRCD-tRP)
333
DDR-333B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 25 16 A R TA - 6B
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
25: 256M / 4-bank
Speed
6B: DDR333B (2.5-3-3)
Organization
16: x16
Package
TA: TSOP (II)
Die Rev.
Power Supply, Interface
A: 2.5V, SSTL_2
Data Sheet E0848E10 (Ver. 1.0)
2
EDD2516ARTA-6B
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................11
Pin Function.................................................................................................................................................12
Command Operation ...................................................................................................................................14
Simplified State Diagram .............................................................................................................................21
Operation of the DDR SDRAM ....................................................................................................................22
Timing Waveforms.......................................................................................................................................24
Package Drawing ........................................................................................................................................30
Recommended Soldering Conditions..........................................................................................................31
Data Sheet E0848E10 (Ver. 1.0)
3
EDD2516ARTA-6B
Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Voltage on input pin relative to VSS
VI
–0.5 to VDD +0.5
V
Voltage on DQ and DQS pin relative to VSS
VIO
–0.5 to VDDQ +0.5
V
Supply voltage relative to VSS
VDD
–0.5 to +3.7
V
Supply voltage for output relative to VSS
VDDQ
–0.5 to +3.7
V
Short circuit output current
IOS
50
mA
Power dissipation
PD
1.0
W
Operating temperature
TA
0 to +70
°C
Storage temperature
Tstg
–55 to +125
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0°C to 70°C)
Parameter
Symbol
Supply voltage
VDD,
VDDQ
VSS,
VSSQ
min.
typ.
max.
Unit
Notes
2.3
2.5
2.7
V
1
0
0
0
V
0.49 × VDDQ
0.50 × VDDQ
0.51 × VDDQ
V
Input reference voltage
VREF
Termination voltage
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high voltage
VIH (DC)
VREF + 0.15
—
VDDQ + 0.3
V
Input low voltage
VIL (DC)
–0.3
—
VREF – 0.15
V
VIN (DC)
–0.3
—
VDDQ + 0.3
V
VIX (DC)
0.5 × VDDQ − 0.2V
0.5 × VDDQ
0.5 × VDDQ + 0.2V V
VID (DC)
0.36
—
VDDQ + 0.6
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
Notes: 1.
2.
3.
4.
V
2
3, 4
VDDQ must be lower than or equal to VDD.
VIN (DC) specifies the allowable DC execution of each differential input.
VID (DC) specifies the input differential voltage required for switching.
VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement.
Data Sheet E0848E10 (Ver. 1.0)
4
EDD2516ARTA-6B
AC Overshoot/Undershoot Specification
Parameter
Specification
Maximum peak amplitude allowed for overshoot
1.6V
Maximum peak amplitude allowed for undershoot
1.6V
The area between the overshoot signal and VDD must be less than or equal to
4.5V-ns
The area between the undershoot signal and GND must be less than or equal to
4.5V-ns
Maximum amplitude = 1.6V
Overshoot area
4.5V-ns (max.)
5
4
3
2
Volts (V) 1
0
−1
−2
−3
VDD
Ground
Undershoot area
4.5V-ns (max.)
0
1
2
3
4
Time (ns)
Data Sheet E0848E10 (Ver. 1.0)
5
5
6
EDD2516ARTA-6B
DC Characteristics 1 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Symbol
Grade
max.
Unit
Operating current (ACT-PRE)
IDD0
85
mA
Operating current
(ACT-READ-PRE)
IDD1
125
mA
Idle power down standby current
IDD2P
6
mA
Floating idle standby current
IDD2F
35
mA
Quiet idle standby current
IDD2Q
35
mA
Active power down standby current
IDD3P
25
mA
Active standby current
IDD3N
45
mA
IDD4R
250
mA
IDD4W
200
mA
Auto Refresh current
IDD5
145
mA
Self refresh current
IDD6
3
mA
Operating current
(4 banks interleaving)
IDD7A
330
mA
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Test condition
CKE ≥ VIH,
tRC = tRC (min.)
CKE ≥ VIH, BL = 4,
CL = 2.5,
tRC = tRC (min.)
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
CKE ≥ VIH, /CS ≥ VIH
DQ, DQS, DM = VREF
CKE ≤ VIL
CKE ≥ VIH, /CS ≥ VIH
tRAS = tRAS (max.)
CKE ≥ VIH, BL = 2,
CL = 2.5
CKE ≥ VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input ≤ VIL or ≥ VIH
Input ≥ VDD – 0.2 V
Input ≤ 0.2 V
BL = 4
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
1, 5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at ≥ VIH or ≤ VIL.
DC Characteristics 2 (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Symbol
min.
max.
Unit
Test condition
Input leakage current
ILI
–2
2
µA
VDD ≥ VIN ≥ VSS
Output leakage current
ILO
–5
5
µA
VDDQ ≥ VOUT ≥ VSS
Output high current
IOH
–16.2
—
mA
VOUT = 1.95V
Output low current
IOL
16.2
—
mA
VOUT = 0.35V
Data Sheet E0848E10 (Ver. 1.0)
6
Notes
EDD2516ARTA-6B
Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V)
Parameter
Symbol
Pins
min.
typ.
max.
Unit
Notes
Input capacitance
CI1
CK, /CK
2.0
—
3.0
pF
1
CI2
All other input pins
2.0
—
3.0
pF
1
Cdi1
CK, /CK
—
—
0.25
pF
1
Cdi2
All other input-only pins
—
—
0.5
pF
1
Data input/output capacitance
CI/O
DQ, DM, DQS
4.0
—
5
pF
1, 2,
Delta input/output capacitance
Cdio
DQ, DM, DQS
—
—
0.5
pF
1
Delta input capacitance
Notes: 1. These parameters are measured on conditions:
TA = +25°C.
2. DOUT circuits are disabled.
f = 100MHz, VOUT = VDDQ/2, ∆VOUT = 0.2V,
AC Characteristics (TA = 0°C to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
-6B
Parameter
Symbol
min.
max.
Unit
Notes
Clock cycle time
(CL = 2)
tCK
7.5
12
ns
10
(CL = 2.5)
tCK
6
12
ns
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
CK half period
tHP
min (tCH, tCL)
—
tCK
DQ output access time from
CK, /CK
tAC
–0.7
0.7
ns
2, 11
DQS output access time from CK, /CK
tDQSCK
–0.6
0.6
ns
2, 11
DQS to DQ skew
tDQSQ
—
0.45
ns
3
DQ/DQS output hold time from DQS
tQH
tHP – tQHS
—
ns
Data hold skew factor
tQHS
—
1
ns
Data-out high-impedance time from CK, /CK
tHZ
–0.7
0.7
ns
5, 11
Data-out low-impedance time from CK, /CK
tLZ
–0.7
0.7
ns
6, 11
Read preamble
tRPRE
0.9
1.1
tCK
Read postamble
tRPST
0.3
0.7
tCK
DQ and DM input setup time
tDS
0.50
—
ns
8
DQ and DM input hold time
tDH
0.50
—
ns
8
7
DQ and DM input pulse width
tDIPW
1.75
—
ns
Write preamble setup time
tWPRES
0
—
ns
Write preamble
tWPRE
0.25
—
tCK
Write postamble
tWPST
0.4
0.6
tCK
Write command to first DQS latching
transition
tDQSS
0.75
1.25
tCK
DQS falling edge to CK setup time
tDSS
0.2
—
tCK
DQS falling edge hold time from CK
tDSH
0.2
—
tCK
DQS input high pulse width
tDQSH
0.35
—
tCK
DQS input low pulse width
tDQSL
0.35
—
tCK
Address and control input setup time
tIS
0.75
—
ns
8
Address and control input hold time
tIH
0.75
—
ns
8
Address and control input pulse width
tIPW
2.2
—
ns
7
Data Sheet E0848E10 (Ver. 1.0)
7
9
EDD2516ARTA-6B
-6B
Parameter
Symbol
min.
max.
Unit
Mode register set command cycle time
tMRD
2
—
tCK
Active to Precharge command period
tRAS
42
120000
ns
60
—
ns
72
—
ns
18
—
ns
Active to Active/Auto refresh command
tRC
period
Auto refresh to Active/Auto refresh command
tRFC
period
Active to Read/Write delay
tRCD
Precharge to active command period
tRP
18
—
ns
Active to Autoprecharge delay
tRAP
tRCD min.
—
ns
Active to active command period
tRRD
12
—
ns
Write recovery time
tWR
15
—
ns
Auto precharge write recovery and precharge
tDAL
time
(tWR/tCK) + (tRP/tCK) —
tCK
Internal write to Read command delay
tWTR
1
—
tCK
Average periodic refresh interval
tREF
—
7.8
µs
Notes
13
Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter
definitions, see ‘Timing Waveforms’ section.
2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal
transition is defined to occur when the signal level crossing VTT.
3. The timing reference level is VTT.
4. Output valid window is defined to be the period between two successive transition of data out or DQS
(read) signals. The signal transition is defined to occur when the signal level crossing VTT.
5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The
timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage
level, but specify when the device output stops driving.
6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This
parameter is not referred to a specific DOUT voltage level, but specify when the device output begins
driving.
7. Input valid windows is defined to be the period between two successive transition of data input or DQS
(write) signals. The signal transition is defined to occur when the signal level crossing VREF.
8. The timing reference level is VREF.
9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific
reference voltage to judge this transition is not given.
10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not
assured.
11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these
values are 10% of tCK.
12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than
0.4V/400 cycle.
13. tDAL = (tWR/tCK)+(tRP/tCK)
For each of the terms above, if not already an integer, round to the next highest integer.
Example: For –6B Speed at CL = 2.5, tCK = 6ns, tWR = 15ns and tRP= 18ns,
tDAL = (15ns/6ns) + (18ns/6ns) = (3) + (3)
tDAL = 6 clocks
Data Sheet E0848E10 (Ver. 1.0)
8
EDD2516ARTA-6B
Test Conditions
Parameter
Symbol
Value
Unit
Input reference voltage
VREF
VDDQ/2
V
Termination voltage
VTT
VREF
V
Input high voltage
VIH (AC)
VREF + 0.80
V
Input low voltage
VIL (AC)
VREF − 0.80
V
VID (AC)
1.6
V
VIX (AC)
VREF
V
SLEW
1
V/ns
Input differential voltage, CK and /CK
inputs
Input differential cross point voltage,
CK and /CK inputs
Input signal slew rate
tCK
VDD
CK VID
VREF
/CK
VSS
tCL
tCH
VIX
VDD
VIH
VIL
VREF
VSS
∆t
SLEW = (VIH (AC) – VIL (AC))/∆t
VTT
Measurement point
RT = 50Ω
DQ
CL = 30pF
Input Waveforms and Output Load
Data Sheet E0848E10 (Ver. 1.0)
9
EDD2516ARTA-6B
Timing Parameter Measured in Clock Cycle
Number of clock cycle
tCK
6ns
Parameter
Symbol
min.
max.
Unit
Write to pre-charge command delay (same bank)
tWPD
4 + BL/2
—
tCK
Read to pre-charge command delay (same bank)
tRPD
BL/2
—
tCK
Write to read command delay (to input all data)
tWRD
2 + BL/2
—
tCK
Burst stop command to write command delay
(CL = 2)
tBSTW
2
—
tCK
(CL = 2.5)
tBSTW
3
—
tCK
Burst stop command to DQ High-Z
(CL = 2)
tBSTZ
2
2
tCK
(CL = 2.5)
tBSTZ
2.5
2.5
tCK
Read command to write command delay
(to output all data)
(CL = 2)
tRWD
2 + BL/2
—
tCK
(CL = 2.5)
tRWD
3 + BL/2
—
tCK
Pre-charge command to High-Z
(CL = 2)
tHZP
2
2
tCK
(CL = 2.5)
tHZP
2.5
2.5
tCK
Write command to data in latency
tWCD
1
1
tCK
Write recovery
tWR
3
—
tCK
DM to data in latency
tDMD
0
0
tCK
Mode register set command cycle time
tMRD
2
—
tCK
Self refresh exit to non-read command
tSNR
12
—
tCK
Self refresh exit to read command
tSRD
200
—
tCK
Power down entry
tPDEN
1
1
tCK
Power down exit to command input
tPDEX
1
—
tCK
Data Sheet E0848E10 (Ver. 1.0)
10
EDD2516ARTA-6B
Clock
generator
Block Diagram
Bank 3
Bank 2
Bank 1
A0 to A12, BA0, BA1
Mode
register
Row
address
buffer
and
refresh
counter
Row decoder
CK
/CK
CKE
Memory cell array
Bank 0
Control logic
/CS
/RAS
/CAS
/WE
Command decoder
Sense amp.
Column decoder
Column
address
buffer
and
burst
counter
Data control circuit
Latch circuit
DLL
CK, /CK
Input & Output buffer
DQ
Data Sheet E0848E10 (Ver. 1.0)
11
DQS
DM
EDD2516ARTA-6B
Pin Function
CK, /CK (input pins)
The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point
of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point
of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the
VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock
input to this pin. The other input signals are referred at CK rising edge.
/CS (input pin)
When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal
operations (bank active, burst operations, etc.) are held.
/RAS, /CAS, and /WE (input pins)
These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels.
See "Command operation".
A0 to A12 (input pins)
Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the
/CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0
to the A8 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This
column address becomes the starting address of a burst operation.
[Address Pins Table]
Address (A0 to A12)
Part number
Row address
Column address
EDD2516ARTA
AX0 to AX12
AY0 to AY8
A10 (AP) (input pin)
A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If
A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge
command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write
command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled.
BA0 and BA1 (input pins)
BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See
Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Data Sheet E0848E10 (Ver. 1.0)
12
EDD2516ARTA-6B
CKE (input pin)
This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is
Low. CKE controls power down and self-refresh. The power down and the self-refresh commands are entered
when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or
write access.
The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge
and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper
hold time tIH.
UDM, LDM (input pin)
DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and
VREF. DMs provide the byte mask function. In × 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data. When DM = High, the data input at the same timing are
masked while the internal burst counter will be count up. LDM controls the lower byte (DQ0 to DQ7) and UDM
controls the upper byte (DQ8 to DQ15) of write data.
DQ0 to DQ15 (input/output pins)
Data is input to and output from these pins.
UDQS, LDQS (input and output pin): DQS provide the read data strobes (as output) and the write data strobes
(as input). In ×16 products, LDQS is the lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8
to DQ15) data strobe signal.
VDD, VSS, VDDQ, VSSQ (Power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
Data Sheet E0848E10 (Ver. 1.0)
13
EDD2516ARTA-6B
Command Operation
Command Truth Table
DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other
combinations than those in the table below are illegal.
CKE
Command
Symbol
n–1
n
/CS
/RAS /CAS /WE
BA1
BA0
AP
Address
Ignore command
DESL
H
H
H
×
×
×
×
×
×
×
No operation
NOP
H
H
L
H
H
H
×
×
×
×
Burst stop in read command
BST
H
H
L
H
H
L
×
×
×
×
Column address and read command
READ
H
H
L
H
L
H
V
V
L
V
Read with auto-precharge
READA
H
H
L
H
L
H
V
V
H
V
Column address and write command
WRIT
H
H
L
H
L
L
V
V
L
V
Write with auto-precharge
WRITA
H
H
L
H
L
L
V
V
H
V
Row address strobe and bank active
ACT
H
H
L
L
H
H
V
V
V
V
Precharge select bank
PRE
H
H
L
L
H
L
V
V
L
×
Precharge all bank
PALL
H
H
L
L
H
L
×
×
H
×
Refresh
REF
H
H
L
L
L
H
×
×
×
×
SELF
H
L
L
L
L
H
×
×
×
×
MRS
H
H
L
L
L
L
L
L
L
V
EMRS
H
H
L
L
L
L
L
H
L
V
Mode register set
Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input
Note: The CKE level must be kept for 1 CK cycle at least.
Ignore command [DESL]
When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal
status is held.
No operation [NOP]
As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data
input are neglected and internal status is held.
Burst stop in read operation [BST]
This command stops a burst read operation, which is not applicable for a burst write operation.
Column address strobe and read command [READ]
This command starts a read operation. The start address of the burst read is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation,
the output buffer becomes High-Z.
Read with auto-precharge [READA]
This command starts a read operation. After completion of the read operation, precharge is automatically executed.
Column address strobe and write command [WRIT]
This command starts a write operation. The start address of the burst write is determined by the column address
(See “Address Pins Table” in Pin Function) and the bank select address.
Write with auto-precharge [WRITA]
This command starts a write operation. After completion of the write operation, precharge is automatically executed.
Data Sheet E0848E10 (Ver. 1.0)
14
EDD2516ARTA-6B
Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
BA0
BA1
Bank 0
L
L
Bank 1
H
L
Bank 2
L
H
Bank 3
H
H
Remark: H: VIH. L: VIL.
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode
register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
CKE
Current state
Command
n–1
n
/CS
/RAS
/CAS
/WE
Address
Notes
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
2
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
2
Idle
Power down entry (PDEN)
H
L
L
H
H
H
×
H
L
H
×
×
×
×
Self refresh
Self refresh exit (SELFX)
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Power down
Power down exit (PDEX)
Remark: H: VIH. L: VIL. ×: VIH or VIL.
Notes: 1. All the banks must be in IDLE before executing this command.
2. The CKE level must be kept for 1 CK cycle at least.
Data Sheet E0848E10 (Ver. 1.0)
15
EDD2516ARTA-6B
Function Truth Table
The following tables show the operations that are performed when each command is issued in each state of the
DDR SDRAM.
Current state
Precharging*
1
/CS
/RAS /CAS
/WE
Address
Command
Operation
Next state
H
×
×
×
×
DESL
NOP
ldle
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL*
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
ILLEGAL*
11
—
11
—
L
Idle*
2
Activating*
4
Active*
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
L
H
L
BA, A10
PRE, PALL
NOP
ldle
L
L
L
×
×
ILLEGAL
—
ldle
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
H
H
L
×
BST
ldle
ILLEGAL*
11
—
—
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
11
L
L
H
H
BA, RA
ACT
Activating
L
L
H
L
BA, A10
PRE, PALL
NOP
ldle
ldle/
Self refresh
Active
L
L
L
H
×
REF, SELF
Refresh/
12
Self refresh*
L
L
L
L
MODE
MRS
Mode register set*
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
ldle
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
×
×
ILLEGAL
—
12
ldle
ldle
L
L
×
×
×
ILLEGAL
—
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL*
11
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
11
—
ILLEGAL*
11
—
—
—
L
5
H
—
L
L
Refresh
3
(auto-refresh)*
ldle
11
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11
L
L
L
×
×
ILLEGAL
—
—
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
Active
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation Read/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
Write
Starting write operation recovering/
precharging
L
L
H
H
BA, RA
ACT
ILLEGAL*
L
L
H
L
BA, A10
PRE, PALL
Pre-charge
Idle
L
L
L
×
×
ILLEGAL
—
Data Sheet E0848E10 (Ver. 1.0)
16
11
—
EDD2516ARTA-6B
Current state
Read*
6
/CS
/RAS /CAS
/WE
Address
Command
Operation
Next state
H
×
×
×
×
DESL
NOP
Active
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
BST
Active
L
H
L
H
BA, CA, A10
READ/READA
Interrupting burst read
operation to
start new read
Active
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
13
—
L
L
H
H
BA, RA
ACT
ILLEGAL*
11
—
L
L
H
L
BA, A10
PRE, PALL
Interrupting burst
read operation to
start pre-charge
Precharging
ILLEGAL
—
NOP
Precharging
L
L
L
×
×
Read with auto-preH
7
charge*
×
×
×
×
DESL
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
—
—
Write*
8
Write recovering*
9
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
—
ILLEGAL*
11, 14
—
L
L
H
L
BA, A10
PRE, PALL
L
L
L
×
×
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
ILLEGAL
ILLEGAL
—
Write
recovering
Write
recovering
—
Interrupting burst write
operation to
start read operation.
Interrupting burst write
operation to
start new write
operation.
L
H
L
H
BA, CA, A10
READ/READA
L
H
L
L
BA, CA, A10
WRIT/WRITA
L
L
H
H
BA, RA
ACT
ILLEGAL*
PRE, PALL
Interrupting write
operation to start precharge.
Idle
ILLEGAL
—
NOP
Active
11
Read/ReadA
Write/WriteA
—
L
L
H
L
BA, A10
L
L
L
×
×
H
×
×
×
×
DESL
L
H
H
H
×
NOP
NOP
Active
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
Starting read operation. Read/ReadA
L
H
L
L
BA, CA, A10
WRIT/WRITA
Starting new write
operation.
L
L
H
H
BA, RA
L
L
H
L
BA, A10
L
L
L
×
×
ACT
PRE/PALL
ILLEGAL*
11
ILLEGAL*
11
ILLEGAL
Data Sheet E0848E10 (Ver. 1.0)
17
Write/WriteA
—
—
—
EDD2516ARTA-6B
Current state
/CS
/RAS
/CAS
/WE
Address
Command
Operation
Next state
Write with auto10
pre-charge*
H
×
×
×
×
DESL
NOP
Precharging
L
H
H
H
×
NOP
NOP
Precharging
L
H
H
L
×
BST
ILLEGAL
—
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL*
14
—
—
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL*
14
L
L
H
H
BA, RA
ACT
ILLEGAL*
11, 14
—
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*
11, 14
—
L
L
L
×
×
ILLEGAL
—
H: VIH. L: VIL. ×: VIH or VIL
The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued.
The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued.
The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued.
The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued.
The DDR SDRAM is in "Active" state after "Activating" is completed.
The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned
off.
7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been
output and DQ output circuits are turned off.
8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input.
9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input.
10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input.
11. This command may be issued for other banks, depending on the state of the banks.
12. All banks must be in "IDLE".
13. Before executing a write command to stop the preceding burst read operation, BST command must be
issued.
14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or
a write with auto-precharge enabled, may be followed by any column command to other banks, as long as
that command does not interrupt the read or write data transfer, and all other related limitations apply.
(E.g. Conflict between READ data and WRITE data must be avoided.)
Remark:
Notes: 1.
2.
3.
4.
5.
6.
The minimum delay from a read or write command with auto precharge enabled, to a command to a
different bank, is summarized below.
From command
To command (different bank, noninterrupting command)
Read w/AP
Write w/AP
Minimum delay
(Concurrent AP supported)
Units
Read or Read w/AP
BL/2
tCK
Write or Write w/AP
CL(rounded up)+ (BL/2)
tCK
Precharge or Activate
1
tCK
Read or Read w/AP
1 + (BL/2) + tWTR
tCK
Write or Write w/AP
BL/2
tCK
Precharge or Activate
1
tCK
Data Sheet E0848E10 (Ver. 1.0)
18
EDD2516ARTA-6B
Command Truth Table for CKE
Current State
CKE
n–1 n
Self refresh
Self refresh recovery
Power down
All banks idle
Row active
/CS
/RAS /CAS /WE Address
Operation
H
×
×
×
×
×
×
INVALID, CK (n-1) would exit self refresh
L
H
H
×
×
×
×
Self refresh recovery
L
H
L
H
H
×
×
Self refresh recovery
L
H
L
H
L
×
×
ILLEGAL
L
H
L
L
×
×
×
ILLEGAL
L
L
×
×
×
×
×
Maintain self refresh
H
H
H
×
×
×
×
Idle after tRC
H
H
L
H
H
×
×
Idle after tRC
H
H
L
H
L
×
×
ILLEGAL
H
H
L
L
×
×
×
ILLEGAL
H
L
H
×
×
×
×
ILLEGAL
H
L
L
H
H
×
×
ILLEGAL
H
L
L
H
L
×
×
ILLEGAL
H
L
L
L
×
×
×
ILLEGAL
EXIT power down → Idle
H
×
×
×
×
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
×
Notes
INVALID, CK (n – 1) would exit power down
L
L
×
×
×
×
H
H
H
×
×
×
Refer to operations in Function Truth Table
H
H
L
H
×
×
Refer to operations in Function Truth Table
H
H
L
L
H
×
H
H
L
L
L
H
×
H
H
L
L
L
L
OPCODE Refer to operations in Function Truth Table
H
L
H
×
×
×
Refer to operations in Function Truth Table
H
L
L
H
×
×
Refer to operations in Function Truth Table
H
L
L
L
H
×
Refer to operations in Function Truth Table
H
L
L
L
L
H
×
H
L
L
L
L
L
OPCODE Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Power down
H
×
×
×
×
×
×
Refer to operations in Function Truth Table
L
×
×
×
×
×
×
Power down
Maintain power down mode
Refer to operations in Function Truth Table
CBR (auto) refresh
Self refresh
1
1
1
Remark: H: VIH. L: VIL. ×: VIH or VIL
Note: 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
Data Sheet E0848E10 (Ver. 1.0)
19
EDD2516ARTA-6B
Auto-refresh command [REF]
This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined
by the internal refresh controller. The average refresh cycle is 7.8 µs. The output buffer becomes High-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can
be issued tRFC after the last auto-refresh command.
Self-refresh entry [SELF]
This command starts self-refresh. The self-refresh operation continues as long as CKE is held Low. During the selfrefresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A self-refresh is
terminated by a self-refresh exit command.
Power down mode entry [PDEN]
tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In
power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode
continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not
disable DLL.
Self-refresh exit [SELFX]
This command is executed to exit from self-refresh mode. To issue non-read commands, tSNR has to be satisfied.
((tSNR =)10 cycles for tCK = 7.5 ns or 12 cycles for tCK = 6.0 ns after [SELFX]) To issue read command, tSRD has
to be satisfied to adjust DOUT timing by DLL. (200 cycles after [SELFX]) After the exit, input auto-refresh command
within 7.8 µs.
Power down exit [PDEX]
The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued.
Data Sheet E0848E10 (Ver. 1.0)
20
EDD2516ARTA-6B
Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
POWER
DOWN
CKE_
CKE
ROW
ACTIVE
BST
WRITE
Write
READ
WRITE
WITH
AP
WRITE
READ
WITH
AP
READ
READ
READ
WITH AP
WRITE
WITH AP
Read
READ
WITH AP
PRECHARGE
WRITEA
READA
PRECHARGE
POWER
APPLIED
POWER
ON
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically
and enter the IDLE state.
Data Sheet E0848E10 (Ver. 1.0)
21
EDD2516ARTA-6B
Operation of the DDR SDRAM
Power-up Sequence
The following sequence is recommended for Power-up.
(1) Apply power and attempt to maintain CKE at an LVCMOS low state (all other inputs may be undefined).
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
clock input is required to lock the DLL after every DLL reset).
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
the DLL.
(4)
(5)
PALL
EMRS
(6)
(7)
MRS
PALL
(8)
(9)
CK
/CK
Command
2 cycles (min.)
REF
REF
tRP
2 cycles (min.) 2 cycles (min.)
REF
tRFC
tRFC
2 cycles (min.)
Disable DLL reset with A8 = Low
DLL reset with A8 = High
DLL enable
Any
command
MRS
200 cycles (min)
Power-up Sequence after CKE Goes High
Mode Register and Extended Mode Register Set
There are two mode registers, the mode register and the extended mode register so as to define the operating
mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command
[MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are
set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine
which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode
register must be set.
Remind that no other parameters shown in the table bellow are allowed to input to the registers.
BA0
BA1
A12
0
0
0
A11 A10 A9
0
0
0
A8
A7
DR
0
A6
A5
A4
LMODE
A3
A2
A1
BT
A0
BL
MRS
A8 DLL Reset A6 A5 A4 CAS Latency
2
0 1 0
0 No
1 Yes
1
1
0
2.5
A3 Burst Type
0 Sequential
1 Interleave
Mode Register Set [MRS] (BA0 = 0, BA1 = 0)
Data Sheet E0848E10 (Ver. 1.0)
22
A2 A1 A0
Burst Length
0
0
0
1
BT=0 BT=1
2
2
1
4
4
0
0
1
1
8
8
EDD2516ARTA-6B
BA0 BA1
1
A12 A11 A10 A9
0
0
0
0
0
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
DLL
EMRS
A0 DLL Control
0 DLL Enable
1 DLL Disable
Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0)
Burst Operation
The burst type (BT) and the first three bits of the column address determine the order of a data out.
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequence
Interleave
Starting Ad. Addressing(decimal)
A1
A0
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Sequence
Interleave
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
0
0
A0 Sequence
0
0, 1, 2, 3, 4, 5, 6, 7,
Interleave
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
Data Sheet E0848E10 (Ver. 1.0)
23
;;;;;;
EDD2516ARTA-6B
Timing Waveforms
Command and Addresses Input Timing Definition
CK
/CK
tIS
Command
(/RAS, /CAS,
/WE, /CS)
tIH
VREF
tIS
tIH
VREF
Address
Read Timing Definition
tCK
/CK
CK
tCL
tCH
tDQSCK
tDQSCK
tDQSCK
tDQSCK tRPST
tRPRE
DQS
tDQSQ
tLZ
DQ
(Dout)
tAC
tDQSQ
tQH
tAC
tAC
tQH
tHZ
tDQSQ
tDQSQ tQH
tQH
Write Timing Definition
tCK
/CK
CK
tDQSS
DQS
tDSH
tDSS
tDSS
VREF
tWPRES
tDQSL
tWPRE
DQ
(Din)
tWPST
VREF
tDS
DM
tDQSH
tDIPW
tDH
VREF
tDS
tDH
tDIPW
Data Sheet E0848E10 (Ver. 1.0)
24
tDIPW
EDD2516ARTA-6B
Read Cycle
tCK
tCH tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRCD
tRP
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
BA
A10
tIS tIH
Address
DM
DQS
DQ (output)
tRPRE
High-Z
tRPST
High-Z
Bank 0
Active
Bank 0
Read
Bank 0
Precharge
Data Sheet E0848E10 (Ver. 1.0)
25
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
EDD2516ARTA-6B
Write Cycle
tCK
tCH
tCL
CK
/CK
tRC
VIH
CKE
tRAS
tRP
tRCD
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
tIS tIH
/CS
/RAS
/CAS
/WE
BA
A10
tIS tIH
Address
tDQSS
DQS
(input)
tDQSL
tWPST
tDQSH
tDS
tDS
tDH
DM
tDS
tDH
DQ (input)
tWR
tDH
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
Data Sheet E0848E10 (Ver. 1.0)
26
CL = 2
BL = 4
Bank0 Access
= VIH or VIL
EDD2516ARTA-6B
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
code
Address
C: b
R: b
code
valid
DM
High-Z
DQS
High-Z
b
DQ (output)
tMRD
tRP
Mode
register
set
Precharge
If needed
Bank 3
Read
Bank 3
Active
Bank 3
Precharge
CL = 2
BL = 4
= VIH or VIL
Read/Write Cycle
/CK
CK
CKE
0
1
2
3
4
C:a
R:b
5
6
7
8
9
10
11
12
13
14
15
VIH
/CS
/RAS
/CAS
/WE
BA
Address
R:a
C:b''
C:b
DM
DQS
a
DQ (output)
b’’
High-Z
DQ (input)
b
tRWD
Bank 0
Active
tWRD
Bank 0 Bank 3
Read Active
Bank 3
Write
Data Sheet E0848E10 (Ver. 1.0)
27
Bank 3
Read
Read cycle
CL = 2
BL = 4
=VIH or VIL
;;;;;
;
;
;
;
;
;
;;;
EDD2516ARTA-6B
;;;;;;;;;
;
;
;
;
;;;;;;;;;
;
;
;
;;
Auto Refresh Cycle
/CK
CK
CKE
VIH
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
b
DQ (output)
High-Z
DQ (input)
tRP
Precharge
If needed
tRFC
Auto
Refresh
Bank 0
Active
Bank 0
Read
CL = 2
BL = 4
= VIH or VIL
Data Sheet E0848E10 (Ver. 1.0)
28
EDD2516ARTA-6B
Self Refresh Cycle
/CK
CK
tIS
tIH
CKE
CKE = low
/CS
/RAS
/CAS
/WE
BA
Address
A10=1
R: b
C: b
DM
DQS
DQ (output)
High-Z
DQ (input)
tSNR
tRP
tSRD
Precharge
If needed
Self
refresh
entry
Self refresh
exit
Bank 0
Active
Bank 0
Read
CL = 2.5
BL = 4
= VIH or VIL
Data Sheet E0848E10 (Ver. 1.0)
29
EDD2516ARTA-6B
Package Drawing
66-pin Plastic TSOP (II)
Unit: mm
22.22 ± 0.10 *
1
A
PIN#1 ID
1
0.65
2
0.22 +0.1
−0.05*
33
11.76 ± 0.20
34
10.16
66
B
0.13 M S A B
0.80
Nom
0.25
0.125 ± 0.075
0.125 +0.05
−0.02
0.10 S
S
1.20 max
1.0 ± 0.05
0 to 10°
0.60 ± 0.15
Notes: 1. This dimension does not include mold flash.
2. This dimension does not include trim offset.
0.71
0.86 max
ECA-TS2-0097-01
Data Sheet E0848E10 (Ver. 1.0)
30
EDD2516ARTA-6B
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the EDD2516ARTA.
Type of Surface Mount Device
EDD2516ARTA: 66-pin Plastic TSOP (II)
Data Sheet E0848E10 (Ver. 1.0)
31
EDD2516ARTA-6B
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
Data Sheet E0848E10 (Ver. 1.0)
32
EDD2516ARTA-6B
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
M01E0107
Data Sheet E0848E10 (Ver. 1.0)
33