PRELIMINARY DATA SHEET 256M bits DDR SDRAM with Super Self-Refresh EDD2516KCTA (16M words × 16 bits) Specifications Pin Configurations • Density: 256M bits • Organization ⎯ 4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS compliant) • Power supply: VDD, VDDQ = 2.5V ± 0.2V • Data rate: 333Mbps/266Mbps (max.) • Four internal banks for concurrent operation • Interface: SSTL_2 • Burst lengths (BL): 2, 4, 8 • Burst type (BT): ⎯ Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5 • Precharge: auto precharge operation for each burst access • Driver strength: normal/weak • Refresh: auto-refresh, super self-refresh with Auto Temperature Compensated Self-refresh (ATCSR) function • Refresh cycles: 8192 cycles/64ms ⎯ Average refresh period: 7.8μs • Operating ambient temperature range ⎯ TA = 0°C to +70°C /xxx indicates active low signal. 66-pin Plastic TSOP(II) L EO 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 VSS (Top view) A0 to A12 BA0, BA1 DQ0 to DQ15 UDQS/LDQS /CS /RAS /CAS /WE UDM/LDM CK /CK CKE VREF VDD VSS VDDQ VSSQ NC SF Address input Bank select address Data-input/output Input and output data strobe Chip select Row address strobe command Column address strobe command Write enable Input mask Clock input Differential clock input Clock enable Input reference voltage Power for internal circuit Ground for internal circuit Power for DQ circuit Ground for DQ circuit No connection SSR Flag t uc • Double-data-rate architecture; two data transfers per clock cycle • The high-speed data transfer is realized by the 2 bits prefetch pipelined architecture • Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS • Data mask (DM) for write data • SSR Flag function available Document No. E0641E20 (Ver.2.0) Date Published December 2005 (K) Japan Printed in Japan URL: http://www.elpida.com 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 od Pr Features VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS SF VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10(AP) A0 A1 A2 A3 VDD This product became EOL in April, 2007. ©Elpida Memory, Inc. 2005 EDD2516KCTA Ordering Information Mask version Part number EDD2516KCTA-6BS-E EDD2516KCTA-7AS-E EDD2516KCTA-7BS-E C Organization (words × bits) 16M × 16 Internal banks Data rate Mbps (max.) JEDEC speed bin (CL-tRCD-tRP) 4 333 266 266 DDR333B (2.5-3-3) DDR266A (2-3-3) DDR266B (2.5-3-3) Package 66-pin Plastic TSOP (II) Part Number E D D 25 16 K C TA - 6B S - E Elpida Memory EO Environment Code E: Lead Free Type D: Monolithic Device Spec Detail S: 0 to +70°C Product Family D: DDR SDRAM Speed 6B: DDR333B (2.5-3-3) 7A: DDR266A (2-3-3) 7B: DDR266B (2.5-3-3) Density / Bank 25: 256M / 4-bank Organization 16: x16 L Package TA: TSOP (II) Power Supply, Interface K: 2.5V, SSTL_2, Super self-refresh with SSR flag Die Rev. t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 2 EDD2516KCTA CONTENTS Specifications ................................................................................................................................................ 1 Features ........................................................................................................................................................ 1 Pin Configurations......................................................................................................................................... 1 Ordering Information ..................................................................................................................................... 2 Part Number.................................................................................................................................................. 2 Electrical Specifications ................................................................................................................................ 4 Block Diagram............................................................................................................................................. 11 Pin Function ................................................................................................................................................ 12 Command Operation................................................................................................................................... 14 EO Simplified State Diagram ............................................................................................................................ 21 Operation of the DDR SDRAM ................................................................................................................... 22 Timing Waveforms ...................................................................................................................................... 42 Package Drawing........................................................................................................................................ 49 Recommended Soldering Conditions ......................................................................................................... 50 L t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 3 EDD2516KCTA Electrical Specifications • All voltages are referenced to VSS (GND). • After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before proper device operation is achieved. Absolute Maximum Ratings Symbol Rating Unit Voltage on any pin relative to VSS VT –1.0 to +3.6 V Supply voltage relative to VSS VDD –1.0 to +3.6 V Short circuit output current IOS 50 mA Power dissipation PD 1.0 W Operating ambient temperature TA 0 to +70 °C Storage temperature Tstg –55 to +125 °C EO Parameter Note Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions (TA = 0 to +70°C) Supply voltage Symbol L Parameter VDD, VDDQ VSS, VSSQ min. typ. max. Unit Notes 2.3 2.5 2.7 V 1 0 0 0 V VREF 0.49 × VDDQ 0.50 × VDDQ 0.51 × VDDQ V Termination voltage VTT VREF – 0.04 VREF VREF + 0.04 V Input high voltage VIH (DC) VREF + 0.15 — VDDQ + 0.3 V 2 Input low voltage VIL (DC) –0.3 — VREF – 0.15 V 3 VIN (DC) –0.3 — VDDQ + 0.3 V 4 VIX (DC) 0.5 × VDDQ − 0.2V 0.5 × VDDQ 0.5 × VDDQ + 0.2V V VID (DC) 0.36 — VDDQ + 0.6 V 5, 6 VDDQ must be lower than or equal to VDD. VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns. VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns. VIN (DC) specifies the allowable DC execution of each differential input. VID (DC) specifies the input differential voltage required for switching. VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement. t uc Notes: 1. 2. 3. 4. 5. 6. od Input voltage level, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input differential voltage, CK and /CK inputs Pr Input reference voltage Preliminary Data Sheet E0641E20 (Ver.2.0) 4 EDD2516KCTA DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) max. Parameter Symbol Operating current (ACTPRE) Operating current (ACT-READ-PRE) Idle power down standby current IDD0 IDD1 -6B -7A, -7B -6B -7A, -7B 110 100 140 130 3 IDD2Q Active power down standby current IDD3P Active standby current IDD3N EO Quiet idle standby current Auto Refresh current × 16 IDD2P Floating idle standby current IDD2F Operating current (Burst read operation) Operating current (Burst write operation) Grade -6B -7A, -7B -6B -7A, -7B IDD4R IDD4W IDD5 mA mA mA 35 30 30 25 20 -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B -6B -7A, -7B Unit 55 50 205 180 205 180 200 175 mA mA mA mA mA mA mA L 150 µA 40 µA IDD6SSRPEAK 3.5 mA Super self-refresh current IDD6SSR Pr IDD6SSRENT IDD6SSREX Operating current (4 banks interleaving) IDD7A -6B -7A, -7B Test condition Notes CKE ≥ VIH, 1, 2, 9 tRC = tRC (min.) CKE ≥ VIH, BL = 4,CL = 2.5, 1, 2, 5 tRC = tRC (min.) CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF CKE ≥ VIH, /CS ≥ VIH DQ, DQS, DM = VREF CKE ≤ VIL CKE ≥ VIH, /CS ≥ VIH tRAS = tRAS (max.) CKE ≥ VIH, BL = 2, CL = 2.5 CKE ≥ VIH, BL = 2 CL = 2.5 tRFC = tRFC (min.), Input ≤ VIL or ≥ VIH TA ≤ 70°C, Input ≥ VDD – 0.2V, Input ≤ 0.2V TA = 25°C, typical condition Input ≥ VDD – 0.2V, Input ≤ 0.2V Input ≥ VDD – 0.2V, Input ≤ 0.2V 4 4, 5 4, 10 3 3, 5, 6 1, 2, 5, 6 1, 2, 5, 6 11, 15 11, 14, 15 15 3 mA 12 250 mA 13 350 300 mA BL = 4 1, 5, 6, 7 t uc od Notes: 1. These IDD data are measured under condition that DQ pins are not connected. 2. One bank operation. 3. One bank active. 4. All banks idle. 5. Command/Address transition once per one clock cycle. 6. DQ, DM and DQS transition twice per one clock cycle. 7. 4 banks active. Only one bank is running at tRC = tRC (min.) 8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general. 9. Command/Address transition once every two clock cycle. 10. Command/Address stable at ≥ VIH or ≤ VIL. 11. IDD6SSR varies automatically with TA. 12. IDD6SSRENT is average current during tSSRENT. Do not switch to low current power supply with less than IDD6SSRENT during tSSRENT. 13. IDD6SSREX is average current during “Exiting SSR”. Use high current power supply with more than IDD6SSREX during “Exiting SSR”. . 14. Typical value only for reference. Preliminary Data Sheet E0641E20 (Ver.2.0) 5 EDD2516KCTA 15. In super self-refresh state, burst refresh period and standby period repeat alternately. IDD6SSR is the average current during whole super self-refresh period (average current for burst refresh period and standby period). IDD6SSRPEAK is the average current during burst refresh period. DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) Parameter Symbol min. max. Unit Test condition Input leakage current ILI –2 2 µA VDD ≥ VIN ≥ VSS Output leakage current ILO –5 5 µA VDDQ ≥ VOUT ≥ VSS Output high current IOH –15.2 — mA VOUT = 1.95V Output low current IOL 15.2 — mA VOUT = 0.35V Notes EO Pin Capacitance (TA = +25°C, VDD, VDDQ = 2.5V ± 0.2V) Parameter Symbol Pins min. typ. max. Unit Notes Input capacitance CI1 CK, /CK 2.0 — 3.0 pF 1 CI2 All other input pins 2.0 — 3.0 pF 1 Cdi1 CK, /CK — — 0.25 pF 1 Cdi2 All other input-only pins — — 0.5 pF 1 Delta input capacitance L Data input/output capacitance CI/O DQ, DM, DQS 4.0 — 5 pF 1, 2 Delta input/output capacitance Cdio DQ, DM, DQS — — 0.5 pF 1 Notes: 1. These parameters are measured on conditions: TA = +25°C. 2. DOUT circuits are disabled. f = 100MHz, VOUT = VDDQ/2, ΔVOUT = 0.2V, t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 6 EDD2516KCTA AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V) -6B -7A -7B Parameter Symbol min. max. min. max. min. max Unit Notes Clock cycle time (CL = 2) tCK 7.5 12 7.5 12 10 12 ns 10 (CL = 2.5) tCK 6 12 7.5 12 7.5 12 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK tHP min (tCH, tCL) — min (tCH, tCL) — min (tCH, tCL) — tCK tAC –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 2, 11 tDQSCK –0.6 0.6 –0.75 0.75 –0.75 0.75 ns 2, 11 DQS to DQ skew tDQSQ — 0.45 — 0.5 — 0.5 ns 3 DQ/DQS output hold time from DQS tQH tHP – tQHS — tHP – tQHS — tHP – tQHS — ns Data hold skew factor tQHS — 0.55 — 0.75 — 0.75 ns –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 5, 11 –0.7 0.7 –0.75 0.75 –0.75 0.75 ns 6, 11 tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK DQ and DM input setup time tDS 0.45 — 0.5 — 0.5 — ns 8 DQ and DM input hold time tDH 0.45 — 0.5 — 0.5 — ns 8 DQ and DM input pulse width tDIPW 1.75 — 1.75 — 1.75 — ns 7 CK half period EO DQ output access time from CK, /CK DQS output access time from CK, /CK Data-out high-impedance time from tHZ CK, /CK Data-out low-impedance time from tLZ CK, /CK Read postamble L Read preamble Pr 0.6 tDSH — 0.2 — 0.2 — tCK — 0.35 — 0.35 — tCK — 0.35 — 0.35 — tCK — 0.9 — 0.9 — ns 8 — 0.9 — 0.9 — ns 8 — 2.2 — 2.2 — ns 7 2 — tCK tWPRES 0 — 0 — 0 — ns Write preamble tWPRE 0.25 — 0.25 — 0.25 — tCK Write postamble tWPST 0.4 0.6 0.4 0.4 0.6 tCK Write command to first DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 tCK DQS falling edge to CK setup time tDSS 0.2 — 0.2 — 0.2 — tCK DQS falling edge hold time from CK 0.2 DQS input high pulse width tDQSH 0.35 DQS input low pulse width tDQSL 0.35 Address and control input setup time tIS 0.75 Address and control input hold time tIH 0.75 Address and control input pulse width Mode register set command cycle time Active to Precharge command period Active to Active/Auto refresh command period Auto refresh to Active/Auto refresh command period od Write preamble setup time 2.2 tMRD 2 — 2 — tRAS 42 120000 45 120000 45 120000 ns tRC 60 — 67.5 — 67.5 — ns tRFC 72 — 75 — 75 — ns Active to Read/Write delay tRCD 18 — 20 — 20 — ns Precharge to active command period tRP 18 — 20 — 20 — ns Preliminary Data Sheet E0641E20 (Ver.2.0) 7 t uc tIPW 9 EDD2516KCTA -6B -7A -7B Parameter Symbol min. max. min. max. min. max Unit Active to Autoprecharge delay tRAP tRCD min. — tRCD min. — tRCD min. — ns Active to active command period tRRD 12 — 15 — 15 — ns Write recovery time tWR 15 — 15 — 15 — ns Auto precharge write recovery and tDAL precharge time Internal write to Read command tWTR delay (tWR/tCK)+ — (tRP/tCK) (tWR/tCK)+ — (tRP/tCK) (tWR/tCK)+ — (tRP/tCK) tCK 1 — 1 — 1 — tCK Notes 13 Average periodic refresh interval tREF — 7.8 — 7.8 — 7.8 µs Super self-refresh entry time tSSRENT — 30 — 30 — 30 s 200 — 200 — 200 — ms 14 1.5 — 1.5 — 1.5 — ms 14 EO SSR exit command to non refresh command delay tSSREX (SSRX command during “super self-refresh“) (SSRX command during “Entering tSSREX SSR”) SSR flag hold time tSSRFH 1 — 1 — 1 — µs SSR flag delay time tSSRFD — 40 — 40 — 40 ns SSR exit flag delay time tFDSSR — 40 — 40 — 40 ns 0.2 200 0.2 200 0.2 200 ms 14 0.2 1.5 0.2 1.5 0.2 1.5 ms 14 — 1 — 1 — 1 µs L SSR exit flag hold time (SSRX command during “super tFHSSR self-refresh“) (SSRX command during “Entering tFHSSR SSR”) Flag reset delay time by SSR tFRD command t uc od Pr Notes: 1. On all AC measurements, we assume the test conditions shown in the next page. For timing parameter definitions, see ‘Timing Waveforms’ section. 2. This parameter defines the signal transition delay from the cross point of CK and /CK. The signal transition is defined to occur when the signal level crossing VTT. 3. The timing reference level is VTT. 4. Output valid window is defined to be the period between two successive transition of data out or DQS (read) signals. The signal transition is defined to occur when the signal level crossing VTT. 5. tHZ is defined as DOUT transition delay from Low-Z to High-Z at the end of read burst operation. The timing reference is cross point of CK and /CK. This parameter is not referred to a specific DOUT voltage level, but specify when the device output stops driving. 6. tLZ is defined as DOUT transition delay from High-Z to Low-Z at the beginning of read operation. This parameter is not referred to a specific DOUT voltage level, but specify when the device output begins driving. 7. Input valid windows is defined to be the period between two successive transition of data input or DQS (write) signals. The signal transition is defined to occur when the signal level crossing VREF. 8. The timing reference level is VREF. 9. The transition from Low-Z to High-Z is defined to occur when the device output stops driving. A specific reference voltage to judge this transition is not given. 10. tCK (max.) is determined by the lock range of the DLL. Beyond this lock range, the DLL operation is not assured. 11. tCK = tCK (min) when these parameters are measured. Otherwise, absolute minimum values of these values are 10% of tCK. 12. VDD is assumed to be 2.5V ± 0.2V. VDD power supply variation per cycle expected to be less than 0.4V/400 cycle. Preliminary Data Sheet E0641E20 (Ver.2.0) 8 EDD2516KCTA 13. tDAL = (tWR/tCK)+(tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For -7A Speed at CL = 2.5, tCK = 7.5ns, tWR = 15ns and tRP= 20ns, tDAL = (15ns/7.5ns) + (20ns/7.5ns) = (2) + (3) tDAL = 5 clocks 14. When the memory is in “Exiting SSR” state, any command except SSR is ignored. If SF pin is monitored by the system and as soon as it returns to low (tFHSSR), any command for IDLE state will be accepted by the memory. (tSSREX is "Don't care" in this case. ) If SF pin is not monitored, tSSREX has to be satisfied. (Issue auto refresh command repeatedly at less than 7.8μs interval during tSSREX.) Test Conditions EO Parameter Symbol Value Unit Input reference voltage VREF VDDQ/2 V Termination voltage VTT VREF V Input high voltage VIH (AC) VREF + 0.31 V Input low voltage VIL (AC) VREF − 0.31 V VID (AC) 0.62 V VIX (AC) VREF V SLEW 1 V/ns L Input differential voltage, CK and /CK inputs Input differential cross point voltage, CK and /CK inputs Input signal slew rate tCK VDD Pr CK VID /CK tCL VSS tCH VIX VDD VREF od VIH VIL VREF VSS Δt SLEW = (VIH (AC) – VIL (AC))/Δt Measurement point RT = 50Ω DQ CL = 30pF Input Waveforms and Output Load Preliminary Data Sheet E0641E20 (Ver.2.0) 9 t uc VTT EDD2516KCTA Timing Parameter Measured in Clock Cycle Number of clock cycle tCK 6ns Parameter Symbol 7.5ns max. min. max. Unit Write to pre-charge command delay (same bank) tWPD 4 + BL/2 — 3 + BL/2 — tCK Read to pre-charge command delay (same bank) tRPD BL/2 — BL/2 — tCK Write to read command delay (to input all data) tWRD 2 + BL/2 — 2 + BL/2 — tCK Burst stop command to write command delay (CL = 2) tBSTW — — 2 — tCK (CL = 2.5) tBSTW 3 — 3 — tCK Burst stop command to DQ High-Z (CL = 2) tBSTZ — — 2 2 tCK (CL = 2.5) tBSTZ 2.5 2.5 2.5 2.5 tCK Read command to write command delay (to output all data) (CL = 2) tRWD — — 2 + BL/2 — tCK (CL = 2.5) tRWD 3 + BL/2 — 3 + BL/2 — tCK Pre-charge command to High-Z (CL = 2) tHZP — — 2 2 tCK (CL = 2.5) tHZP 2.5 2.5 2.5 2.5 tCK Write command to data in latency tWCD 1 1 1 1 tCK tWR 3 — 2 — tCK DM to data in latency tDMD 0 0 0 0 tCK Mode register set command cycle time tMRD 2 — 2 — tCK Power down entry tPDEN 1 1 1 1 tCK Power down exit to command input tPDEX 1 — 1 — tCK Write recovery L EO min. t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 10 EDD2516KCTA Clock generator Block Diagram Bank 3 Bank 2 Bank 1 A0 to A12, BA0, BA1 Memory cell array Bank 0 Sense amp. L Control logic Command decoder EO /CS /RAS /CAS /WE Mode register Row address buffer and refresh counter Row decoder CK /CK CKE Column decoder Column address buffer and burst counter Data control circuit Latch circuit Pr DLL CK, /CK Input & Output buffer DQS DM DQ t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 11 EDD2516KCTA Pin Function CK, /CK (input pins) The CK and the /CK are the master clock inputs. All inputs except DM, DQS and DQs are referred to the cross point of the CK rising edge and the /CK falling edge. When a read operation, DQS and DQs are referred to the cross point of the CK and the /CK. When a write operation, DQS and DQs are referred to the cross point of the DQS and the VREF level. DQS for write operation is referred to the cross point of the CK and the /CK. CK is the master clock input to this pin. The other input signals are referred at CK rising edge. /CS (input pin) When /CS is Low, commands and data can be input. When /CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. EO /RAS, /CAS, and /WE (input pins) These pins define operating commands (read, write, etc.) depending on the combinations of their voltage levels. See "Command operation". A0 to A12 (input pins) Row address (AX0 to AX12) is determined by the A0 to the A12 level at the cross point of the CK rising edge and the /CK falling edge in a bank active command cycle. Column address (See “Address Pins Table”) is loaded via the A0 to the A8 at the cross point of the CK rising edge and the /CK falling edge in a read or a write command cycle. This column address becomes the starting address of a burst operation. [Address Pins Table] L Address (A0 to A12) Part number EDD2516KCTA Row address Column address AX0 to AX12 AY0 to AY8 Pr A10 (AP) (input pin) A10 defines the precharge mode when a precharge command, a read command or a write command is issued. If A10 = High when a precharge command is issued, all banks are precharged. If A10 = Low when a precharge command is issued, only the bank that is selected by BA1/BA0 is precharged. If A10 = High when read or write command, auto-precharge function is enabled. While A10 = Low, auto-precharge function is disabled. [Bank Select Signal Table] BA0 Bank 0 L Bank 1 H L Bank 3 H BA1 L L H H t uc Bank 2 od BA0 and BA1 (input pins) BA0, BA1 are bank select signals (BA). The memory array is divided into bank 0, bank 1, bank 2 and bank 3. (See Bank Select Signal Table) Remark: H: VIH. L: VIL. Preliminary Data Sheet E0641E20 (Ver.2.0) 12 EDD2516KCTA CKE (input pin) This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low. CKE controls power down and super self-refresh. The power down and the super self-refresh commands are entered when the CKE is driven Low and exited when it resumes to High. CKE must be maintained high throughout read or write access. The CKE level must be kept for 1 CK cycle at least, that is, if CKE changes at the cross point of the CK rising edge and the /CK falling edge with proper setup time tIS, by the next CK rising edge CKE level must be kept with proper hold time tIH. UDM, LDM (input pin) DMs are the reference signals of the data input mask function. DMs are sampled at the cross point of DQS and VREF. DMs provide the byte mask function. In × 16 products, LDM controls the lower byte (DQ0 to DQ7) and UDM controls the upper byte (DQ8 to DQ15) of write data. When DM = High, the data input at the same timing are masked while the internal burst counter will be count up. EO DQ0 to DQ15 (input and output pins) Data is input to and output from these pins. UDQS, LDQS (input and output pin) DQS provide the read data strobes (as output) and the write data strobes (as input). In ×16 products, LDQS is the lower byte (DQ0 to DQ7) data strobe signal, UDQS is the upper byte (DQ8 to DQ15) data strobe signal. L VDD, VSS, VDDQ, VSSQ (Power supply) VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output buffers. t uc od Pr SF (SSR Flag, output pin) SSR Flag has 3 purposes. • SSR identification flag: To show the memory is SSR (High for tSSRFH when MRS/EMRS command is issued). • SSR exit flag: To show “Exiting SSR” duration. • SSR uncorrectable flag: To show error correction result (returns to low if success, keeps high if fail. (If fail, flag is reset by EMRS/MRS command.)) Preliminary Data Sheet E0641E20 (Ver.2.0) 13 EDD2516KCTA Command Operation Command Truth Table DDR SDRAM recognize the following commands specified by the /CS, /RAS, /CAS, /WE and address pins. All other combinations than those in the table below are illegal. CKE Symbol n–1 n /CS /RAS /CAS /WE BA1 BA0 AP Address Ignore command DESL H H H × × × × × × × No operation NOP H H L H H H × × × × Burst stop in read command BST H H L H H L × × × × Column address and read command READ H H L H L H V V L V Read with auto-precharge READA H H L H L H V V H V Column address and write command WRIT H H L H L L V V L V Write with auto-precharge WRITA H H L H L L V V H V Row address strobe and bank active ACT H H L L H H V V V V Precharge select bank PRE H H L L H L V V L × Precharge all bank PALL H H L L H L × × H × Refresh REF H H L L L H × × × × Super self-refresh SSR H L L L L H × × × × Mode register set MRS H H L L L L L L L V EMRS H H L L L L L H L V L EO Command Remark: H: VIH. L: VIL. ×: VIH or VIL V: Valid address input Note: The CKE level must be kept for 1 CK cycle at least. Pr Ignore command [DESL] When /CS is High at the cross point of the CK rising edge and the VREF level, every input are neglected and internal status is held. od No operation [NOP] As long as this command is input at the cross point of the CK rising edge and the VREF level, address and data input are neglected and internal status is held. Burst stop in read operation [BST] This command stops a burst read operation, which is not applicable for a burst write operation. t uc Column address strobe and read command [READ] This command starts a read operation. The start address of the burst read is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. After the completion of the read operation, the output buffer becomes High-Z. Read with auto-precharge [READA] This command starts a read operation. After completion of the read operation, precharge is automatically executed. Column address strobe and write command [WRIT] This command starts a write operation. The start address of the burst write is determined by the column address (See “Address Pins Table” in Pin Function) and the bank select address. Write with auto-precharge [WRITA] This command starts a write operation. After completion of the write operation, precharge is automatically executed. Preliminary Data Sheet E0641E20 (Ver.2.0) 14 EDD2516KCTA Row address strobe and bank activate [ACT] This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12). (See Bank Select Signal Table) Precharge selected bank [PRE] This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table) [Bank Select Signal Table] BA0 BA1 Bank 0 L L Bank 1 H L Bank 2 L H Bank 3 H H EO Remark: H: VIH. L: VIL. Precharge all banks [PALL] This command starts a precharge operation for all banks. Refresh [REF/SSR] This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another is super self-refresh. For details, refer to the CKE truth table section. L Mode register set/Extended mode register set [MRS/EMRS] The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode register set cycle. For details, refer to "Mode register and extended mode register set". Pr CKE Truth Table CKE Current state Command Idle Auto-refresh command (REF) n–1 n /CS /RAS /CAS /WE Address Notes H L L L H × 2 H L L L L H × 2 Idle H L L H H H × H L H × × × × L H L H H H × L H H × × × × L H L H H H × L H H × × × × Power down entry (PDEN) Entering SSR or Super self-refresh exit (SSRX) Super self-refresh Power down Power down exit (PDEX) Remark: H: VIH. L: VIL. ×: VIH or VIL. Notes: 1. All the banks must be in IDLE before executing this command. 2. The CKE level must be kept for 1 CK cycle at least. Preliminary Data Sheet E0641E20 (Ver.2.0) 15 t uc od H Idle or Exiting SSR Super self-refresh entry (SSR) EDD2516KCTA Function Truth Table The following tables show the operations that are performed when each command is issued in each state of the DDR SDRAM. Current state /CS /RAS /CAS /WE Address Command Operation Next state Precharging*1 H × × × × DESL NOP ldle L H H H × NOP NOP ldle 11 L H H L × BST ILLEGAL* — L H L H BA, CA, A10 READ/READA ILLEGAL*11 — 11 — 11 L H L L BA, CA, A10 WRIT/WRITA ILLEGAL* L L H H BA, RA ACT ILLEGAL* — L L H L BA, A10 PRE, PALL NOP ldle L EO L × × ILLEGAL — H × × × × DESL NOP ldle L H H H × NOP NOP L Idle* 2 L H H L — H L H BA, CA, A10 READ/READA ILLEGAL* H L L BA, CA, A10 WRIT/WRITA ILLEGAL*11 — L L H H BA, RA ACT Activating Active L L H L BA, A10 PRE, PALL NOP ldle L L L H × REF, SSR Refresh/ Super self-refresh*12 ldle/ Super selfrefresh L L L L MODE MRS Mode register set*12 ldle H × × × × DESL NOP ldle L H H H × NOP NOP ldle L H H L × BST ILLEGAL — L H L × × ILLEGAL — L L × × × ILLEGAL — H × × × × DESL NOP Active NOP NOP Active BST ILLEGAL*11 — READ/READA ILLEGAL*11 — 11 — L H H H × L H H L × L H L H BA, CA, A10 od L H L L BA, CA, A10 WRIT/WRITA ILLEGAL* L L H H BA, RA ACT ILLEGAL*11 — 11 — L L H L BA, A10 PRE, PALL L L L × × H × × × × DESL L H H H × NOP L H H L × BST L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/WRITA L L H H BA, RA ACT L L H L BA, A10 PRE, PALL L L L × × ILLEGAL* ILLEGAL Preliminary Data Sheet E0641E20 (Ver.2.0) 16 — t uc Active*5 — 11 ILLEGAL* L Pr Activating*4 BST L L Refresh (auto-refresh)*3 × ldle 11 NOP Active NOP Active ILLEGAL Active Starting read operation Read/READA Write Starting write operation recovering/ precharging ILLEGAL*11 — Pre-charge Idle ILLEGAL — EDD2516KCTA Current state 6 Read* /CS /RAS /CAS /WE Address Command Operation Next state H × × × × DESL NOP Active L H H H × NOP NOP Active L H H L × BST BST Active L H L H BA, CA, A10 READ/READA Interrupting burst read operation to start new read Active L H L L BA, CA, A10 WRIT/WRITA ILLEGAL*13 — 11 L L H H BA, RA L L H L BA, A10 L L L × × EO ACT ILLEGAL* — PRE, PALL Interrupting burst read operation to start pre-charge Precharging ILLEGAL — NOP Precharging Read with auto-preH charge*7 × × × × DESL L H H H × NOP NOP Precharging L H H L × BST ILLEGAL — L H L H BA, CA, A10 READ/READA ILLEGAL*14 — 14 — L H L L BA, CA, A10 WRIT/WRITA ILLEGAL* L L H H BA, RA ACT ILLEGAL*11, 14 — 11, 14 — L L H L L L 8 Write* × × ILLEGAL* ILLEGAL H × × × × DESL NOP L H H H × NOP NOP L H H L × BST ILLEGAL — Write recovering Write recovering — Interrupting burst write operation to start read operation. Interrupting burst write operation to start new write operation. L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/WRITA L L H H BA, RA ACT ILLEGAL*11 — PRE, PALL Interrupting write operation to start precharge. Idle ILLEGAL — NOP Active NOP NOP Active BST ILLEGAL — L L H L BA, A10 L L L × × H × × × × L H H H × L H H L × L H L H BA, CA, A10 L L H L L H L H DESL READ/READA BA, CA, A10 WRIT/WRITA BA, RA L L H L BA, A10 L L L × × ACT PRE/PALL Preliminary Data Sheet E0641E20 (Ver.2.0) 17 Read/ReadA Write/WriteA t uc od Write recovering* L PRE, PALL Pr 9 L BA, A10 Starting read operation. Read/ReadA Starting new write operation. Write/WriteA 11 — 11 ILLEGAL* — ILLEGAL — ILLEGAL* EDD2516KCTA Current state /CS /RAS /CAS /WE Address Command Operation Next state Write with autopre-charge*10 H × × × × DESL NOP Precharging L H H H × NOP NOP Precharging L H H L × BST ILLEGAL L H L H BA, CA, A10 READ/READA — ILLEGAL* 14 — 14 — L H L L BA, CA, A10 WRIT/WRIT A ILLEGAL* L L H H BA, RA ACT ILLEGAL*11, 14 — 11, 14 ILLEGAL* — ILLEGAL — L L H L BA, A10 L L L × × PRE, PALL H: VIH. L: VIL. ×: VIH or VIL The DDR SDRAM is in "Precharging" state for tRP after precharge command is issued. The DDR SDRAM reaches "IDLE" state tRP after precharge command is issued. The DDR SDRAM is in "Refresh" state for tRFC after auto-refresh command is issued. The DDR SDRAM is in "Activating" state for tRCD after ACT command is issued. The DDR SDRAM is in "Active" state after "Activating" is completed. The DDR SDRAM is in "READ" state until burst data have been output and DQ output circuits are turned off. 7. The DDR SDRAM is in "READ with auto-precharge" from READA command until burst data has been output and DQ output circuits are turned off. 8. The DDR SDRAM is in "WRITE" state from WRIT command to the last burst data are input. 9. The DDR SDRAM is in "Write recovering" for tWR after the last data are input. 10. The DDR SDRAM is in "Write with auto-precharge" until tWR after the last data has been input. 11. This command may be issued for other banks, depending on the state of the banks. 12. All banks must be in "IDLE". 13. Before executing a write command to stop the preceding burst read operation, BST command must be issued. 14. The DDR SDRAM supports the concurrent auto-precharge feature, a read with auto-precharge enabled,or a write with auto-precharge enabled, may be followed by any column command to other banks, as long as that command does not interrupt the read or write data transfer, and all other related limitations apply. (E.g. Conflict between READ data and WRITE data must be avoided.) L EO Remark: Notes: 1. 2. 3. 4. 5. 6. od Pr The minimum delay from a read or write command with auto precharge enabled, to a command to a different bank, is summarized below. From command Read w/AP To command (different bank, noninterrupting command) Read or Read w/AP Write or Write w/AP Precharge or Activate Read or Read w/AP Units BL/2 tCK CL(rounded up)+ (BL/2) tCK 1 tCK 1 + (BL/2) + tWTR tCK Write or Write w/AP BL/2 tCK Precharge or Activate 1 Preliminary Data Sheet E0641E20 (Ver.2.0) 18 t uc Write w/AP Minimum delay (Concurrent AP supported) tCK EDD2516KCTA Command Truth Table for CKE CKE Current State n–1 n Super self-refresh H Entering super self*2 refresh /RAS /CAS /WE Address Operation × × × × × × INVALID, CK (n-1) would exit super self-refresh L H H × × × × Exit super self-refresh L H L H H × × Exit super self-refresh L H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × Maintain super self-refresh H × × × × × × INVALID, CK (n-1) would exit super self-refresh L H H × × × × Exit super self-refresh L H L H H × × Exit super self-refresh L H L H L × × ILLEGAL L H L L × × × ILLEGAL L L × × × × × Continue super self-refresh entry (super self-refresh after tSSRENT) H H H × × × × Idle after tFHSSR H H L H H × × Idle after tFHSSR EO /CS Exiting super self*3 refresh L L L L H × Super self-refresh entry L H L × × ILLEGAL H H L L × × × ILLEGAL H L H × × × × ILLEGAL H L L H H × × ILLEGAL H L L H L × × ILLEGAL × H L L L × × H × × × × × L H H × × × × ILLEGAL INVALID, CK (n – 1) would exit power down EXIT power down → Idle L H L H H H × L L × × × × × H H H × × × H H L H × × H H L L H × H H L L L H H H L L L L H L H × × × H L L H × × H L L L H × H L L L L H × H L L L L L OPCODE Refer to operations in Function Truth Table Maintain power down mode Refer to operations in Function Truth Table Refer to operations in Function Truth Table Refer to operations in Function Truth Table × CBR (auto) refresh OPCODE Refer to operations in Function Truth Table Refer to operations in Function Truth Table t uc Row active L H od All banks idle H H Pr Power down Notes Refer to operations in Function Truth Table Refer to operations in Function Truth Table Super self-refresh L × × × × × × Power down H × × × × × × Refer to operations in Function Truth Table L × × × × × × Power down Remark: H: VIH. L: VIL. ×: VIH or VIL Preliminary Data Sheet E0641E20 (Ver.2.0) 19 1 1 1 EDD2516KCTA Notes: 1. Super self-refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state. 2. The device is in “Entering super self-refresh” state during tSSRENT. 3. The device is in “Exiting super self-refresh” state during tFHSSR. Auto-refresh command [REF] This command executes auto-refresh. The banks and the ROW addresses to be refreshed are internally determined by the internal refresh controller. The average refresh cycle is 7.8 μs. The output buffer becomes High-Z after autorefresh start. Precharge has been completed automatically after the auto-refresh. The ACT or MRS command can be issued tRFC after the last auto-refresh command. EO Super self-refresh entry [SSR] This command starts super self-refresh. The super self-refresh operation continues as long as CKE is held Low. During the super self-refresh operation, all ROW addresses are repeated refreshing by the internal refresh controller. A super self-refresh is terminated by a super self-refresh exit command. Power down mode entry [PDEN] tPDEN (= 1 cycle) after the cycle when [PDEN] is issued. The DDR SDRAM enters into power-down mode. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. No internal refresh operation occurs during the power down mode. [PDEN] do not disable DLL. L Super self-refresh exit [SSRX] This command is executed to exit from super self-refresh mode (After tFHSSR from SSRX command, the device becomes IDLE). If SSR Exit flag is not monitored by the system, issue auto refresh command repeatedly at less than 7.8μs interval during tSSREX. t uc od Pr Power down exit [PDEX] The DDR SDRAM can exit from power down mode tPDEX (1 cycle min.) after the cycle when [PDEX] is issued. Preliminary Data Sheet E0641E20 (Ver.2.0) 20 EDD2516KCTA Simplified State Diagram SUPER SELF REFRESH ENTERING SSR SSR SSRX SSRX SSR EXITING SSR REFRESH IDLE *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE ACTIVE POWER DOWN CKE_ CKE L EO MRS MODE REGISTER SET ROW ACTIVE BST WRITE Write WRITE READ WRITE WITH AP READ WITH AP Read READ READ Pr READ WITH AP WRITE WITH AP READ WITH AP PRECHARGE WRITEA READA PRECHARGE POWER ON od POWER APPLIED PRECHARGE PRECHARGING PRECHARGE Automatic transition after completion of command. Transition resulting from command input. t uc Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. Preliminary Data Sheet E0641E20 (Ver.2.0) 21 EDD2516KCTA Operation of the DDR SDRAM Power-up Sequence EO (1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined). Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VTT and VREF. (2) Start clock and maintain stable condition for a minimum of 200 µs. (3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high. (4) Issue precharge all command for the device. (5) Issue EMRS to enable DLL. (6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of clock input is required to lock the DLL after every DLL reset). (7) Issue precharge all command for the device. (8) Issue 2 or more auto-refresh commands. (9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting the DLL. (4) (5) PALL EMRS (6) (7) MRS PALL (8) (9) CK /CK L Command 2 cycles (min.) REF REF tRP 2 cycles (min.) 2 cycles (min.) REF tRFC tRFC DLL reset with A8 = High DLL enable Any command MRS 2 cycles (min.) Disable DLL reset with A8 = Low 200 cycles (min) Power-up Sequence after CKE Goes High Pr Mode Register and Extended Mode Register Set BA0 BA1 A12 0 0 0 A11 A10 A9 0 0 0 A8 A7 DR 0 A6 1 1 0 A4 LMODE A8 DLL Reset A6 A5 A4 CAS Latency 2 0 1 0 0 No 1 Yes A5 2.5 A3 22 A1 BT A3 Burst Type 0 Sequential 1 Interleave Mode Register Set [MRS] (BA0 = 0, BA1 = 0) Preliminary Data Sheet E0641E20 (Ver.2.0) A2 A0 BL t uc MRS od There are two mode registers, the mode register and the extended mode register so as to define the operating mode. Parameters are set to both through the A0 to the A12 and BA0, BA1 pins by the mode register set command [MRS] or the extended mode register set command [EMRS]. The mode register and the extended mode register are set by inputting signal via the A0 to the A12 and BA0, BA1 during mode register set cycles. BA0 and BA1 determine which one of the mode register or the extended mode register are set. Prior to a read or a write operation, the mode register must be set. Remind that no other parameters shown in the table bellow are allowed to input to the registers. A2 A1 A0 Burst Length BT=0 BT=1 2 2 0 0 1 0 1 0 4 4 0 1 1 8 8 EDD2516KCTA BA0 BA1 1 A12 A11 A10 A9 0 0 0 0 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 0 0 0 0 0 0 DS DLL EMRS A1 Driver Strength A0 DLL Control 0 Normal 0 DLL Enable 1 Weak 1 DLL Disable Extended Mode Register Set [EMRS] (BA0 = 1, BA1 = 0) Burst Operation EO The burst type (BT) and the first three bits of the column address determine the order of a data out. Burst length = 2 Burst length = 4 Starting Ad. Addressing(decimal) A0 Sequence Starting Ad. Addressing(decimal) Interleave A1 A0 0 0, 1, 0, 1, 0 0 0, 1, 2, 3, 0, 1, 2, 3, 1 1, 0, 1, 0, 0 1 1, 2, 3, 0, 1, 0, 3, 2, 1 0 2, 3, 0, 1, 2, 3, 0, 1, 1 1 3, 0, 1, 2, 3, 2, 1, 0, Sequence Interleave L Burst length = 8 Addressing(decimal) Starting Ad. A1 0 0 A0 Sequence 0 0, 1, 2, 3, 4, 5, 6, 7, Interleave 0, 1, 2, 3, 4, 5, 6, 7, 0 0 1 1, 2, 3, 4, 5, 6, 7, 0, 1, 0, 3, 2, 5, 4, 7, 6, 0 1 0 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 0, 1, 6, 7, 4, 5, 0 1 1 3, 4, 5, 6, 7, 0, 1, 2, 3, 2, 1, 0, 7, 6, 5, 4, 1 0 0 4, 5, 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2, 3, 1 0 1 5, 6, 7, 0, 1, 2, 3, 4, 5, 4, 7, 6, 1, 0, 3, 2, 1 1 0 6, 7, 0, 1, 2, 3, 4, 5, 6, 7, 4, 5, 2, 3, 0, 1, 1 1 1 7, 0, 1, 2, 3, 4, 5, 6, 7, 6, 5, 4, 3, 2, 1, 0, t uc od Pr A2 Preliminary Data Sheet E0641E20 (Ver.2.0) 23 ; ;; EDD2516KCTA Read/Write Operations Bank active A read or a write operation begins with the bank active command [ACT]. The bank active command determines a bank address and a row address. For the bank and the row, a read or a write command can be issued tRCD after the ACT is issued. EO Read operation The burst length (BL), the /CAS latency (CL) and the burst type (BT) of the mode register are referred when a read command is issued. The burst length (BL) determines the length of a sequential output data by the read command that can be set to 2, 4, or 8. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12 and BA0, BA1 pins in the cycle when the read command is issued. The data output timing are characterized by CL and tAC. The read burst start CL • tCK + tAC (ns) after the clock rising edge where the read command are latched. The DDR SDRAM output the data strobe through DQS simultaneously with data. tRPRE prior to the first rising edge of the data strobe, the DQS are driven Low from VTT level. This low period of DQS is referred as read preamble. The burst data are output coincidentally at both the rising and falling edge of the data strobe. The DQ pins become High-Z in the next cycle after the burst read operation completed. tRPST from the last falling edge of the data strobe, the DQS pins become High-Z. This low period of DQS is referred as read postamble. t0 CK /CK Address t4 NOP t5 ACT NOP t7 Row READ t8 t9 NOP Column tRPRE Pr out0 out1 BL = 2 DQS DQ t6 tRCD L Command t1 out0 out1 out2 out3 BL = 4 od BL = 8 tRPST out0 out1 out2 out3 out4 out5 out6 out7 CL = 2 BL: Burst length Read Operation (Burst Length) t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 24 ;; ;;; EDD2516KCTA t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 CK /CK Command READ NOP tRPRE tRPST VTT DQS CL = 2 tAC,tDQSCK out0 DQ out1 out2 VTT out3 EO tRPRE tRPST VTT DQS CL = 2.5 tAC,tDQSCK out0 DQ out1 out2 VTT out3 Read Operation (/CAS Latency) L Write operation The burst length (BL) and the burst type (BT) of the mode register are referred when a write command is issued. The burst length (BL) determines the length of a sequential data input by the write command that can be set to 2, 4, or 8. The latency from write command to data input is fixed to 1. The starting address of the burst read is defined by the column address, the bank select address which are loaded via the A0 to A12, BA0 to BA1 pins in the cycle when the write command is issued. DQS should be input as the strobe for the input-data and DM as well during burst operation. tWPRE prior to the first rising edge of the DQS should be set to Low and tWPST after the last falling edge of the data strobe can be set to High-Z. The leading low period of DQS is referred as write preamble. The last low period of DQS is referred as write postamble. t1 Pr t0 tn tn+0.5 tn+1 CK /CK tn+2 tn+3 tn+4 tn+5 ;; tRCD Command ACT NOP Row WRITE Column NOP od Address NOP tWPRE tWPRES BL = 2 DQS DQ BL = 8 in1 tWPST in0 in1 in2 in3 in0 in1 in2 in3 t uc BL = 4 in0 in4 in5 in6 in7 BL: Burst length Write Operation Preliminary Data Sheet E0641E20 (Ver.2.0) 25 EDD2516KCTA Burst Stop Burst stop command during burst read The burst stop (BST) command is used to stop data output during a burst read. The BST command stops the burst read and sets the output buffer to High-Z. tBSTZ (= CL) cycles after a BST command issued, the DQ pins become High-Z. The BST command is not supported for the burst write operation. Note that bank address is not referred when this command is executed. t0 t0.5 t1 t1.5 t2 t2.5 t3 t3.5 t4 t4.5 t5 t5.5 CK /CK EO Command READ BST NOP tBSTZ 2 cycles DQS CL = 2 out0 DQ out1 tBSTZ 2.5 cycles DQS L CL = 2.5 out0 DQ out1 CL: /CAS latency t uc od Pr Burst Stop during a Read Operation Preliminary Data Sheet E0641E20 (Ver.2.0) 26 EDD2516KCTA Auto Precharge Read with auto-precharge The precharge is automatically performed after completing a read operation. The precharge starts tRPD (BL/2) cycle after READA command input. tRAP specification for READA allows a read command with auto precharge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS (min) specification. A column command to the other active bank can be issued the next cycle after the last data output. Read with auto-precharge command does not limit row commands execution for other bank. Refer to ‘Function truth table and related note(Notes.*14). CK /CK EO Command ACT tRP (min) tRPD 2 cycles (= BL/2) tRAP (min) = tRCD (min) NOP READA ACT DQS tAC,tDQSCK DQ out0 L Note: Internal auto-precharge starts at the timing indicated by " out1 out2 out3 ". Read with auto-precharge CK /CK tRAS (min) tRCD (min) Command ACT NOP NOP WRITA BL/2 + 3 cycles DM DQS DQ in1 in2 in3 Note: Internal auto-precharge starts at the timing indicated by " in4 ". Burst Write (BL = 4) Preliminary Data Sheet E0641E20 (Ver.2.0) 27 tRP ACT t uc od Pr Write with auto-precharge The precharge is automatically performed after completing a burst write operation. The precharge operation is started (BL/ 2 + 3) cycles after WRITA command issued. A column command to the other banks can be issued the next cycle after the internal precharge command issued. Write with auto-precharge command does not limit row commands execution for other bank. Refer to the ‘Read with Auto-Precharge Enabled, Write with Auto-Precharge Enabled’ section. Refer to ‘Function truth table and related note(Notes.*14). BL = 4 ; ;;;; EDD2516KCTA Command Intervals A Read command to the consecutive Read command Interval Destination row of the consecutive read command Bank address Row address State 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE Operation EO The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. The consecutive read can be performed after an interval of no less than 1 cycle to interrupt the preceding read operation. Precharge the bank without interrupting the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. IDLE t0 t3 t4 t5 READ READ t6 t7 t8 t9 CK /CK Address ACT NOP L Command Row NOP Column A Column B BA Pr out out A0 A1 DQ Column = A Column = B Read Read Bank0 Active Column = A Dout out B1 out B2 out B3 Column = B Dout od DQS out B0 CL = 2 BL = 4 Bank0 READ to READ Command Interval (same ROW address in the same bank) t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 28 EDD2516KCTA t0 t1 t2 t3 t4 t5 ACT NOP ACT NOP READ READ t6 t7 t8 t9 CK /CK Command Address Row0 Row1 NOP Column A Column B BA out out A0 A1 DQ EO Column = A Column = B Read Read Bank0 Dout out out out out B0 B1 B2 B3 Bank3 Dout DQS Bank0 Active Bank3 Active Bank0 Read CL = 2 BL = 4 Bank3 Read READ to READ Command Interval (different bank) L t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 29 ;;;;; EDD2516KCTA A Write command to the consecutive Write command Interval Destination row of the consecutive write command Bank address 1. Same 2. Same 3. Different Row address State Same ACTIVE Different — Any ACTIVE EO /CK Command BA NOP WRIT Row tn+1 tn+2 tn+4 tn+5 tn+6 NOP WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 Column = A Write DQS tn+3 Pr DQ tn L Address ACT The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank to interrupt the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A write command to the consecutive precharge interval’ section. The consecutive write can be performed after an interval of no less than 1 cycle to interrupt the preceding write operation. Precharge the bank without interrupting the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. IDLE t0 CK Operation Bank0 Active Column = B Write od BL = 4 Bank0 WRITE to WRITE Command Interval (same ROW address in the same bank) t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 30 ;;; ;;; EDD2516KCTA CK /CK Command Address BA DQ t0 t1 t2 ACT NOP ACT Row0 NOP WRIT tn+1 tn+2 tn+3 tn+4 tn+5 NOP WRIT Column A Column B inA0 inA1 inB0 inB1 inB2 inB3 EO DQS Row1 tn Bank0 Write Bank0 Active Bank3 Write Bank3 Active BL = 4 Bank0, 3 WRITE to WRITE Command Interval (different bank) L t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 31 EDD2516KCTA A Read command to the consecutive Write command interval with the BST command Destination row of the consecutive write command Bank address Row address State 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE Operation EO Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank to interrupt the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. See ‘A read command to the consecutive precharge interval’ section. Issue the BST command. tBSTW (≥ tBSTZ) after the BST command, the consecutive write command can be issued. Precharge the bank independently of the preceding read operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive write command can be issued. IDLE t0 t1 t2 t3 t4 READ BST NOP WRIT t5 t6 t7 t8 CK /CK Command NOP L tBSTW (≥ tBSTZ) DM DQ out0 out1 High-Z DQS Pr tBSTZ (= CL) in1 in2 in3 od OUTPUT in0 INPUT BL = 4 CL = 2 READ to WRITE Command Interval t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 32 EDD2516KCTA A Write command to the consecutive Read command interval: To complete the burst operation Destination row of the consecutive read command Bank address Row address State 1. Same Same ACTIVE 2. Same Different — 3. Different Any ACTIVE EO t0 Operation To complete the burst operation, the consecutive read command should be performed tWRD (= BL/ 2 + 2) after the write command. Precharge the bank tWPD after the preceding write command. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. See ‘A read command to the consecutive precharge interval’ section. To complete a burst operation, the consecutive read command should be performed tWRD (= BL/ 2 + 2) after the write command. Precharge the bank independently of the preceding write operation. tRP after the precharge command, issue the ACT command. tRCD after the ACT command, the consecutive read command can be issued. IDLE t1 t2 t3 t4 t5 t6 CK /CK Command L WRIT NOP READ NOP tWRD (min) tWTR* BL/2 + 2 cycle DM DQS Pr DQ in0 in1 in2 od INPUT out0 in3 out1 out2 OUTPUT Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. BL = 4 CL = 2 WRITE to READ Command Interval t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 33 EDD2516KCTA A Write command to the consecutive Read command interval: To interrupt the write operation Destination row of the consecutive read command Bank address Row address State Operation 1. Same Same ACTIVE DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. 2. Same Different — —*1 3. Different Any ACTIVE DM must be input 1 cycle prior to the read command input to prevent from being written invalid data. In case, the read command is input in the next cycle of the write command, DM is not necessary. IDLE —*1 EO Note: 1. Precharge must be preceded to read command. Therefore read command can not interrupt the write operation in this case. WRITE to READ Command Interval (Same bank, same ROW address) t0 t1 t2 t3 t4 t5 t6 t7 t8 CK /CK L Command WRIT READ 1 cycle NOP CL=2 DM DQS in0 Pr DQ in1 in2 High-Z od Data masked High-Z out0 out1 out2 out3 BL = 4 CL= 2 [WRITE to READ delay = 1 clock cycle] t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 34 EDD2516KCTA t0 t1 t2 WRIT NOP READ t3 t4 t5 t6 t7 t8 CK /CK Command 2 cycle NOP CL=2 DM EO DQ in0 in1 in2 High-Z out0 out1 out2 out3 in3 High-Z DQS /CK [WRITE to READ delay = 2 clock cycle] t1 t2 t3 t4 t5 t6 Pr Command BL = 4 CL= 2 L t0 CK Data masked WRIT NOP READ 3 cycle t7 t8 NOP CL=2 tWTR* DM in0 in1 in2 in3 DQS Data masked od DQ out0 out1 out2 out3 t uc Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR. BL = 4 CL= 2 [WRITE to READ delay = 3 clock cycle] Preliminary Data Sheet E0641E20 (Ver.2.0) 35 EDD2516KCTA A Read command to the consecutive Precharge command interval (same bank): To output all data To complete a burst read operation and get a burst length of data, the consecutive precharge command must be issued tRPD (= BL/ 2 cycles) after the read command is issued. t0 t1 t2 t3 READ NOP PRE/ PALL t4 t5 t6 t7 t8 CK /CK Command NOP DQ NOP out0 out1 out2 out3 DQS EO tRPD = BL/2 READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2, BL = 4) t0 t1 t2 t3 NOP READ NOP PRE/ PALL t4 t5 t6 t7 t8 CK /CK Command L DQ NOP out0 out1 out2 out3 DQS Pr tRPD = BL/2 READ to PRECHARGE Command Interval (same bank): To output all data (CL = 2.5, BL = 4) t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 36 EDD2516KCTA READ to PRECHARGE Command Interval (same bank): To stop output data A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become High-Z tHZP (= CL) after the precharge command. t0 t1 t2 t3 READ PRE/PALL t4 t5 t6 t7 t8 CK /CK Command NOP DQ NOP High-Z out0 out1 High-Z DQS EO tHZP READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2, BL = 2, 4, 8) t0 t1 t2 t3 t4 t5 t6 t7 t8 CK /CK DQ NOP READ PRE/PALL NOP CL = 2.5 High-Z out0 out1 High-Z Pr DQS L Command tHZP READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 2.5, BL = 2, 4, 8) t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 37 ;;;;;;; ;; ; EDD2516KCTA A Write command to the consecutive Precharge command interval (same bank) The minimum interval tWPD is necessary between the write command and the precharge command. t0 t1 t2 t3 t4 t5 t6 t7 CK /CK Command WRIT PRE/PALL NOP NOP tWPD tWR EO DM DQS DQ in0 in1 in2 in3 Last data input L WRITE to PRECHARGE Command Interval (same bank) (BL = 4) t0 CK /CK Command t1 t2 t3 t4 t5 PRE/PALL NOP od WRIT Pr Precharge Termination in Write Cycles During a burst write cycle without auto precharge, the burst write operation is terminated by a precharge command of the same bank. In order to write the last input data, tWR (min) must be satisfied. When the precharge command is issued, the invalid data must be masked by DM. t6 t7 NOP tWR DM DQ in0 in1 in2 t uc DQS in3 Data masked Precharge Termination in Write Cycles (same bank) (BL = 4) Preliminary Data Sheet E0641E20 (Ver.2.0) 38 EDD2516KCTA Bank active command interval Destination row of the consecutive ACT command Bank address Row address 1. Same Any ACTIVE 2. Different Any ACTIVE State Operation Two successive ACT commands can be issued at tRC interval. In between two successive ACT operations, precharge command should be executed. Precharge the bank. tRP after the precharge command, the consecutive ACT command can be issued. IDLE tRRD after an ACT command, the next ACT command can be issued. CK /CK EO Command Address ACTV ACT ACT ROW: 0 ROW: 1 Bank0 Active Bank3 Active NOP PRE NOP ACT NOP ROW: 0 BA L tRRD Bank0 Precharge Bank0 Active tRC Bank Active to Bank Active Pr Mode register set to Bank-active command interval The interval between setting the mode register and executing a bank-active command must be no less than tMRD. CK /CK Command MRS CODE Mode Register Set ACT NOP od Address NOP BS and ROW tMRD Bank3 Active t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 39 EDD2516KCTA DM Control DM can mask input data. In ×16 products, UDM and LDM can mask the upper and lower byte of input data, respectively. By setting DM to Low, data can be written. When DM is set to High, the corresponding data is not written, and the previous data is held. The latency between DM input and enabling/disabling mask function is 0. t1 t2 t3 t4 t5 t6 DQS DQ Mask Mask EO DM Write mask latency = 0 DM Control L t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 40 EDD2516KCTA SSR-Flag Function This function is to show that the memory is SSR. When MRS or EMRS command is issued, SF becomes high after tSSRFD delay and returns to low when tSSRFH is satisfied. If another MRS/EMRS command follows previous MRS/EMRS command with less than tSSRFH interval, SF stays high until tSSRFH for later MRS/EMRS command is satisfied. CK /CK Command NOP MRS or EMRS NOP NOP NOP NOP NOP tSSRFD EO SF tSSRFH CK /CK Command NOP MRS NOP NOP NOP NOP tMRD tSSRFD L SF EMRS tSSRFH-1 tSSRFH-2 Pr SSR Identification Flag Function SSR Re-Entry during “Exiting SSR” State When SSR command is issued during “Exiting SSR” state, SF is driven low after tFRD delay. od CK /CK tFRD CKE Command SSR NOP SSRX NOP SSR tFDSSR SF Preliminary Data Sheet E0641E20 (Ver.2.0) 41 NOP t uc tFHSSR NOP ;;;;;; EDD2516KCTA Timing Waveforms Command and Addresses Input Timing Definition CK /CK tIS Command (/RAS, /CAS, /WE, /CS) tIH VREF tIS tIH VREF Address Read Timing Definition EO /CK CK DQS tCL tCH tDQSCK tDQSCK tDQSCK tDQSCK tRPST tRPRE tDQSQ tLZ L DQ (Dout) tCK tAC tDQSQ tQH tAC tAC tQH tHZ tDQSQ tDQSQ tQH tQH Write Timing Definition tCK tDQSS DQS tWPRES Pr /CK CK tDSS tDQSL tWPRE tDS DM tDS tDH tDH tDSS VREF tDQSH tWPST od DQ (Din) tDSH VREF tDIPW tDIPW VREF tDIPW t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 42 EDD2516KCTA Read Cycle ; ; ; ; ; ;;; ; tCK tCH tCL CK /CK tRC VIH CKE tRAS tRCD tRP tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH /CS /RAS EO /CAS /WE BA ; ;; ;; ; ; L A10 tIS tIH tIS tIH tIS tIH Address DQS DQ (output) High-Z High-Z Pr DM Bank 0 Read tRPST od Bank 0 Active tRPRE Bank 0 Precharge CL = 2 BL = 4 Bank0 Access = VIH or VIL t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 43 ; ; ;;;;; ; EDD2516KCTA Write Cycle tCK tCH tCL CK /CK tRC VIH CKE tRAS tRP tRCD tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH tIS tIH /CS /RAS EO /CAS /WE BA Address L A10 tIS tIH tDQSS tDQSL tWPST Pr DQS (input) tDQSH tDS tDS DM tDS tDH tDH od DQ (input) tWR tDH Bank 0 Active Bank 0 Write Bank 0 Precharge CL = 2 BL = 4 Bank0 Access = VIH or VIL t uc Preliminary Data Sheet E0641E20 (Ver.2.0) 44 EDD2516KCTA Mode Register Set Cycle (SSR-Flag Function) /CK CK CKE VIH /CS /RAS /CAS /WE EO BA Address code C: b R: b code valid DM High-Z DQS High-Z b DQ (output) L SF tRP Read/Write Cycle /CK CK CKE VIH tSSRFH MRS or EMRS command /RAS /CAS /WE BA R:a C:a R:b C:b DQS a DQ (output) C:b'' b’’ High-Z b tRWD Bank 0 Active CL = 2 BL = 4 = VIH or VIL t uc DM DQ (input) Bank 3 Precharge od /CS Address Bank 3 Read Bank 3 Active Pr Precharge If needed tSSRFD tWRD Bank 3 Write Bank 0 Bank 3 Read Active Preliminary Data Sheet E0641E20 (Ver.2.0) 45 Bank 3 Read Read cycle CL = 2 BL = 4 =VIH or VIL EDD2516KCTA Auto Refresh Cycle /CK CK CKE VIH /CS /RAS /CAS /WE EO BA Address A10=1 R: b C: b DM DQS b DQ (output) L DQ (input) High-Z tRP Precharge If needed tRFC Auto Refresh Bank 0 Active Bank 0 Read t uc od Pr CL = 2 BL = 4 = VIH or VIL Preliminary Data Sheet E0641E20 (Ver.2.0) 46 EDD2516KCTA Super Self-Refresh Cycle SSR Exit-Flag Function: When the error correction is successful. /CK CK tIS tIH CKE CKE = low /CS /RAS /CAS EO /WE BA Address DQS R: b L DM A10=1 High-Z High-Z DQ (output) High-Z SF tRP Precharge If needed Pr DQ (input) tSSRENT tSSREX tFDSSR tFHSSR SSRX command SSR command Auto Refresh Auto Refresh Bank 0 Active t uc od = VIH or VIL Preliminary Data Sheet E0641E20 (Ver.2.0) 47 EDD2516KCTA SSR Uncorrectable-Flag Function: When the error correction fails. /CK CK tIS tIH CKE CKE = low /CS /RAS /CAS /WE BA EO code Address A10=1 code DM DQS High-Z High-Z DQ (output) High-Z DQ (input) L SF tRP Precharge If needed tSSREX tFDSSR tFHSSR tSSRENT SSR command SSRX command Auto Refresh tSSRFH Auto Refresh MRS/EMRS command Pr SSR Uncorrectable flag reset = VIH or VIL t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 48 EDD2516KCTA Package Drawing 66-pin Plastic TSOP (II) Solder plating: Lead free (Sn-Bi) Unit: mm 22.22 ± 0.10 *1 A EO PIN#1 ID 1 0.17 to 0.32 11.76 ± 0.20 34 10.16 66 33 0.65 B 0.13 M S A B 0.80 Nom 0.10 +0.08 −0.05 0.09 to 0.20 0.10 S 1.20 max S 0.25 0 to 8° L 1.0 ± 0.05 0.91 max. 0.60 ± 0.15 Pr Note: This dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.20mm per side. ECA-TS2-0029-01 t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 49 EDD2516KCTA Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the EDD2516KCTA. Type of Surface Mount Device EDD2516KCTA: 66-pin Plastic TSOP (II) < Lead free (Sn-Bi) > L EO t uc od Pr Preliminary Data Sheet E0641E20 (Ver.2.0) 50 EDD2516KCTA NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. EO 2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. L 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Pr Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. CME0107 t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 51 EDD2516KCTA The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. EO [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. L [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. Pr If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. M01E0107 t uc od Preliminary Data Sheet E0641E20 (Ver.2.0) 52