STMICROELECTRONICS TDA8133_09

TDA8133
+5.1 V and +8 V dual voltage regulator with
disable and reset functions
Features
■
Input voltage range: 7 V to 18 V
■
Output currents up to 750 mA
■
Fixed precision output 1 voltage: 5.1 V ±2%
■
Fixed precision output 2 voltage: 8 V ±2%
■
Output 1 with reset function
■
Output 2 with disable function by TTL Input
■
Short-circuit protection at both outputs
■
Thermal protection
■
Low dropout voltage
SIP9 (plastic package)
DIP16 (8 + 8)
Table 1.
Description
Device summary
Order code
An internal reset circuit generates a reset pulse
when the voltage of output 1 drops below the
regulated voltage value.
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TDA8133
The TDA8133 and the TDA8133D are monolithic
dual positive voltage regulators designed to
provide fixed precision output voltages of 5.1 V
and 8.0 V for currents up to 750 mA.
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TDA8133D
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Packaging
Tray
Tray
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Output 2 can be disabled via the TTL input.
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Short-circuit and thermal protections are included
in all versions.
Figure 1.
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TDA8133 and TDA8133D
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9
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7
6
5
4
3
2
1
INPUT1
1
16
GROUND
OUTPUT1
INPUT2
OUTPUT2
DELAY CAPACITOR
NTBC
DISABLE
RESET
GROUND
RESET
DISABLE
NTBC
DELAY CAPACITOR
OUTPUT2
INPUT2
INPUT1
OUTPUT1
2
15
GROUND
3
14
GROUND
4
13
GROUND
5
12
GROUND
6
11
GROUND
7
10
GROUND
8
9
GROUND
Tab is connected to GROUND
March 2009
Rev 2
1/14
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1
Contents
TDA8133
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3
Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4
Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
Power dissipation and layout indications . . . . . . . . . . . . . . . . . . . . . . . . 9
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.1
7
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Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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Environmentally-friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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TDA8133
1
Description
Description
Figure 2.
TDA8133 block diagram
DELAY CAPACITOR
3
6
RESET
Reference
INPUT1
1
9 OUTPUT1
Regulator 1
Protection
INPUT2
2
DISABLE
4
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7 NTBC
5
GROUND
Figure 3.
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8 OUTPUT2
Regulator 2
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TDA8133D block diagram
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NTBC: Not to be Connected
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DELAY CAPACITOR
3
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Reference
INPUT1
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INPUT2
2
DISABLE
4
5
RESET
8 OUTPUT1
Regulator 1
Protection
Regulator 2
7 OUTPUT2
6 NTBC
Pins 9 to 16
GROUND
NTBC: Not to be Connected
3/14
Electrical characteristics
2
TDA8133
Electrical characteristics
Table 2.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VIN
DC input voltage at pins INPUT1 and INPUT2
20
V
VDIS
Disable input voltage at pin DISABLE
20
V
VRST
Output voltage at pin RESET
20
V
IO1,2
Output currents
Internally limited
Pt
Power dissipation
Internally limited
TSTG
Storage temperature
-65 to +150
°C
TJ
Junction temperature
0 to +150
°C
Table 3.
Thermal data
Symbol
Parameter
uc
Value
od
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Unit
RthJC
Thermal resistance
(junction-to-case)
TDA8133 9
TDA8133D 15
RthJA
Thermal resistance (1)
(junction-to-ambient)
TDA8133 50
TDA8133D 56
TJ
Maximum recommended junction temperature
140
°C
TOPER
Operating free air temperature range
0 to +70
°C
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°C/W
°C/W
1. Mounted on board. For more information, refer to Section 5.
Table 4.
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Electrical characteristics
Symbol
Parameter
VO1
Output voltage
VO2
Output voltage
VIO1,2
Dropout voltage
Test Conditions
du
Min.
Typ.
Max.
Unit
IO1 = 10 mA
5
5.1
5.2
V
IO2 = 10 mA
7.84
8.00
8.16
V
IO1,2 = 750 mA
1.4
V
Line regulation
7 V < VIN1 < 14 V
10 V < VIN2 < 14 V
IO1,2 = 200 mA
50
80
mV
VO1,2LO
Load regulation
5 mA < IO1 < 600 mA
5 mA < IO2 < 600 mA
100
160
mV
IQ
Quiescent current
IO1 = 10 mA, OUTPUT2
Disabled
2
mA
VO1RST
Reset threshold voltage
K = VO1, VIN1 ≥ 7 V
K - 0.4
K - 0.25
K - 0.1
V
VRTH
Reset threshold hysteresis
See circuit description
20
50
75
mV
tRD
Reset pulse delay
Ce = 100 nF
See circuit description
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25
ms
TDA8133
Table 4.
Electrical characteristics
Electrical characteristics (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VRL
Saturation voltage in reset
condition
IRESET = 5 mA
0.4
V
IRH
Leakage current in normal
condition
VRESET= 10 V
10
µA
Output voltage thermal drift
KO1, 2
ΔV 0 ⋅ 10 6
K 0 = -------------------------ΔT ⋅ V0
100
ppm/°C
TJ = 0 to + 125°C
VIN1 = 7 V, VIN2 = 10 V
VIN1,2 = 16 V(1)
IO1,2SC
Short circuit output current
VDISH
Disable voltage when pin DISABLE is high (OUTPUT2
active)
VDISL
Disable voltage when pin DISABLE is low (OUTPUT2
disabled)
IDIS
Disable bias current
TJSD
Junction temperature for thermal shutdown
0 V < VDIS < 7 V
1.6
1.0
A
2
V
0.8
-100
2
V
145
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µA
°C
1. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power
occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is
only guaranteed for input voltages up to 16 V.
P
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let
Note:
TAMB = 25° C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified.
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Circuit description
3
TDA8133
Circuit description
The TDA8133 and the TDA8133D are dual-voltage regulators with reset and disable
functions.
The two regulation parts are supplied from a single voltage reference circuit trimmed by
zener zapping during EWS testing. Since the supply voltage of this voltage reference is
connected to pin INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not
supplied.
The output stages are designed using a Darlington configuration with a typical dropout
voltage of 1.2 V.
The disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin
DISABLE.
The reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VO1 0.25 V (4.85 V Typ.), the "a" comparator (Figure 4) rapidly discharges the external capacitor
(Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1
exceeds VO1 - 0.2 V (4.9 V Typ.), the VCe voltage increases linearly to the reference voltage
(VREF = 2.5 V) corresponding to a reset pulse delay (tRD) as shown in Figure 5.
C e × 2.5V
t RD = -------------------------10μA
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Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second
comparator "b" has a large hysteresis (1.9 V).
Figure 4.
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Reset diagram
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10 µA
VREF
OUTPUT1
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VREF = 2.5 V
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Ce
VREF
0.6V
b
RESET
TDA8133
Figure 5.
Circuit description
Internal reset diagram
VO1
K
VO1RST
VRTH
RESET
K = Actual Value of VO1
tRD
Power On
tRD
Power Off
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Application diagrams
4
TDA8133
Application diagrams
Figure 6.
TDA8133 typical application
RESET
0.1 µF
Ce
6
3
DELAY
CAPACITOR
RESET
VIN1
1 INPUT1
OUTPUT1 9
VO1
VIN2
2 INPUT2
OUTPUT2 8
VO2
C1
C2
GROUND
5
DISABLE
4
NTBC
7
C3
C4
DISABLE
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C1 to C4 = 10 µF
Figure 7.
TDA8133D typical application
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RESET
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5
RESET
VIN1
VIN2
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C1 to C4 = 10 µF
C2
Ce
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0.1 µF
3
DELAY
CAPACITOR
1 INPUT1
OUTPUT1 8
VO1
2 INPUT2
OUTPUT2 7
VO2
GROUND
NTBC
6
DISABLE
4
Pins 9 to 16
DISABLE
C3
C4
TDA8133
5
Power dissipation and layout indications
Power dissipation and layout indications
The power is mainly dissipated by the two device buffers. It can be calculated by the
equation:
P = (VIN1-VO1) x IO1 + (VIN2-VO2) x IO2
The following table lists the different RthJA values of these packages with or without a heat
sink and the corresponding maximum power dissipation assuming:
●
Maximum ambient temperature = 70° C
●
Maximum junction temperature = 140° C
Table 5.
Power dissipation
Device
Heat Sink
RthJA in °C/W
PMAX in W
No
50
1.4
Yes
20
3.5
No
56 to 40
1.25 to 1.75
Yes
32
2.2
TDA8133
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TDA8133D
Figure 8.
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Thermal resistance (junction-to-ambient) for DIP16 package without heatsink
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To optimize the thermal conductivity of the copper
layer and the exchanges with the air, the solder
must cover the maximum amount of this area
60
RthJA °C/W
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Test board with
“on board” square heat sink area
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45
40
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6
0
2
4
8
10
12
Copper area (cm²) (35 µm plus solder) board is face-down
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Figure 9.
Metal plate mounted near the TDA8133D for heatsinking
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Top View
Bottom View
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Package mechanical data
6
TDA8133
Package mechanical data
Figure 10. 9-pin plastic single in-line package
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Table 6.
mm
Min.
Typ.
(s)
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b3
C
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c2
Max.
Min.
Inches
Typ.
7.1
3
0.106
0.118
0.976
0.020
0.033
0.063
3.3
0.130
0.43
0.017
1.32
0.052
21.2
0.835
d1
14.5
0.571
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2.54
0.100
e3
20.32
0.800
3.1
Max.
0.280
24.8
1.6
D
L
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0.5
0.85
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2.7
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9-pin plastic single in-line package dimensions
Dim.
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1.122
L1
3
0.116
L2
17.6
0.693
TDA8133
Package mechanical data
Table 6.
9-pin plastic single in-line package dimensions (continued)
mm
Inches
Dim.
Min.
Typ.
Max.
L3
Min.
Typ.
0.25
Max.
0.010
M
3.2
0.126
N
1
0.039
Figure 11. 16-pin plastic dual in-line package, 300 mil width
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Table 7.
(s)
mm
ct
Min.
Typ.
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A
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A1
0.38
A2
2.92
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b2
bs
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Inches
Max.
Typ.
16-pin plastic dual in-line package dimensions
Dim.
b
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3.30
0.36
5.33
Max.
0.210
0.015
4.95
0.115
0.56
0.014
1.52
1.78
0.20
0.25
0.36
18.67
19.18
19.69
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Min.
0.130
0.195
0.022
0.060
0.070
0.008
0.010
0.014
0.735
0.755
0.775
2.54
0.100
E1
6.10
6.35
7.11
0.240
0.250
0.280
L
2.92
3.30
3.81
0.115
0.130
0.150
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Package mechanical data
6.1
TDA8133
Environmentally-friendly packages
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance.
ECOPACK specifications, grade definitions and product status are available at: www.st.com.
ECOPACK is an ST trademark.
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7
Revision history
Revision history
Table 8.
Document revision history
Date
Revision
Changes
March 1994
1.0
First issue
July 2001
1.1
Datasheet update and addition of DIP16 package
August 2001
1.2
General update; DISABLE pin renamed DISABLE (function remains
unchanged)
September
2001
1.3
Thermal data updated
October 2001
1.4
Thermal data updated. Figure 2 and Figure 3 updated
05-Mar-2009
2
Preliminary banner removed, template updated and Section 6.1
added
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TDA8133
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