STV8162 +5 V, +5 V and +8 V triple voltage regulator with disable and reset functions Features Figure 1. ■ Input voltage range between 7 V and 18 V ■ Output currents up to 600 mA ■ Fixed precision output 1 voltage of 5 V ± 2% ■ Fixed precision output 2 voltage of 5 V ± 2% ■ Fixed precision output 3 voltage of 8 V ± 2% ■ Output 1 with reset facility ■ Outputs 2 and 3 can be disabled by digital input ■ Short circuit protection on each output ■ Thermal protection ■ Low dropout voltages STV8162 and STV8162D Clipwatt 11 c u d Description e t le ) s t( o r P Power DIP18 (9 + 9) The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of output 1 drops below the regulated voltage value. ) s ( ct o s b O Table 1. Device summary Order code Packaging STV8162 Tray STV8162D Tray Outputs 2 and 3 can be disabled by a digital input. u d o Short-circuit and thermal protections are included in all versions. r P e t e l o GROUND 10 9 DISABLE GROUND 11 8 INPUT3 GROUND 12 7 OUTPUT3 GROUND 13 6 INPUT2 GROUND 14 5 OUTPUT2 GROUND 15 4 INPUT1 GROUND bs O 16 3 OUTPUT1 GROUND 17 2 DELAY CAPACITOR GROUND 18 1 RESET March 2009 Top View Rev 2 11 10 9 8 7 6 5 4 3 2 1 NC DISABLE INPUT3 OUTPUT3 INPUT2 GROUND OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET 1/14 www.st.com 1 Contents STV8162 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 Application diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 Power dissipation and layout indications . . . . . . . . . . . . . . . . . . . . . . . . 9 6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.1 7 c u d Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 e t le ) s ( ct u d o r P e t e l o s b O 2/14 ) s t( Environmentally-friendly packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 o s b O - o r P STV8162 1 Description Description Figure 2. STV8162 block diagram DELAY CAPACITOR 2 1 RESET 3 OUTPUT1 5 OUTPUT2 Reference INPUT1 4 Regulator 1 Protections INPUT2 INPUT3 7 Regulator 2 9 DISABLE 10 o r P 11 Not Connected 6 e t le GROUND Figure 3. c u d OUTPUT3 8 Regulator 3 ) s t( o s b O - STV8162D block diagram DELAY CAPACITOR 2 (s) t c u 1 RESET 3 OUTPUT1 5 OUTPUT2 7 OUTPUT3 Reference od INPUT1 4 r P e s b O t e l o INPUT2 6 INPUT3 8 Regulator 1 Protections Regulator 2 Regulator 3 DISABLE 9 GROUND Pins 10 to 18 3/14 Electrical characteristics 2 STV8162 Electrical characteristics Table 2. Absolute maximum ratings Symbol Parameter Value Unit VIN DC input voltage at pins INPUT1, INPUT2 and INPUT3 20 V VDIS Disable input voltage at pin DISABLE 20 V VRST Output voltage at pin RESET 20 V IOUTPUT Output currents Internally limited Pt Power dissipation Internally limited TSTG Storage temperature -65 to +150 °C TJ Junction temperature 0 to +150 °C Table 3. Thermal data Symbol Parameter uc Value RthJC Junction-to-case thermal resistance STV8162 STV8162D RthJA Junction-to-ambient thermal resistance (1) STV8162 STV8162D TJ Maximum recommended junction temperature TOPER Operating free air temperature range 3 15 r P e t le ≥10 56 ) s t( od °C 0 to +70 b O - °C/W °C/W 140 so Unit °C 1. Mounted on board. For more information, refer to Section 5. Table 4. ) s ( ct Electrical characteristics Symbol du Parameter o r P e VOUT1 Output voltage VOUT2 Output voltage VOUT3 Test conditions Min. Typ. Max. Unit IOUT1 = 10 mA 4.90 5.00 5.10 V IOUT2 = 10 mA 4.90 5.00 5.10 V Output voltage IOUT3 = 10 mA 7.84 8.00 8.16 V Output voltage 4.80 5.20 V s b O 7 V < VIN1 < 12 V 5 mA < IOUT1 < 600 mA Output voltage 7 V < VIN2 < 12 V 5 mA < IOUT2 < 600 mA 4.80 5.20 V VOUT3 Output voltage 10 V < VIN3 < 15 V 5 mA < IOUT3 < 600 mA 7.68 8.32 V VIO1 Dropout voltage IOUT1 = 0.6 A 1 1.4 V VIO2 Dropout voltage IOUT2 = 0.6 A 1 1.4 V VIO3 Dropout voltage IOUT3 = 0.6 A 1 1.4 V t e l o VOUT1 VOUT2 4/14 STV8162 Table 4. Electrical characteristics Electrical characteristics (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit VOUT1LI Line regulation 7 V < VIN1 < 12 V, IOUT1 = 200 mA 50 mV VOUT2LI Line regulation 7 V < VIN2 < 12 V, IOUT2 = 200 mA 50 mV VOUT3LI Line regulation 10 V < VIN3 < 15 V, IOUT3 = 200 mA 80 mV VOUT1LO Load regulation 5 mA < IOUT1 < 600 mA 100 mV VOUT2LO Load regulation 5 mA < IOUT2 < 600 mA 100 mV VOUT3LO Load regulation 5 mA < IOUT3 < 600 mA 160 mV IQ Quiescent current IOUT1 = 10 mA Outputs 2 and 3 disabled 2.2 3.0 mA VO1RST Reset threshold voltage K = VOUT1 K-0.4 K-0.25 K-0.10 V VRTH Reset threshold hysteresis See circuit description. 30 75 120 tRD Reset pulse delay Ce = 100 nF See circuit description. VRL Saturation voltage in reset condition IRESET = 5 mA IRH Leakage current in normal condition, at RESET pin VRESET = 10 V KOUT1 KOUT2 KOUT3 Output voltage thermal drift IOUT1SC Short circuit output current VIN1 = 7 V IOUT2SC Short circuit output current IOUT3SC Short circuit output current VDISH Voltage high level at DISABLE pin (Outputs 2 and 3 active) VDISL Voltage low level at DISABLE pin (Outputs 2 and 3 disabled) IDIS Bias current at DISABLE pin TJSD Junction temperature for thermal shutdown TSDH t e l o r P e ms 0.4 V 10 μA ppm/° C 100 0.8 1.3 1.8 A VIN1 = 7 V 0.8 1.3 1.8 A VIN3 = 10 V 0.8 1.3 1.8 A ) s ( ct u d o b O - d o r P e let so TJ = 0 to 125°C 6 ΔV OUT ⋅ 10 K OUT = ---------------------------------ΔT ⋅ V OUT uc 25 ) s t( mV 0 V < VDISABLE < 7 V Thermal shutdown temperature hysteresis 2 V -100 0.8 V 2 μA 150 °C 15 °C s b O 5/14 Circuit description 3 STV8162 Circuit description The STV8162 and STV8162D are triple-voltage regulators with reset and disable functions. The three regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second and third regulators will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.0 V. In all applications, all three inputs must be polarized. If outputs 2 or 3 are not used, the corresponding inputs must be connected to Input 1. The disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is applied to pin DISABLE. The reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1-0.25 V (4.75 V Typ.), the "a" comparator (Figure 4) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VOUT1-0.175 V (4.825 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a reset pulse delay (tRD)as shown in Figure 5. C e × 2.5V t RD = -------------------------10μA e t le c u d ) s t( o r P Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V). ) s ( ct u d o r P e t e l o s b O 6/14 o s b O - STV8162 4 Application diagrams Application diagrams Figure 4. Reset diagram 10 µA VREF OUTPUT1 + a - + RESET b 3 REG Ce VREF 0.6V VREF = 2.5 V Figure 5. Internal reset diagram VOUT1 K VO1RST c u d VRTH e t le RESET K = Actual Value of VOUT1 Figure 6. o r P tRD Power Off b O - STV8162 typical application ) s ( ct C1 to C6 = 10 µF u d o Ce 1 RESET r P e 0.1 µF 2 DELAY CAPACITOR VIN1 4 INPUT1 OUTPUT1 3 VOUT1 VIN2 7 INPUT2 OUTPUT2 5 VOUT2 VIN3 9 INPUT3 OUTPUT3 8 VOUT3 t e l o s b O so Power On tRD ) s t( C1 C2 C3 GROUND DISABLE 6 10 NC 11 C4 C5 C6 7/14 Application diagrams Figure 7. STV8162 STV8162D typical application C1 to C6 = 10 µF 0.1 µF Ce 1 RESET 2 DELAY CAPACITOR VIN1 4 INPUT1 OUTPUT1 3 VOUT1 VIN2 6 INPUT2 OUTPUT2 5 VOUT2 VIN3 8 INPUT3 OUTPUT3 7 VOUT3 C2 C1 C3 C4 GROUND DISABLE 9 Pins 10 to 18 C5 c u d e t le ) s ( ct u d o r P e t e l o s b O 8/14 o s b O - o r P C6 ) s t( STV8162 5 Power dissipation and layout indications Power dissipation and layout indications The power is mainly dissipated by the three device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 + (VIN3-VOUT3) x IOUT3 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: ● Maximum ambient temperature = 70° C ● Maximum junction temperature = 140° C Table 5. Power dissipation Device Heat Sink RthJA in °C/W PMAX in W No 50 1.4 Yes 15 4.6 No 56 to 40 1.25 to 1.75 Yes 32 2.2 STV8162 c u d STV8162D Figure 8. o r P Thermal resistance (junction-to-ambient) of DIP18 package without heatsink e t le To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. 60 RthJA °C/W ) s t( 55 o s b O - Test Board with “On Board” square heat sink area. 50 ) s ( ct 45 40 u d o 6 0 2 4 8 10 12 Copper area (cm²) (35 µm plus solder) Board is face-down r P e t e l o Figure 9. Metal plate mounted near STV8162D for heatsinking s b O Top View Bottom View 9/14 Package mechanical data 6 STV8162 Package mechanical data Figure 10. 11-pin plastic Clipwatt package H3 C A D L B L1 L2 H1 c u d E ro F P e let G1 M1 M Table 6. Dim. Min. Typ. A B C o r P e E t e l o F G bs O Typ. 0.126 1.05 0.041 0.006 1.50 0.059 0.55 1.70 0.019 0.91 0.031 1.83 0.062 0.002 0.036 0.067 0.480 H2 18.60 0.732 19.85 17.90 0.700 L1 14.45 0.569 L3 0.072 0.781 L 10.70 Max. 3.20 0.15 0.80 1.57 Min. 12.00 L2 10/14 0.49 c u d (t s) Max. Inches H1 H3 G 11-pin plastic Clipwatt package dimensions mm D o s b O - ) s t( 11.00 5.50 11.20 0.421 0.433 0.217 0.441 STV8162 Package mechanical data Table 6. 11-pin plastic Clipwatt package dimensions (continued) mm Inches Dim. Min. Typ. Max. Min. Typ. M 2.54 0.100 M1 2.54 0.100 Max. Number of pins N 11 Figure 11. 18-pin plastic dual in-line power package E A2 A A1 L b2 b c u d e eB D1 b3 e t le D 18 o r P 10 (s) 1 E1 9 t c u d o r P e Table 7. o s b O - ) s t( c 18-pin pastic dual in-line power package dimensions mm Inches Dim. A1 0.38 A2 2.92 3.30 4.95 0.115 0.130 0.195 b 0.36 0.46 0.56 0.014 0.018 0.022 b2 1.14 1.52 1.78 0.045 0.060 0.070 b3 0.76 0.99 1.14 0.030 0.039 0.045 c 0.20 0.25 0.36 0.008 0.010 0.014 D 22.35 22.86 23.37 0.880 0.900 0.920 s b O t e l o Min. Typ. A Max. Min. Typ. 5.33 Max. 0.210 0.015 11/14 Package mechanical data Table 7. STV8162 18-pin pastic dual in-line power package dimensions (continued) mm Inches Dim. Min. D1 Typ. 0.13 Min. Typ. Max. 0.005 e 2.54 eB 6.1 Max. 0.100 10.92 0.430 E 7.62 7.87 8.26 0.300 0.310 0.325 E1 6.10 6.35 7.11 0.240 0.250 0.280 L 2.92 3.30 3.81 0.115 0.130 0.150 Environmentally-friendly packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. c u d ) s t( ECOPACK specifications, grade definitions and product status are available at: www.st.com. ECOPACK is an ST trademark. e t le ) s ( ct u d o r P e t e l o s b O 12/14 o s b O - o r P STV8162 7 Revision history Revision history Table 8. Document revision history Date Revision Changes January 2000 0.2 Initial release. November 2002 0.3 Addition of PDIP18 pakage 04-Mar-2009 2.0 New template applied, Section 6.1 added c u d e t le ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 13/14 STV8162 Please Read Carefully: Information in this document is provided solely in connection with ST products. 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