STV8130AD ® ADJUSTABLE AND +3.3 V DUAL VOLTAGE REGULATOR WITH DISABLE AND RESET FUNCTIONS PRELIMINARY DATA FEATURES ■ Input Voltage Range: 5 V to 18 V ■ Output Currents up to 750 mA ■ Fixed Precision Output 1 Voltage: 3.3 V ±2% ■ Adjustable Output 2 Voltage: 2.8 to 16 V ■ Output 1 with Reset Function ■ Output 2 with Disable Function by TTL Input ■ Short-circuit Protection at both Outputs ■ Thermal Protection SIP9 (Plastic Package) ORDER CODE: STV8130A# ■ Low Dropout Voltage DESCRIPTION The STV8130A# and STV8130D# are monolithic dual positive voltage regulators designed to provide a fixed precision output voltage of 3.3 V and an adjustable voltage between 2.8 and 16 V for currents up to 750 mA. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. DIP16 (8 + 8) ORDER CODE: STV8130D# Output 2 can be disabled via the TTL input. Short-circuit and thermal protections are included. 9 8 7 6 5 4 3 2 1 INPUT1 OUTPUT1 OUTPUT2 INPUT2 PROGRAM DELAY CAPACITOR RESET DISABLE GROUND DISABLE RESET DELAY CAPACITOR PROGRAM INPUT2 OUTPUT2 INPUT1 OUTPUT1 1 16 GROUND 2 15 GROUND 3 14 GROUND 4 13 GROUND 5 12 GROUND 6 11 GROUND 7 10 GROUND 8 9 GROUND Tab is connected to GROUND September 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/12 STV8130AD TABLE OF CONTENTS Chapter 1 GENERAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Chapter 2 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Absolute Maximum Ratings ................................................................................................ 4 2.2 Thermal Data ...................................................................................................................... 4 2.3 Electrical Characteristics ...................................................................................................... 4 Chapter 3 CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Chapter 4 APPLICATION DIAGRAMS Chapter 5 POWER DISSIPATION AND LAYOUT INDICATIONS . . . . . . . . . . . . . . . . . . . . . .8 Chapter 6 PACKAGE MECHANICAL DATA Chapter 7 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2/12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 STV8130AD 1 GENERAL INFORMATION GENERAL INFORMATION Figure 1: STV8130A# Block Diagram DELAY CAPACITOR 3 6 RESET 9 OUTPUT1 8 OUTPUT2 Reference 1 INPUT1 Regulator 1 Protection INPUT2 2 DISABLE 4 Regulator 2 7 PROGRAM 5 GROUND Figure 2: STV8130D# Block Diagram DELAY CAPACITOR 3 5 RESET 8 OUTPUT1 7 OUTPUT2 Reference INPUT1 1 Regulator 1 Protection INPUT2 2 DISABLE 4 Regulator 2 6 PROGRAM Pins 9 to 16 GROUND 3/12 ELECTRICAL CHARACTERISTICS STV8130AD 2 ELECTRICAL CHARACTERISTICS 2.1 Absolute Maximum Ratings Symbol Parameter Value Unit VIN DC Input Voltage at pins INPUT1 and INPUT2 20 V VDIS Disable Input Voltage at pin DISABLE 20 V VRST Output Voltage at pin RESET 20 V IOUT1,2 Pt Output Currents Internally Limited Power Dissipation Internally Limited TSTG Storage Temperature -65 to +150 °C TJ Junction Temperature 0 to +150 °C Value Unit 2.2 Thermal Data Symbol Parameter RthJC Thermal Resistance (Junction-to-Case) STV8130A# STV8130D# 9 15 °C/W RthJA Thermal Resistance 1 (Junction-to-Ambient) STV8130A# STV8130D# 50 56 °C/W 140 °C 0 to +70 °C TJ Maximum Recommended Junction Temperature TOPER Operating Free Air Temperature Range 1. Mounted on board. For more information, refer to Section 5. 2.3 Electrical Characteristics TAMB = 25° C, VIN1 = 7 V, VIN2 = 10 V, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. Unit 3.30 3.37 V 16.0 V VOUT1 Output Voltage IOUT1 = 10 mA 3.23 VOUT2 Output Voltage IOUT2 = 10 mA 2.8 VIO1,2 Dropout Voltage IOUT1,2 = 750 mA 1.4 V VO1,2LI Line Regulation 6 V < VIN1 < 12 V 12 V < VIN2 < 18 V IOUT1,2 = 200 mA 50 100 mV VO1,2LO Load Regulation 5 mA < IOUT1 < 600 mA 5 mA < IOUT2 < 600 mA 100 200 4/12 mV STV8130AD Symbol ELECTRICAL CHARACTERISTICS Parameter Test Conditions Min. Typ. Max. Unit 2 mA Quiescent Current IOUT1 = 10 mA, OUTPUT2 Disabled Reset Threshold Voltage1 K = VOUT1, IOUT1 ≥ 50 mA Reset Threshold Hysteresis See circuit description. tRD Reset Pulse Delay Ce = 100 nF See circuit description. VRL Saturation Voltage in Reset Condition IRESET = 5 mA 0.4 V IRH Leakage Current in Normal Condition VRESET = 10 V 10 µA IQ VO1RST VRTH KOUT1, 2 K - 0.4 K - 0.25 K - 0.1 V 20 50 75 mV 25 ∆V 0 ⋅ 10 6 K 0 = -----------------------∆T ⋅ V 0 Output Voltage Thermal Drift ms 100 ppm/°C TJ = 0 to + 125°C IOUT1,2SC Short Circuit Output Current VIN1 = 7 V, VIN2 = 10 V VIN1,2 = 16 V2 VDISH Disable Voltage when pin DISABLE is High (OUTPUT2 active) VDISL Disable Voltage when pin DISABLE is Low (OUTPUT2 disabled) IDIS Disable Bias Current 0 V < VDIS < 7 V 1.6 1.0 2 A V -100 0.8 V 2 µA VREF Reference Voltage at PROGRAM Pin 2.44 V TJSD Junction Temperature for Thermal Shutdown 145 °C 1. This reset signal is activated by a decrease of VOUT1 voltage which can be due to an overload of pin OUT1 or by a lack of Input Voltage (VIN1). 2. The output short-circuit currents are tested one channel at time. During a short-circuit, a large consumption of power occurs, but the thermal protection circuit prevents any excessive temperatures. A safe permanent short-circuit protection is only guaranteed for input voltages up to 16 V. 5/12 CIRCUIT DESCRIPTION 3 STV8130AD CIRCUIT DESCRIPTION The STV8130A# and STV8130D# are dual-voltage regulators with Reset and Disable functions. The two regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second regulator will not work if pin INPUT1 is not supplied. The adjustable voltage of pin OUTPUT2 (VOUT2) is defined by output bridge resistors (R1, R2): the values of these resistors are calculated to obtain, with the targetted value for VOUT2, the reference voltage (VREF = 2.44 V) on the median point connected to pin PROGRAM. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.2 V. The Disable circuit will switch off pin OUTPUT2 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1 - 0.25 V (3.05 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. This drop can be caused by a parasitic loading condition on pin OUTPUT1 or by a too low value of VIN (short powering off). When the voltage at pin OUTPUT1 exceeds VOUT1 - 0.2 V (3.1 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.44 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4. C e × 2.44V t RD = ----------------------------10µA Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.84 V). Figure 3: Reset Diagram 10 µA VREF OUTPUT1 + a - 50 + b RESET 3 REG Ce VREF = 2.44 V VREF 0.6V Figure 4: Internal Reset Voltages VOUT1 K VO1RST VRTH RESET K = Actual Value of VOUT1 6/12 Power On tRD tRD Power Off STV8130AD APPLICATION DIAGRAMS Figure 5: STV8130A # Typical Application RESET Ce 6 RESET 1 INPUT1 V IN1 R 1 + R2 V O2 = V R EF -------------------R1 0.1 µF 3 DELAY CAPACITOR OUTPUT1 9 R1 Value (typ.) = 10 kΩ V OUT1 VREF = 2.44 V STV8130A# V IN2 OUTPUT2 8 2 INPUT2 C1 GROUND DISABLE PROGRAM 5 4 7 C2 V OUT2 C4 R2 C3 DISABLE R1 C1 to C4 = 10 µF Figure 6: STV8130D # Typical Application RESET Ce 5 RESET V IN1 1 INPUT1 V IN2 2 INPUT2 R 1 + R2 V O2 = V R EF -------------------R1 0.1 µF 3 DELAY CAPACITOR OUTPUT1 8 R1 Value (typ.) = 10 kΩ V OUT1 VREF = 2.44 V STV8130D# GROUND C1 C2 Pins 9 to 16 4 APPLICATION DIAGRAMS V OUT2 OUTPUT2 7 DISABLE PROGRAM 4 6 C4 R2 C3 DISABLE R1 C1 to C4 = 10 µF 7/12 POWER DISSIPATION AND LAYOUT INDICATIONS 5 STV8130AD POWER DISSIPATION AND LAYOUT INDICATIONS The power is mainly dissipated by the two device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: ● Maximum Ambient Temperature = 70° C ● Maximum Junction Temperature = 140° C Device Heat Sink RthJA in °C/W PMAX in W No 50 1.4 Yes 20 3.5 No 56 to 40 1.25 to 1.75 Yes 32 2.2 STV8130A# STV8130D# Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP16 Package without Heat Sink To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. RthJA °C/W 60 55 Test Board with “On Board” square heat sink area. 50 45 40 6 0 2 4 8 10 12 Copper area (cm²) (35 µm plus solder) Board is face-down Figure 8: Metal plate mounted near the STV8130D# for heat sinking Top View Bottom View 8/12 STV8130AD 6 PACKAGE MECHANICAL DATA PACKAGE MECHANICAL DATA Figure 9: 9-Pin Plastic Single In Line Package mm Inches Dim. Min. Typ. A a1 Min. Typ. 7.1 2.7 3 B 0.106 0.118 0.976 0.5 0.85 0.020 1.6 0.033 0.063 C 3.3 0.130 c1 0.43 0.017 c2 1.32 0.052 D 21.2 d1 0.835 14.5 0.571 e 2.54 0.100 e3 20.32 0.800 L Max. 0.280 24.8 b1 b3 Max. 3.1 1.122 L1 3 L2 17.6 L3 0.116 0.693 0.25 0.010 M 3.2 0.126 N 1 0.039 9/12 PACKAGE MECHANICAL DATA STV8130AD Figure 10: 16-Pin Plastic Dual In-Line Package, 300-mil Width mm Inches Dim. Min. Typ. A Min. Typ. 5.33 A1 0.38 A2 2.92 b 0.36 b2 Max. 0.210 0.015 3.30 4.95 0.115 0.56 0.014 0.130 0.195 0.022 1.52 1.78 0.060 0.070 c 0.20 0.25 0.36 0.008 0.010 0.014 D 18.67 19.18 19.69 0.735 0.755 0.775 e 10/12 Max. 2.54 0.100 E1 6.10 6.35 7.11 0.240 0.250 0.280 L 2.92 3.30 3.81 0.115 0.130 0.150 STV8130AD 7 REVISION HISTORY REVISION HISTORY Revision Main Changes Date 1.8 General Update; DISABLE pin renamed DISABLE (function remains unchanged). August 2001 1.9 Thermal Data updated. September 2001 2.0 Addition of DIP16 package. September 2001 2.1 Thermal Data updated. Figure 1 and Figure 2 updated. 2.2 Order code changed from STV8130A and STV8130D to STV8130A# and STV8130D#. Update of VO1RST values in Chapter 2.3: Electrical Characteristics on page 4. October 2001 31 January 2002 11/12 STV8130AD Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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