SAA7162E PCI Express based dual channel multistandard audio and video decoder Rev. 02 — 13 August 2007 Product short data sheet 1. General description The SAA7162E is a dual channel multistandard audio and video TV decoder with digital IF demodulator and PCI Express interface. It provides 10-bit ADC, enhanced PAL/NTSC comb filtering, a versatile VBI data processing, more sophisticated scaling algorithms, support of high definition component video, picture improvement processing, more robustness with VCR type signals, increased audio functionality like SPDIF input/output, I2S-bus input/output and an integrated audio sample rate converter from 32 kHz to 44.1 kHz or 48 kHz. The SAA7162E is a highly integrated circuit for e.g. TV insertion inside PC systems. The multistandard TV decoder covered all video color standards like PAL, NTSC and SECAM and sound standards like dual FM, NICAM, BTSC and EIAJ. Additional to the TV decoder function a digital IF demodulator, an FM radio decoder, standard interfaces for digital video and audio, remote control receiver and transmission processing and a high-speed programming port allows high integrated system solutions for multimedia application. 2. Features 2.1 Analog video acquisition n Twenty analog inputs; allowing multiple combinations of u Dual channel CVBS u Dual channel S-video u Dual channel Y/C u One channel RGB or Y-PB-PR (progressive or interlaced); able to handle standard definition signals as well as HD0 u Dual channel low IF from an NXP Silicon Tuner n One channel RGB or Y-PB-PR component input according to u 480i and 576i (standard definition and interlaced) u 480p and 576p (HD0 and double scan rate) at two-fold over sampling (54 MHz) n Software controlled gain adjustment for Y-PB-PR component inputs n One channel 3-level input pins for one fully equipped D-terminal applications n Eight video processing channels with automatic signal clamping and signal amplifying adjustment to a high quality 10-bit CMOS analog-to-digital converter results in a four-fold ITU-R BT.656 oversampled (54 MHz) video signal n AGC for the selected CVBS or S-video channel, or manually adjustable gain for all video signal types SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder n Two channels with buffered analog outputs providing CVBS/S-video signal selected from any input n Two channels with differential analog CVBS and SSIF outputs from the integrated digital video IF demodulator 2.2 Digital IF demodulator n Two separate digital IF demodulators u Worldwide multistandard analog TV IF demodulator (M/N, B/G/H, D/K, I and L/L-accent standard) u FM radio pre-processing, internal selectivity for FM stereo application u Alignment-free application u Noise shaped IF AGC output signal u Easy programming of IF processing by TV or FM radio standard selection 2.3 Dual channel video signal processing and decoding n Luminance and chrominance signal processing for PAL BGDHIN, combination PAL N, PAL M, NTSC M, NTSC Japan, NTSC 4.43 and SECAM n High-performance super-adaptive NTSC/PAL comb filter for 2-dimensional chrominance/luminance separation for u Increased luminance and chrominance bandwidth for all NTSC and PAL standards u Reduced cross-color and cross luminance artefacts, even with critical color pattern n Automatic detection of any supported color standard n High-quality RGB and Y-PB-PR component processing for STV and progressive TV n Optional reduced resolution for Y-PB-PR component processing of HDTV (1080i and 720p) sources n Automatic detection of any supported video standard, including 480p, 576p, 720p and 1080i n Automatic detection of signals from consumer grade sources (e.g. VTRs) n Versatile BCS adjustment for CVBS/S-video, RGB and Y-PB-PR component processing n Easy discrimination between CVBS and Y/C signals n Digital PLL for synchronization and clock generation from all standards and non-standard video sources, e.g. consumer grade VTR n Detection of copy protected input signals according to the Macrovision standard, indicating level of protection, including progressive signals 480p and 576p n On-chip LLC generation according to ITU-R BT.601(standard definition) or SMPTE 293M/ITU-R BT.1358 (HD0) 2.4 Dual channel video scalers n Horizontal and vertical down-scaling and up-scaling to randomly sized windows n Horizontal up-down scaling u Linear horizontal scaling ratio down to 1⁄512 and up to 1024 limited by transfer data rates u Horizontal integer pre-scaler with range 1 to 1⁄128 u Horizontal VPD final scaler for down-scaling by 1⁄7.999 to up-scaling by factor 1024 SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 2 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder n Vertical up-down scaling u Linear phase accurate vertical scaling ratio down to 64 and up to 1024 limited by transfer data rates u Two separate 4-tap programmable polyphase filters for luminance (Y) and chrominance (U or V) data streams optimized for STV and HDTV u EDGI scale algorithm for areas with detected edges u Edge detector controlled mixing of 4-tap polyphase interpolator results and EDGI results enabling a maximum of performance with a minimize scale artefacts n Two separated tasks processing pipes for active video (task A) and raw VBI (task B) regions n Linear zooming of free programmable picture fragment n Programmable panorama scaling n Versatile BCS adjustment for scaled video outputs n Optional DCI via programmable LUT n Optional intrafield de-interlacing (EDGI) n Optional CTI n Optional RGB matrix and a programmable gamma correction 2.5 Dual channel advanced signal processing n Support for letter box detection (black bar detection) via histogram evaluation n Approximate noise level estimation of video input signal n Status register and programmable status change output (interrupt) to minimize software overhead n Support for RMS noise level estimation via histogram evaluation 2.6 Dual channel VBI slicing n Versatile VBI data slicer (slicer, clock regeneration and data byte synchronization) for all common text and data services u WST525/WST625, Gemstar2x and Gemstar1x/VPS, VITC525/VITC625, CC525/CC625, WSS525 (CGMS)/WSS625, CGMS-A (line 41) of 480p (HD0), CGMS (line 41) of 576p (HD0), US NABTS/European teletext (FC) and MOJI (Japanese) n Sliced VBI data can be transferred as ANC data on the digital video output ports (1, 2, 4 or 5) or on the parallel host port n I2C-bus read-back access to data of following VBI data standards u Closed caption (CC525 and CC625), CGMS (WSS525), WSS625, Gemstar1x, Gemstar2x and VPS n Optionally, raw data with dedicated gain and offset adjustment is available for software decoding SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 3 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 2.7 Digital peripheral interfaces n Digital video input ports of 50 pins usable for maximum clock rates up to 75 MHz u Five independent standard TV (ITU-R BT.656 and VMI) 8-bit or 10-bit input streams u Two STV/HDTV 16-bit input streams u One STV/HDTV 20-bit input stream u One STV/HDTV 24-bit (RGB) input stream u Four TS or PS 8-bit input streams n Selectable video input streaming standards u STV/HDTV video in ITU-R BT.656 representation, either 8-bit, 10-bit, 16-bit or 20-bit format Y-CB-CR 4 : 2 : 2 u STV/HDTV video in VMI representation, either 8-bit, 10-bit, 16-bit or 20-bit format u Optionally, STV/HDTV 24-bit (RGB) input stream converted to YUV 4 : 2 : 2 via internal programmable RGB/YUV matrix n A digital video output port of 50 pins usable for maximum clock rates up to 75 MHz u Four independent TV streams [STV (ITU-R BT.656 (8-bit or 10-bit) or VMI (8-bit)) and STV/HDTV (16-bit)] u Four independent standard TV (ITU-R BT.656, VMI) 8-bit or 10-bit output streams u Two STV/HDTV 16-bit output streams u Two STV/HDTV 20-bit output streams n Selectable video output streaming standards u STV/HDTV video in ITU-R BT.656 representation, either 8-bit, 10-bit, 16-bit or 20-bit format Y-CB-CR 4 : 2 : 2, optional with included sliced VBI data and/or audio data u STV/HDTV video in VMI representation, either 8-bit, 10-bit, 16-bit or 20-bit format n One serial input port for infrared transceivers supporting RC5 and RC6 transmission standards n One serial output port for infrared transmitter adjustable to all common transmission standards 2.8 Analog audio acquisition n Differential inputs of analog SSIF u Two differential SSIF signal inputs connectable to internal digital IF via simple post filter or u Two single ended SSIF signal inputs connectable to conventional tuners (TV and FM) n Sound processing channels with automatic signal clamping and signal amplifying adjustment to a high quality 10-bit CMOS ADC with 24.576 MHz sample frequency n Three stereo analog audio baseband inputs with four serial sigma-delta 16-bit high resolution audio ADC n Two stereo analog baseband outputs with filter stream stereo DACs n Integrated analog audio pass-through (support for analog audio loopback cable to sound card) SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 4 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 2.9 TV sound decoder n n n n n All standards TV stereo or mono sound decoder: BTSC, EIAJ, NICAM, FM A2 and AM dbx-TV noise reduction decoding for BTSC systems FM radio stereo decoding Automatic sound standard detection Automatic decoding for stereo and dual 2.10 Digital peripheral audio interfaces n Two SPDIF inputs and two 24-bit SPDIF outputs (according to IEC 60958-3 and TTL compliant only) with 32 kHz, 44.1 kHz or 48 kHz n Five I2S-bus inputs and two 24-bit I2S-bus outputs for up to 4 channels with 32 kHz, 44.1 kHz or 48 kHz n Two inputs of external audio reference clock of 256 × fs or 384 × fs n Two outputs of audio output master clock (512 × fs, 256 × fs or 128 × fs selectable) n Audio output sampling clock can be locked to video frame rate (constant number of audio samples per frame) 2.11 Audio feature processing n n n n n Four stereo SRCs from 32 kHz, 44.1 kHz or 48 kHz to 32 kHz, 44.1 kHz or 48 kHz Volume, balance, bass and treble control Incredible Mono and Incredible Stereo AVL Optional generation of a frame locked audio master clock to support a constant number of audio clocks per video field 2.12 Programming ports n PHI; byte oriented programming interface for fast access of modern microcontroller in future oriented PC TV applications u Fast alternative to I2C-bus based general control u Supports fast access to programming register (up to 8 MHz) u Supports 8-bit data and 16-bit address interface u Data read from VBI slicer (FIFO) for teletext decoding u IRQ register support n Four I2C-bus interfaces u Support register access with 100 kHz and 400 kHz bit rate u I2C-bus master usable PHI port to program additional system devices like tuner, MPEG encoder and decoder u I2C-bus slave, usable to support a programming interface for application systems with limiting controller performance u Two ‘silent’ I2C-bus ports to support noise sensitive devices n One SPI master interface for controlling external peripherals like MPEG encoder n 28 GPIO pins, partly shared with interrupt and chip select functions SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 5 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 2.13 PCI Express interface n Compliant to PCI Express Base Specification 1.0a n The PCI Express circuit supports isochronous data traffic intended for uninterrupted transfer of streaming data like video streaming u x1 PCI Express endpoint (2.5 Gbit/s) u Data and clock recovery from serial stream u Low jitter and BER n Type 0 configuration space header u 64-bit addressing u Single BAR; programmable address range of 17 bits, 18 bits, 19 bits or 20 bits dependent on application requirements n PCI Express capabilities u 128 bytes write packet size and 64 bytes read packet size u MSI support u Software directed power management of four device power states (D0 to D3) u Active state power management of link states u Vendor specific capability for VC1 support; after reset VC1 isochronous capability is disabled 2.14 DMA support n DMA write support u One DMA write channel for MSI u 12 DMA write channels for audio and video streaming: Maximum 8 software buffers per DMA channel or maximum buffer size of 2 MB u Round-robin arbitration between DMAs; support for graceful overflow recovery if PCI Express bandwidth is not provided in the required amount n DMA read support u One DMA read channel for reading from page table(s); required for virtual-to-physical address translation of the streaming DMAs 2.15 General features n Only a single crystal of 24.576 MHz or 32.11 MHz is required for all standards n Software controlled power saving Standby modes n Boundary scan test circuit according to ‘IEEE Std. 1149.1’ SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 6 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 3. Quick reference data Table 1. Quick reference data Symbol Parameter VDDDI0(1V8)_A Conditions Min Typ Max Unit digital internal supply voltage 0 (1.8 V) for unit A 1.65 1.8 1.95 V VDDDI3(1V8)_B digital internal supply voltage 3 (1.8 V) for unit B 1.65 1.8 1.95 V VDDDM0(1V8)_A memory digital supply voltage 0 (1.8 V) for unit A 1.65 1.8 1.95 V VDDDM0(1V8)_B memory digital supply voltage 0 (1.8 V) for unit B 1.65 1.8 1.95 V VDDDI1(1V2) digital internal supply voltage 1 (1.2 V) 1.1 1.2 1.3 V VDDDI2(1V2) digital internal supply voltage 2 (1.2 V) 1.1 1.2 1.3 V VDDD(PCI0)(1V2) PCI Express 0 digital supply voltage (1.2 V) 1.1 1.2 1.3 V VDDD(PCI1)(1V2) PCI Express 1 digital supply voltage (1.2 V) 1.1 1.2 1.3 V VDDDE0(3V3)_A digital extend supply voltage 0 (3.3 V) for unit A 3.0 3.3 3.6 V VDDDE2(3V3) digital extend supply voltage 2 (3.3 V) 3.0 3.3 3.6 V VDDDE3(3V3) digital extend supply voltage 3 (3.3 V) 3.0 3.3 3.6 V VDDDE4(3V3) digital extend supply voltage 4 (3.3 V) 3.0 3.3 3.6 V VDDDE5(3V3) digital extend supply voltage 5 (3.3 V) 3.0 3.3 3.6 V VDDDE6(3V3)_B digital extend supply voltage 6 (3.3 V) for unit B 3.0 3.3 3.6 V VDDD(PCI0)(1V0) PCI Express 0 digital supply voltage (1.0 V) 0.95 1.0 1.05 V VDDD(PCI1)(1V0) PCI Express 1 digital supply voltage (1.0 V) 0.95 1.0 1.05 V VDDA(DAC1_3V3)_A DAC 1 3.3 V analog supply voltage for unit A 3.1 3.3 3.5 V VDDA(DAC2_3V3)_A DAC 2 3.3 V analog supply voltage for unit A 3.1 3.3 3.5 V VDDA(PLL)(3V3)_A PLL analog supply voltage (3.3 V) for unit A 3.1 3.3 3.5 V VDDA0(3V3)_A analog supply voltage 0 (3.3 V) for unit A 3.1 3.3 3.5 V VDDA1(3V3)_A analog supply voltage 1 (3.3 V) for unit A 3.1 3.3 3.5 V VDDA2(3V3)_A analog supply voltage 2 (3.3 V) for unit A 3.1 3.3 3.5 V VDDA(ADC)(3V3)_A ADC analog supply voltage (3.3 V) for unit A 3.1 3.3 3.5 V VDDA(DAC1_3V3)_B DAC 1 3.3 V analog supply voltage for unit B 3.1 3.3 3.5 V VDDA(DAC2_3V3)_B DAC 2 3.3 V analog supply voltage for unit B 3.1 3.3 3.5 V VDDA(PLL)(3V3)_B PLL analog supply voltage (3.3 V) for unit B 3.1 3.3 3.5 V VDDA0(3V3)_B analog supply voltage 0 (3.3 V) for unit B 3.1 3.3 3.5 V VDDA1(3V3)_B analog supply voltage 1 (3.3 V) for unit B 3.1 3.3 3.5 V VDDA2(3V3)_B analog supply voltage 2 (3.3 V) for unit B 3.1 3.3 3.5 V VDDA(ADC)(3V3)_B ADC analog supply voltage (3.3 V) for unit B 3.1 3.3 3.5 V VDDA(PCI0)(3V3) PCI Express 0 analog supply voltage (3.3 V) 3.1 3.3 3.5 V VDDA(PCI1)(3V3) PCI Express 1 analog supply voltage (3.3 V) 3.1 3.3 3.5 V VDDA(1V8)_A analog supply voltage (1.8 V) for unit A 1.65 1.8 1.95 V VDDA(1V8)_B analog supply voltage (1.8 V) for unit B 1.65 1.8 1.95 V VDDA(OSC)(1V8)_A oscillator analog supply voltage (1.8 V) for unit A 1.65 1.8 1.95 V VDDA(OSC)(1V8)_B oscillator analog supply voltage (1.8 V) for unit B 1.65 1.8 1.95 V Ptot total power dissipation - 3.7 4.2 W power management states; D0 for typical application SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 7 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder Table 1. Quick reference data …continued Symbol Parameter Tamb ambient temperature Conditions Min Typ Max Unit 0 - 70 °C PCI Express link data rate fRX receiver data rate - 2.5 - Gbit/s fTX transceiver data rate - 2.5 - Gbit/s 10-bit ADCs (including analog clamp and gain stages) DLEDC DC differential linearity error - 1 - LSB ILEDC DC integral linearity error - 1 - LSB - 1 - V Analog video outputs (AVO_A1 and AVO_B1) peak-to-peak output voltage Vo(p-p) for normal video levels 1 V (p-p); 75 Ω termination 10-bit DACs (ASIFO_AP, ASIFO_AN, AVO_AP, AVO_AN, ASIFO_BP, ASIFO_BN, AVO_BP and AVO_BN) DLEDC DC differential linearity error - - 1 LSB ILEDC DC integral linearity error - - 2 LSB Analog audio inputs (AAIL_AB2, AAIR_AB2, AAIL_A1, AAIR_A1) and analog audio outputs (AAOL_A2, AAOR_A2, AAOL_A1 and AAOR_A1) nominal input voltage (RMS value) Vi(nom)(rms) maximum input voltage (RMS value) Vi(max)(rms) - 200 - mV THD < 3 % [1] - - 1 V [2] - 180 - mV - 1 - V Vo(nom)(rms) nominal output voltage (RMS value) THD < 3 % Vo(max)(rms) maximum output voltage (RMS value) THD < 3 % [1] The analog audio inputs are supported by two input levels: 1 V (RMS) and 2 V (RMS), selectable independently per stereo input pair. [2] Definition of levels and level setting: a) The full-scale level for analog audio signals is 0.8 V (RMS). The nominal level at the digital crossbar switch is defined at −15 dB (FS) b) Nominal audio input levels: external, mono, Vi = 180 mV (RMS); −15 dB (FS) 4. Ordering information Table 2. Ordering information Type number SAA7162E Package Name Description Version BGA756 plastic ball grid array package; 756 balls; body 35 × 35 × 1.75 mm SOT875-1 SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 8 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 5. Block diagram PORT_6 SPDIF_B I2S_IO_B PORT_5 PORT_4 SAA7162E SDA_SILENT_B SCL_SILENT_B I2C-BUS SILENT AVI_B10P AVI_B10N SI_AGC_B AVO_B ASIF_B FGPI2/3 CONTROL CROSSBAR AAI_B I2S_B SPDIF_I_B LOGICAL AUDIO AND VIDEO UNIT B DIGITAL IF DUAL DAC ADC DAC MUX SIF DEMODULATOR STEREO DECODER DSP AVI_B AI1 PORT_7 PORT_8 MULTISTANDARD DECODER VIDEO FRONT-END COMPONENT PROCESSING QUADRUPLE ADC AUDIO AND VIDEO INPUT CROSSBAR VBI SLICER IR SCALER VI0 DIGITAL VIDEO INPUT AI0 SIF DEMODULATOR STEREO DECODER CROSSBAR DUAL DAC SI_AGC_A AVI_A10P AVI_A10N SDA_SILENT_A SCL_SILENT_A CROSSBAR CROSSBAR COMPONENT PROCESSING QUADRUPLE ADC SPDIF_I_A I2S_AB I2S_A AAI_AB AAI_A AVO_A DMA AND FIFO MULTISTANDARD DECODER VIDEO FRONT-END VBI SLICER ASIF_A SCALER VI1 MUX AUX VSYNC_A AVI_A AAO_A CROSSBAR VSYNC_B CROSSBAR DIGITAL VIDEO INPUT ADC DAC DSP CONTROL DIGITAL IF MUX FGPI0/1 LOGICAL AUDIO AND VIDEO UNIT A I2C-BUS SILENT IR MESSAGE SIGNAL INTERRUPT PORT_1 PORT_2 I2S_IO_A SPDIF_A PORT_3 I2C_B I2C_A PHI GPIO SPI MEMORY MANAGEMENT UNIT PERIPHERAL CONTROL INTERFACE PCI EXPRESS INTERFACE XTAL JTAG TEST POWER XTAL JTAG TEST POWER 001aad710 PCI_E Fig 1. Block diagram of SAA7162E SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 9 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 6. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDDA(1V8)_A Conditions Min Max Unit analog supply voltage (1.8 V) for unit A −0.5 +2.5 V VDDA(1V8)_B analog supply voltage (1.8 V) for unit B −0.5 +2.5 V VDDA(OSC)(1V8)_A oscillator analog supply voltage (1.8 V) for unit A −0.5 +2.5 V VDDA(OSC)(1V8)_B oscillator analog supply voltage (1.8 V) for unit B −0.5 +2.5 V VDDDI0(1V8)_A digital internal supply voltage 0 (1.8 V) for unit A −0.5 +2.5 V VDDDI3(1V8)_B digital internal supply voltage 3 (1.8 V) for unit B −0.5 +2.5 V VDDDM0(1V8)_A memory digital supply voltage 0 (1.8 V) for unit A −0.5 +2.5 V VDDDM0(1V8)_B memory digital supply voltage 0 (1.8 V) for unit B −0.5 +2.5 V VDDA(DAC1_3V3)_A DAC 1 3.3 V analog supply voltage for unit A −0.5 +4.5 V VDDA(DAC2_3V3)_A DAC 2 3.3 V analog supply voltage for unit A −0.5 +4.5 V VDDA(PLL)(3V3)_A PLL analog supply voltage (3.3 V) for unit A −0.5 +4.5 V VDDA0(3V3)_A analog supply voltage 0 (3.3 V) for unit A −0.5 +4.5 V VDDA1(3V3)_A analog supply voltage 1 (3.3 V) for unit A −0.5 +4.5 V VDDA2(3V3)_A analog supply voltage 2 (3.3 V) for unit A −0.5 +4.5 V VDDA(ADC)(3V3)_A ADC analog supply voltage (3.3 V) for unit A −0.5 +4.5 V VDDA(DAC1_3V3)_B DAC 1 3.3 V analog supply voltage for unit B −0.5 +4.5 V VDDA(DAC2_3V3)_B DAC 2 3.3 V analog supply voltage for unit B −0.5 +4.5 V VDDA(PLL)(3V3)_B PLL analog supply voltage (3.3 V) for unit B −0.5 +4.5 V VDDA0(3V3)_B analog supply voltage 0 (3.3 V) for unit B −0.5 +4.5 V VDDA1(3V3)_B analog supply voltage 1 (3.3 V) for unit B −0.5 +4.5 V VDDA2(3V3)_B analog supply voltage 2 (3.3 V) for unit B −0.5 +4.5 V VDDA(ADC)(3V3)_B ADC analog supply voltage (3.3 V) for unit B −0.5 +4.5 V VDDA(PCI0)(3V3) PCI Express 0 analog supply voltage (3.3 V) −0.5 +4.5 V VDDA(PCI1)(3V3) PCI Express 1 analog supply voltage (3.3 V) −0.5 +4.5 V VDDDE0(3V3)_A digital extend supply voltage 0 (3.3 V) for unit A −0.5 +4.5 V VDDDE2(3V3) digital extend supply voltage 2 (3.3 V) −0.5 +4.5 V VDDDE3(3V3) digital extend supply voltage 3 (3.3 V) −0.5 +4.5 V VDDDE4(3V3) digital extend supply voltage 4 (3.3 V) −0.5 +4.5 V VDDDE5(3V3) digital extend supply voltage 5 (3.3 V) −0.5 +4.5 V VDDDE6(3V3)_B digital extend supply voltage 6 (3.3 V) for unit B −0.5 +4.5 V VDDD(PCI0)(1V0) PCI Express 0 digital supply voltage (1.0 V) 0.85 1.15 V VDDD(PCI1)(1V0) PCI Express 1 digital supply voltage (1.0 V) 0.85 1.15 V VDDDI1(1V2) digital internal supply voltage 1 (1.2 V) −0.5 +1.7 V VDDDI2(1V2) digital internal supply voltage 2 (1.2 V) −0.5 +1.7 V VDDD(PCI0)(1V2) PCI Express 0 digital supply voltage (1.2 V) −0.5 +1.7 V VDDD(PCI1)(1V2) PCI Express 1 digital supply voltage (1.2 V) −0.5 +1.7 V Vi input voltage −0.5 VDD + 0.5 V Tstg storage temperature −40 +125 SAA7162E_SDS_2 Product short data sheet °C © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 10 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Tamb ambient temperature Vesd electrostatic discharge voltage [1] Class 2 according to JESD22-A114-D. [2] Class B according to EIA/JESD22-A115-A. Conditions Max Unit 0 70 °C human body model [1] - ±2000 V machine model [2] - ±200 V SAA7162E_SDS_2 Product short data sheet Min © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 11 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 7. Package outline BGA756: plastic ball grid array package; 756 balls; body 35 x 35 x 1.75 mm D D1 SOT875-1 B A ball A1 index area A E1 E A2 A1 detail X C e1 e AP AM AK AH AF AD AB Y V T P M K H F D B ∅v ∅w b 1/2 e M M y1 C C A B C y AN AL e AJ AG AE AC AA W e2 U R 1/2 e N L J G E C A 1 2 shape optional (4×) 3 5 4 7 6 9 11 13 15 17 19 21 23 25 27 29 31 33 8 10 12 14 16 18 20 22 24 26 28 30 32 34 0 X 10 20 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 A2 b D D1 E E1 e e1 e2 v w y y1 mm 2.45 0.6 0.4 1.85 1.60 0.7 0.5 35.2 34.8 30.75 29.75 35.2 34.8 30.75 29.75 1 33 33 0.25 0.1 0.2 0.35 REFERENCES OUTLINE VERSION IEC JEDEC SOT875-1 --- MS-034 JEITA EUROPEAN PROJECTION ISSUE DATE 04-11-29 04-12-06 Fig 2. Package outline SOT875-1 (BGA756) SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 12 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 8. Abbreviations Table 4. Abbreviations Acronym Description ADC Analog-to-Digital Converter AGC Automatic Gain Control ANC Ancillary AVL Automatic Volume Levelling BAR Base Address Register BCS Brightness Contrast Saturation BER Bit Error Rate BTSC Broadcast Television Systems Committee CC Closed Caption CGMS Copy Generation Management System CMOS Complementary Metal-Oxide Semiconductor CTI Color Transient Improvement CVBS Color Video Blanking Signal DAC Digital-to-Analog Converter DC Direct Current DCI Dynamic Contrast Improvement DMA Direct Memory Access EDGI Edge Guided 2-tap Interpolation EIAJ Electronic Industries Association/JEDEC standard FC Framing Code FIFO First In First Out GPIO General Purpose Input/Output HD0 High Definition 0 HDTV High Definition TV IF Intermediate Frequency IRQ Interrupt ReQuest LLC Line-Locked Clock LUT Look-Up Table MPEG Moving Picture Experts Group; the official name is ISO/IEC JTC1/SC29/WG11 (International Organization for Standardization/International Electrotechnical Commission, Joint Technical Committee 1, Subcommittee 29, Working Group 11) MSI Message Signal Interrupt NABTS North American Broadcast Text System NICAM Near Instantaneous Companded Audio Multiplex NTSC National Television Standards Committee PAL Phase Alternating Line PC Personal Computer PCI Peripheral Component Interconnect PHI Parallel Host port Interface SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 13 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder Table 4. Abbreviations …continued Acronym Description PLL Phase-Locked Loop PS Program Stream RC Remote Control RGB Red Green Blue RMS Root Mean Square SECAM Sequentiel Couleur avec Memoire SPDIF Sony Philips Digital Interface SPI Serial Peripheral Interface SRC Sample Rate Converter SSIF Second Sound Intermediate Frequency STV Standard TV TS Transport Stream TTL Transistor-Transistor Logic VBI Vertical Blanking Interval VC Virtual Channel VCR Voltage-Controlled Resistor VITC Vertical Interval Time Code VMI Video Module Interface VPD Variable Phase Delay VPS Video Programming System VTR Video Tape Recorder WSS Wide Screen Signalling WST World Standard Teletext YUV luminance (Y) and chrominance (U and V) 9. Revision history Table 5. Revision history Document ID Release date Data sheet status Change notice Supersedes SAA7162E_SDS_2 20070813 Product short data sheet - SAA7162E_SDS_1 Modifications: SAA7162E_SDS_1 • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. 20060710 Preliminary short data sheet - SAA7162E_SDS_2 Product short data sheet - © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 14 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 10. Legal information 10.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 10.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 10.4 Licenses 10.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of ICs with RC5 functionality Purchase of an NXP Semiconductors IC with RC5 functionality does not convey an implied license under any trade secret, copyright, know-how or patent right to use this IC in any RC5 application. A license under applicable rights of Koninklijke Philips Electronics N.V. needs to be obtained via Philips Intellectual Property and Standards (www.ip.philips.com), e-mail: [email protected]. ICs with Macrovision copyright protection technology This product incorporates copyright protection technology that is protected by method claims of certain U.S. patents and other intellectual property rights owned by Macrovision Corporation and other rights owners. Use of this copyright protection technology must be authorized by Macrovision Corporation and is intended for home and other limited viewing uses only, unless otherwise authorized by Macrovision Corporation. Reverse engineering or disassembly is prohibited. ICs with RC6 functionality Purchase of an NXP Semiconductors IC with RC6 functionality does not convey an implied license under any trade secret, copyright, know-how or patent right to use this IC in any RC6 application. A license under applicable rights of Koninklijke Philips Electronics N.V. needs to be obtained via Philips Intellectual Property and Standards (www.ip.philips.com), e-mail: [email protected]. SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 15 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder Purchase of NXP ICs with digital dbx-TV noise reduction functionality Licensed Chips — Purchase of NXP Semiconductors ICs with digital dbx-TV noise reduction functionality for which on top of the IC price, the related THAT Corporation royalty payment is paid to NXP Semiconductors, includes a license from THAT Corporation to use the ICs in a BTSC decoding application. 10.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. Silicon Tuner — is a trademark of NXP B.V. Unlicensed Chips — Purchase of NXP Semiconductors ICs with digital dbx-TV noise reduction functionality for which on top of the IC price, no related THAT Corporation royalty payment is paid to NXP Semiconductors, is only permitted to parties who according to information supplied to NXP Semiconductors by THAT Corporation, have a BTSC set-maker license from THAT Corporation, 45 Summer street, Milford, Massachusetts 01757-1656, USA. 11. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: [email protected] SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 16 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder Notes SAA7162E_SDS_2 Product short data sheet © NXP B.V. 2007. All rights reserved. Rev. 02 — 13 August 2007 17 of 18 SAA7162E NXP Semiconductors PCI Express based dual channel audio and video decoder 12. Contents 1 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 3 4 5 6 7 8 9 10 10.1 10.2 10.3 10.4 10.5 11 12 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Analog video acquisition . . . . . . . . . . . . . . . . . . 1 Digital IF demodulator. . . . . . . . . . . . . . . . . . . . 2 Dual channel video signal processing and decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Dual channel video scalers. . . . . . . . . . . . . . . . 2 Dual channel advanced signal processing . . . . 3 Dual channel VBI slicing . . . . . . . . . . . . . . . . . . 3 Digital peripheral interfaces . . . . . . . . . . . . . . . 4 Analog audio acquisition. . . . . . . . . . . . . . . . . . 4 TV sound decoder . . . . . . . . . . . . . . . . . . . . . . 5 Digital peripheral audio interfaces . . . . . . . . . . 5 Audio feature processing . . . . . . . . . . . . . . . . . 5 Programming ports . . . . . . . . . . . . . . . . . . . . . . 5 PCI Express interface . . . . . . . . . . . . . . . . . . . . 6 DMA support. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General features . . . . . . . . . . . . . . . . . . . . . . . . 6 Quick reference data . . . . . . . . . . . . . . . . . . . . . 7 Ordering information . . . . . . . . . . . . . . . . . . . . . 8 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 10 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 14 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Contact information. . . . . . . . . . . . . . . . . . . . . 16 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 13 August 2007 Document identifier: SAA7162E_SDS_2