PHILIPS SAA7133HL

INTEGRATED CIRCUITS
DATA SHEET
SAA7133HL
PCI audio and video broadcast
decoder
Product specification
2003 Feb 04
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
CONTENTS
8
BOUNDARY SCAN TEST
1
FEATURES
8.1
8.2
Initialization of boundary scan circuit
Device identification codes
1.1
1.2
1.3
1.4
1.5
General
TV video decoder and video scaling
TV sound decoder and TV audio I/O
PCI and DMA bus mastering
Peripheral interface
9
LIMITING VALUES
10
THERMAL CHARACTERISTICS
11
CHARACTERISTICS
12
PACKAGE OUTLINE
2
GENERAL DESCRIPTION
13
SOLDERING
2.1
2.2
Introduction
Related documents
13.1
3
QUICK REFERENCE DATA
4
ORDERING INFORMATION
5
BLOCK DIAGRAM
13.2
13.3
13.4
13.5
6
PINNING
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
6.1
6.2
6.3
Pins sorted by number
Pins grouped by function
Pin type
7
FUNCTIONAL DESCRIPTION
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Overview of internal functions
Application examples
Software support
PCI interface
Analog TV standards
Video processing
TV sound
DTV/DVB channel decoding and MPEG TS or
PS capture
Control of peripheral devices
2003 Feb 04
2
14
DATA SHEET STATUS
15
DEFINITIONS
16
DISCLAIMERS
17
PURCHASE OF PHILIPS I2C COMPONENTS
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
1
1.1
SAA7133HL
FEATURES
General
• Package: LQFP128
• Power supply: 3.3 V only
• Power consumption of typical application: 1.35 W
• Volume, balance, bass and treble control
• PCI-bus Power Management Interface Specification,
rev. 1.1, compliant (supported states: D0, D1, D2
and D3-hot)
• Automatic Volume Levelling (AVL)
• Incredible Mono, Incredible Stereo
• Audio sampling clock can be locked to video frame rate
(no drift of audio stream against video stream)
• Power-down state (D3-hot): <20 mW
• All interface signals 5 V tolerant
• Four analog audio baseband inputs (two stereo pairs)
and on-chip stereo ADCs
• Reference designs available
• Software Development Kit (SDK) for Windows
(95, 98, NT, 2000 and XP), Video for Windows (VfW),
Windows Driver Model (WDM) and Broadcast Driver
Architecture (BDA).
1.2
• Supported audio sampling rates: 32, 44.1 and 48 kHz
• Input of external audio reference clock, e.g. 24.576 MHz
• Output of audio master clock (768 × fs, 512 × fs, 384 × fs
or 256 × fs selectable).
TV video decoder and video scaling
• All-standards TV decoder: NTSC, PAL and SECAM
1.4
• Five analog video inputs: CVBS and S-video
• PCI 2.2 compliant including full Advanced Configuration
and Power Interface (ACPI)
• Video digitizing by two 9-bit ADCs at 27 MHz
PCI and DMA bus mastering
• 3.3 and 5 V compliant
• Sampling according ITU-R BT.601 with 720 pixels/line
• System vendor ID, etc. via I2C-bus EEPROM
• Adaptive comb filter for NTSC and PAL, also operating
for non-standard signals
• DMA bus master write for video, audio, VBI and
TS or PS
• Automatic TV standard detection
• Configurable PCI FIFOs, graceful overflow recovery
• Three level Macrovision copy protection detection
according to Macrovision detect specification Rev.1
• Packed and planar video formats, overlay clipping
• Hardware support for virtual addressing by Memory
Management Unit (MMU).
• Control of brightness, contrast, saturation and hue
• Versatile filter bandwidth selection
• Horizontal and vertical downscaling or zoom
1.5
• Adaptive anti-alias filtering
•
• Capture of raw VBI samples
Peripheral interface
I2C-bus
master interface: 3.3 and 5 V compatible,
100 and 400 kHz mode
• Two alternating settings for active video scaling, e.g. for
independent capturing and preview definition
• The device can operate without PCI-bus (using I2C-bus)
for stand-alone applications, application note available
• Output in YUV or RGB
• Digital video output: ITU, VIP, VMI and ZV formats
• Gamma compensation, black stretching.
• Two digital audio outputs: I2S-bus for up to 4 channels
1.3
• Analog stereo audio output
TV sound decoder and TV audio I/O
• Integrated analog audio pass-through
• BTSC and EIAJ TV sound decoder
• Support for analog audio loop back cable to sound card
• dbx-TV Noise Reduction decoding for BTSC systems
• TS input: serial or parallel
• FM radio stereo decoding
• MPEG elementary or program stream input, parallel
• Input of analog SIF signal and 8-bit ADC at 24.576 MHz
• General purpose I/O, e.g. for strapping and interrupt
• Automatic sound standard detection
• Propagate reset and ACPI state D3.
• Automatic dematrixing (stereo, dual)
2003 Feb 04
3
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
2
2.1
GENERAL DESCRIPTION
SAA7133HL
Analog TV sound is digitized and stereo decoded (BTSC
and EIAJ). Audio is streamed digitally via the PCI-bus or
the I2S-bus or routed as an analog signal via the loop back
cable to the sound card.
Introduction
The PCI audio and video broadcast decoder SAA7133HL
is a highly integrated, low cost and solid foundation for
TV capture in the PC, for analog TV and digital video
broadcast (DTV and DVB). The various multimedia data
types are transported over the PCI-bus by
bus-master-write, to optimum exploit the streaming
capabilities of a modern host based system (see Fig.1).
Legacy requirements are also taken care of.
The SAA7133HL provides a versatile peripheral interface
to support system extensions, e.g. MPEG encoding for
time shift viewing.
The channel decoder for digital video broadcast reception
(ATSC or DVB) can re-use the integrated video ADCs.
The Transport Stream (TS) or Program Stream (PS) is
collected by a tailored interface and pumped through the
PCI-bus to the system memory in well-defined buffer
structures. Various internal events, or peripheral status
information, can be enabled as an interrupt on the
PCI-bus.
The SAA7133HL meets the requirements of PC Design
Guides 98/99 and 2001 and is PCI 2.2 and Advanced
Configuration and Power Interface (ACPI) compliant.
The analog video is sampled by 9-bit ADCs, decoded by a
multi-line adaptive comb filter and scaled horizontally,
vertically and by field rate. Multiple video output formats
(YUV and RGB) are available, including packed and
planar, gamma-compensated or black-stretched.
handbook,
fullfull
pagewidth
handbook,
pagewidth
I 2C-bus
TV TUNER:
CABLE
TERRESTRIAL
SATELLITE
IF-PLL:
DVB
ATV
DTV
DVB
DIGITAL CHANNEL DECODER:
VSB
QAM
OFDM
(1)
I 2C-BUS
EEPROM
(1)
SIF
TS
CVBS
PS
ENCODER:
MPEG2
I 2S-bus
CVBS
S-video
audio I/O
DECODER FOR TV SOUND AND TV VIDEO
WITH TS AND PS INTERFACE AND
DMA MASTER INTO PCI-BUS
PCI-bus
ITU656
SAA7133HL
MBL702
(1) Alternatively.
Fig.1
Application diagram for capturing live TV video and audio streams in the PC, with optional extensions for
DTV and DVB capture and MPEG encoding for time shift viewing.
2003 Feb 04
4
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
2.2
• Data sheets of other devices referred to in this
document, e.g:
Related documents
This document describes the functionality and
characteristics of the SAA7133HL.
– Tuners:
FI1236 for NTSC (US)
FI1286 for NTSC (Japan)
combi-tuner derivatives for FM radio: FM12x6
Other documents related to the SAA7133HL are:
• User manual SAA7133HL, describing the
programmability
– SAA6752HS: MPEG-2 video and MPEG-audio/AC-3
audio encoder with multiplexer.
• Application note SAA7133HL, pointing out
recommendations for system implementation
3
SAA7133HL
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDD
supply voltage
3.0
3.3
3.6
V
Ptot
total power dissipation
−
1.35
1.6
W
Pstandby
standby power dissipation
−
−
0.02
W
Tamb
ambient temperature
0
−
70
°C
4
D3-hot of ACPI
ORDERING INFORMATION
TYPE
NUMBER
SAA7133HL
2003 Feb 04
PACKAGE
NAME
DESCRIPTION
VERSION
LQFP128
plastic low profile quad flat package; 128 leads; body 14 × 20 × 1.4 mm
SOT425-1
5
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left 2
right 2
SIF
ANALOG
SIF/AUDIO
INTERFACE
16-BIT
STEREO ADC
8-BIT
SIF
ADC
AUDIO
FEATURE
PROCESSING
BTSC
EIAJ
FM DECODER
AM DECODER
STEREO DAC
AUDIO
OUTPUT
MUX
audio
stereo
output
I 2S-BUS
I 2S-bus
VIDEO
PORT
ITU656
FORMAT
CV3
CV4
TS/PS data
TS data
digital
data
inputs
GPIO
interrupt
ANALOG
VIDEO
INTERFACE
9-BIT
VIDEO
ADC
DIGITAL VIDEO
COMB FILTER
DECODER
VIDEO
SCALER
MATRIX
GAMMA
CLIPPING
FORMAT
SYNCHRONIZATION
TS/PS PARALLEL
OR
TS SERIAL
PCI INTERFACE
CV2
9-BIT
VIDEO
ADC
DMA
CV1
CVBS
S-video
inputs
ANALOG
VIDEO
INTERFACE
PCI-bus
FORMAT
STATIC I/O
PROGRAM
REGISTERS
IRQ
I 2C-bus
MBL703
Product specification
Fig.2 Block diagram.
SAA7133HL
handbook, full pagewidth
6
CV0
FIFO
SAA7133HL
PCI audio and video broadcast decoder
BLOCK DIAGRAM
sound
audio
inputs
analog audio pass-through
ANALOG
NF/AUDIO
INTERFACE
Philips Semiconductors
5
2003 Feb 04
left 1
right 1
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
6
PINNING
SAA7133HL
SYMBOL
PIN
In Section 6.1 all the pins are sorted by number, table 1.
AD[16]
The pin description for the functional groups is given in
Section 6.2:
C/BE[2]#
24
FRAME#
25
IRDY#
26
TRDY#
27
DEVSEL#
28
STOP#
29
PERR#
30
SERR#
31
PAR
32
• Power supply pins, table 2
• Joint Test Action Group (JTAG) test interface pins for
boundary scan test, table 3
• I2C-bus multi-master interface, table 4
• PCI interface pins, table 5
• General purpose interface (pins GPIO) and the main
functions, table 6
• Analog interface pins, table 7.
23
C/BE[1]#
33
The characteristics of the pin types are detailed in
Section 6.3, table 8.
AD[15]
34
AD[14]
35
The SAA7133HL is packaged in a rectangular LQFP (low
profile quad flat package) with 128 pins (see Fig.3).
AD[13]
36
AD[12]
37
6.1
VDDD
38
VSSD
39
PCI_CLK
40
AD[11]
41
Pins sorted by number
Table 1
Pins sorted by number
SYMBOL
PIN
VDDD
1
AD[10]
42
GNT#
2
AD[09]
43
REQ#
3
AD[08]
44
AD[31]
4
C/BE[0]#
45
AD[30]
5
AD[07]
46
AD[29]
6
AD[06]
47
AD[28]
7
AD[05]
48
AD[27]
8
AD[04]
49
AD[26]
9
AD[03]
50
AD[25]
10
AD[02]
51
AD[24]
11
AD[01]
52
C/BE[3]#
12
AD[00]
53
IDSEL
13
VDDD
54
AD[23]
14
VSSD
55
AD[22]
15
GPIO23
56
AD[21]
16
GPIO22
57
AD[20]
17
GPIO21
58
AD[19]
18
GPIO20
59
VDDD
19
GPIO19
60
VSSD
20
GPIO18
61
AD[18]
21
XTALI
62
AD[17]
22
XTALO
63
2003 Feb 04
7
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
PIN
SAA7133HL
SYMBOL
PIN
VSSD
64
PROP_RST
105
VDDD
65
SIF
106
V_CLK
66
VREF3
107
GPIO17
67
VSSA
108
GPIO16
68
CV2_C
109
GPIO15
69
VDDA
110
GPIO14
70
VREF4
111
GPIO13
71
DRCV_Y
112
GPIO12
72
VSSA
113
VDDD
73
CV0_Y
114
VSSD
74
VDDA
115
GPIO11
75
CV1_Y
116
GPIO10
76
DRCV_C
117
GPIO9
77
CV3_C
118
GPIO8
78
VSSA
119
GPIO7
79
CV4
120
GPIO6
80
TRST
121
GPIO5
81
TCK
122
GPIO4
82
TMS
123
GPIO3
83
TDO
124
GPIO2
84
TDI
125
GPIO1
85
INT_A
126
GPIO0
86
PCI_RST#
127
GPIO27
87
VSSD
128
GPIO26
88
GPIO25
89
SCL
90
SDA
91
VDDD
92
VSSD
93
LEFT2
94
VDDA
95
LEFT1
96
VSSA
97
RIGHT1
98
VREF0
99
RIGHT2
100
VREF1
101
VREF2
102
OUT_RIGHT
103
OUT_LEFT
104
2003 Feb 04
8
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
6.2
SAA7133HL
Pins grouped by function
Table 2
Power supply pins
SYMBOL
PIN
TYPE
DESCRIPTION
VSSA
97, 108, 113
and 119
AG
analog ground for integrated analog signal processing
VDDA
95, 110
and 115
AS
analog supply voltage for integrated analog signal processing
VSSD
20, 39, 55,
64, 74, 93
and 128
VG
digital ground for digital circuit, core and I/Os
1, 19, 38, 54, VS
65, 73
and 92
VDDD
Table 3
digital supply voltage for digital circuit, core and I/Os. The next generation
products of this product family will be pin compatible to its predecessors but
with a core supply voltage of 1.8 V.
JTAG test interface pins
SYMBOL
PIN
TYPE
DESCRIPTION
TRST
121
I
test reset input: drive LOW for normal operating (active LOW)
TCK
122
I
test clock input: drive LOW for normal operating
TMS
123
I
test mode select input: tie HIGH or let float for normal operating
TDO
124
O
test serial data output: 3-state
TDI
125
I
test serial data input: tie HIGH or let float for normal operating
Table 4
I2C-bus multi-master interface
SYMBOL
PIN
TYPE
DESCRIPTION
SCL
90
IO2
serial clock input (slave mode) or output (multi-master mode)
SDA
91
IO2
serial data input and output; always available
PROP_RST
105
GO
propagate reset and D3-hot output; to peripheral board circuitry (active
LOW)
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 5
SAA7133HL
PCI interface pins, PCI-bus pins are located on the long side of the package to simplify PCI board layout
requirements
SYMBOL
PIN
TYPE
DESCRIPTION
PCI_CLK
40
PI
PCI clock input: reference for all bus transactions, up to 33.33 MHz
PCI_RST#
127
PI
PCI reset input: will 3-state all PCI pins (active LOW)
AD[31] to
AD[00]
C/BE[3]# to
C/BE[0]#
4 to 11,
14 to 18,
21 to 23,
34 to 37,
41 to 44 and
46 to 53
PIO and multiplexed address and data input or output: bi-directional, 3-state
T/S
12, 24, 33
and 45
PIO and command code input or output: indicates type of requested transaction and
T/S
byte enable, for byte aligned transactions (active LOW)
PAR
32
PIO and parity input or output: driven by the data source, even parity over all pins AD
T/S
and C/BE#
FRAME#
25
PIO and frame input or output: driven by the current bus master (owner), to indicate
S/T/S
the beginning and duration of a bus transaction (active LOW)
TRDY#
27
PIO and target ready input or output: driven by the addressed target, to indicate
S/T/S
readiness for requested transaction (active LOW)
IRDY#
26
PIO and initiator ready input or output: driven by the initiator, to indicate readiness to
S/T/S
continue transaction (active LOW)
STOP#
29
PIO and stop input or output: target is requesting the master to stop the current
S/T/S
transaction (active LOW)
IDSEL
13
PI
DEVSEL#
28
PIO and device select input or output: driven by the target device, to acknowledge
S/T/S
address decoding (active LOW)
REQ#
3
PO
PCI request output: the SAA7133HL requests master access to PCI-bus
(active LOW)
GNT#
2
PI
PCI grant input: the SAA7133HL is granted to master access PCI-bus
(active LOW)
INT_A
126
PO and
O/D
interrupt A output: this pin is an open-drain interrupt output, conditions
assigned by the interrupt register
PERR#
30
PIO and parity error input or output: the receiving device detects data parity error
S/T/S
(active LOW)
SERR#
31
PO and
O/D
2003 Feb 04
initialization device select input: this input is used to select the SAA7133HL
during configuration read and write transactions
system error output: reports address parity error (active LOW)
10
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 6
SAA7133HL
GPIO pins and functions; note 1
FUNCTION
SYMBOL
PIN
TYPE
AUDIO AND VIDEO
PORT OUTPUTS
TS AND PS CAPTURE
INPUTS
RAW DTV/DVB
OUTPUTS
GPIO
GPIO27
87
GIO
A_SDO (I2S-bus 1 data)
−
−
R/W
GPIO26
88
GIO
A_WS (I2S-bus word
select)
−
−
R/W
GPIO25
89
GIO
A_SCK (I2S-bus clock)
−
−
R/W
V_CLK
66
GO
V_CLK (also gated)
−
ADC_CLK (out)
−
GPIO23
56
GIO
HSYNC
−
ADC_C[0] (LSB) R/W, INT
GPIO22
57
GIO
VSYNC
TS_LOCK (channel
decoder locked)
−
R/W, INT
GPIO21
58
GIO
−
TS_S_D
(bit-serial data)
−
R/W
GPIO20
59
GIO
−
TS_CLK (<33 MHz)
−
R/W
GPIO19
60
GIO
−
TS_SOP (packet start)
−
R/W
GPIO18
61
GIO
VAUX2; A_CLK_master,
A_REF_CLK
−
X_CLK_IN
R/W, INT
GPIO17
67
GIO
VAUX1 (e.g. VACTIVE);
A_SDO_aux, I2S-bus 2
data
−
ADC_Y[0] (LSB) R/W
GPIO16
68
GIO
−
TS_VAL (valid flag)
−
R/W, INT
GPIO15 to
GPIO8
69 to 72 GIO
and
75 to 78
VP[7:0] for formats:
ITU-R BT.656, VMI,
VIP (1.1, 2.0), etc.
−
ADC_Y[8:1]
R/W
GPIO7 to
GPIO0
79 to 86 GIO
VP extension for 16-bit
formats: ZV, VIP-2,
DMSD, etc.
TS_P_D[7:0] (transport ADC_C[8:1]
stream or program
stream, byte-parallel
data)
R/W
Note
1. The SAA7133HL offers a peripheral interface with General Purpose Input/Output (GPIO) pins. Dedicated functions
can be selected:
a) Digital Video Port (VP): output only; in 8-bit and 16-bit formats, such as VMI, DMSD (ITU-R BT.601); zoom-video,
with discrete sync signals; ITU-R BT.656; VIP (1.1 and 2.0), with sync encoded in SAV and EAV codes.
b) Transport Stream (TS) capture input: from the peripheral DTV/DVB channel decoder; synchronized by Start Of
Packet (SOP); in byte-parallel or bit-serial protocol.
c) Digitized raw DTV/DVB samples stream output: from internal ADCs; to feed the peripheral DTV/DVB channel
decoder.
d) Program Stream (PS) capture input, e.g. from an external MPEG encoder chip.
e) GPIO: as default (no other function selected); static (no clock); read and write from or to individually selectable
pins; latching ‘strap’ information at system reset time.
f) Peripheral interrupt (INT) input: enabled by interrupt enable register; routed to PCI interrupt (INT_A).
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Table 7
SAA7133HL
Analog interface pins, the SAA7133HL offers an interface for analog video and audio signals. The related
analog supply pins are included in this table
SYMBOL
PIN
TYPE
DESCRIPTION
XTALI
62
CI
quartz oscillator input: 32.11 or 24.576 MHz
XTALO
63
CO
quartz oscillator output
LEFT2
94
AI
analog audio stereo left 2 input or mono input
VDDA
95
AS
analog supply voltage (3.3 V)
LEFT1
96
AI
analog audio stereo left 1 input or mono input; default analog pass-through
to pin OUT_LEFT after reset
VSSA
97
AG
analog ground (for audio)
RIGHT1
98
AI
analog audio stereo right 1 input or mono input; default analog pass-through
to pin OUT_RIGHT after reset
VREF0
99
AR
analog reference ground for audio Sigma Delta ADC; to be connected VSSA
RIGHT2
100
AI
analog audio stereo right 2 input or mono input
VREF1
101
AR
analog reference voltage for audio Sigma Delta ADC; to be connected to
VDDA and via a 220 nF capacitor to pin VREF0
VREF2
102
AR
analog reference voltage for audio Sigma Delta ADC; to be supported with
two parallel capacitors of 47 and 0.1 µF to VSSA
OUT_RIGHT
103
AO
analog audio stereo right channel output; 1 V (RMS) line-out, feeding the
audio loop back cable via a coupling capacitor of 2.2 µF
OUT_LEFT
104
AO
analog audio stereo left channel output; 1 V (RMS) line-out, feeding the
audio loop back cable via a coupling capacitor of 2.2 µF
PROP_RST
105
AO
analog output for test and debug purpose
SIF
106
AI
sound IF input from TV tuner (4.5 to 9.2 MHz); coupling capacitor of 47 pF
after the termination with 50 Ω
VREF3
107
AR
analog reference voltage for audio FIR-DAC and SCART audio input buffer;
to be supported with two parallel capacitors of 47 and 0.1 µF to VSSA
VSSA
108
AG
analog ground
CV2_C
109
AI
composite video input (mode 2) or C input (modes 6 and 8)
VDDA
110
AS
analog power supply (3.3 V)
VREF4
111
AR
analog reference voltage; to be supported with a capacitor of 220 nF VSSA
DRCV_Y
112
AR
differential reference connection (for CV0 and CV1); to be supported with a
capacitor of 47 nF to VSSA
VSSA
113
AG
analog ground
CV0_Y
114
AI
composite video input (mode 0) or Y input (modes 6 and 8)
VDDA
115
AS
analog supply voltage (3.3 V)
CV1_Y
116
AI
composite video input (mode 1) or Y input (modes 7 and 9)
DRCV_C
117
AR
differential reference connection (for CV2, CV3 and CV4); to be supported
with a capacitor of 47 nF to VSSA
CV3_C
118
AI
composite video input (mode 3) or C input (modes 7 and 9)
VSSA
119
AG
analog ground
CV4
120
AI
composite video input (mode 4)
2003 Feb 04
12
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
6.3
SAA7133HL
Pin type
Table 8
Characteristics of pin types and remarks
PIN TYPE
DESCRIPTION
AG
analog ground
AI
analog input; video, audio and sound
AO
analog output
AR
analog reference support pin
AS
analog supply voltage (3.3 V)
CI
CMOS input; 3.3 V signal level (not 5 V tolerant)
CO
CMOS output; 3.3 V signal level (not 5 V tolerant)
GI
digital input (GPIO); 3.3 V signal level (5 V tolerant)
GIO
digital input/output (GPIO); 3.3 V signal level (5 V tolerant)
GO
digital output (GPIO); 3.3 V signal level (5 V tolerant)
I
JTAG test input
IO2
digital input and output of the I2C-bus interface; 3.3 and 5 V compatible, auto-adapting
O
JTAG test output
O/D
open-drain output (for certain PCI pins); multiple clients can drive LOW at the same time,
wired-OR, floating back to 3-state over several clock cycles
PI
input according to PCI requirements
PIO
input and output according to PCI requirements
PO
output according to PCI requirements
S/T/S
sustained 3-state (for certain PCI pins); previous owner drives HIGH for one clock cycle before
leaving to 3-state
T/S
3-state I/O according to PCI requirements; bi-directional
VG
ground for digital supply
VS
supply voltage (3.3 V)
With overscore or #
this pin or ‘signal’ is active LOW, i.e. the function is ‘true’ if the logic level is LOW
2003 Feb 04
13
Philips Semiconductors
Product specification
103 OUT_RIGHT
104 OUT_LEFT
105 PROP_RST
106 SIF
108 VSSA
107 VREF3
109 CV2_C
111 VREF4
110 VDDA
113 VSSA
112 DRCV_Y
SAA7133HL
115 VDDA
114 CV0_Y
116 CV1_Y
117 DRCV_C
119 VSSA
118 CV3_C
120 CV4
121 TRST
122 TCK
123 TMS
124 TDO
125 TDI
128 VSSD
127 PCI_RST#
handbook, full pagewidth
126 INT_A
PCI audio and video broadcast decoder
VDDD
1
GNT#
2
102 VREF2
101 VREF1
REQ#
3
100 RIGHT2
AD[31]
4
AD[30]
5
99 VREF0
98 RIGHT1
AD[29]
6
97 VSSA
AD[28]
7
96 LEFT1
AD[27]
8
95 VDDA
AD[26]
9
94 LEFT2
AD[25] 10
93 VSSD
AD[24] 11
92 VDDD
C/BE[3]# 12
91 SDA
IDSEL 13
90 SCL
AD[23] 14
89 GPIO25
AD[22] 15
88 GPIO26
AD[21] 16
87 GPIO27
AD[20] 17
86 GPIO0
AD[19] 18
85 GPIO1
VDDD 19
84 GPIO2
SAA7133HL
VSSD 20
83 GPIO3
AD[18] 21
82 GPIO4
AD[17] 22
81 GPIO5
AD[16] 23
80 GPIO6
C/BE[2]# 24
79 GPIO7
FRAME# 25
78 GPIO8
IRDY# 26
77 GPIO9
TRDY# 27
76 GPIO10
DEVSEL# 28
75 GPIO11
PERR# 30
74 VSSD
73 VDDD
SERR# 31
72 GPIO12
PAR 32
71 GPIO13
C/BE[1]# 33
70 GPIO14
AD[15] 34
69 GPIO15
AD[14] 35
68 GPIO16
AD[13] 36
67 GPIO17
AD[12] 37
66 V_CLK
VDDD 38
65 VDDD
Fig.3 Pin configuration.
2003 Feb 04
14
VSSD 64
XTALO 63
XTALI 62
GPIO18 61
GPIO19 60
GPIO20 59
GPIO21 58
GPIO22 57
GPIO23 56
VSSD 55
VDDD 54
AD[00] 53
AD[01] 52
AD[02] 51
AD[03] 50
AD[04] 49
AD[05] 48
AD[06] 47
AD[07] 46
C/BE[0]# 45
AD[08] 44
AD[09] 43
AD[10] 42
AD[11] 41
VSSD 39
PCI_CLK 40
STOP# 29
MBL704
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7
7.1
SAA7133HL
FUNCTIONAL DESCRIPTION
Overview of internal functions
The SAA7133HL is able to capture TV signals over the PCI-bus in personal computers by a single chip (see Fig.4).
GPIO
handbook, full pagewidth
5 analog
video
inputs
digital
video
output
I 2C-bus
INPUT SELECTION
VIDEO PORT
(DIGITAL)
I 2C-BUS
INTERFACE
CLAMP AND GAIN
CONTROL
transport stream
or
program stream
reset
input
PARALLEL
OR SERIAL
INTERFACE
digital
audio
output
I 2S-BUS
OUTPUT
stereo
output
stereo stereo
input 1 input 2
IF sound
input
ANALOG AUDIO I/O
SIF
ADC
PASS-THROUGH (DEFAULT)
9-BIT ADC 9-BIT ADC
AUDIO
16-BIT
DAC
DECODER
(NTSC, PAL, SECAM)
AUDIO
16-BIT
DAC
AUDIO
16-BIT
ADC
AUDIO
16-BIT
ADC
SIF
DEMOD
PROPAGATE
RESET
LLC
ADAPTIVE
COMB FILTER
FLC
AUDIO
FEATURE
PROCESSING:
INCREDIBLE
MONO OR STEREO
VIDEO SCALER
MATRIX
3-D
GAMMA
RAW VBI
BTSC
EIAJ
FORMAT
SAA7133HL
PROGRAM PROGRAM
SET
SET
VIDEO FIFOS
AUDIO FIFOS
DMA CONTROL
DMA CONTROL
PCI-BUS INTERFACE
BOUNDARY
SCAN TEST
OSCILLATOR
test
x-tal
ACPI POWER
MANAGEMENT
MBL705
PCI-bus
Fig.4 Functional block diagram.
2003 Feb 04
15
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
The SAA7133HL incorporates two 9-bit video ADCs and
the entire decoding circuitry of any analog TV signal:
NTSC, PAL and SECAM, including non-standard signals,
such as playback from a VCR. The adaptive multi-line
comb filter provides superb picture quality, component
separation, sharpness and high bandwidth. The video
stream can be cropped and scaled to the needs of the
application. Scaling down as well as zooming up is
supported in the horizontal and vertical direction, and an
adaptive filter algorithm prevents aliasing artifacts. With
the acquisition unit of the scaler two different ‘tasks’ can be
defined, e.g. to capture video to the CPU for compression,
and write video to the screen from the same video source
but with different resolution, colour format and frame rate.
7.2
Application examples
The SAA7133HL enables PC TV capture applications
both on the PC mother board and on PCI add-on
TV capture cards. Figures 5 and 6 illustrate some
examples of add-on card applications.
Figure 5 shows the basic application to capture video from
analog TV sources. The proposed tuner types incorporate
the RF tuning function and the IF downconversion. Usually
the IF downconversion stage also includes a single
channel and analog sound FM demodulator. The Philips
tuners FI1286 (Japan) and FI1236MK2 (USA and other
NTSC countries) are suitable for M standard. The FM12x6
are special versions for additional FM radio reception. All
types are suited for terrestrial broadcast and for cable
reception. The tuners provide composite video CVBS and
audio as second SIF. These analog video and sound
signals are fed to the appropriate input pins of the
SAA7133HL.
The SAA7133HL contains TV sound stereo decoding from
Sound IF (SIF), for the BTSC and EIAJ stereo sound
standards, FM and AM mono sound and also
non-standard signals. Baseband stereo audio sampling is
also implemented, e.g. for capturing from a camcorder or
other external devices. The audio sampling rate can be
locked to the video frame rate to ensure synchronization
(lip-sync) between the video and audio data flow, e.g. for
storage, compression or time shift viewing applications.
Further analog video input signals, CVBS and/or Y-C, can
be connected via the board back-panel, or the separate
front connectors, e.g. from a camcorder. Accompanying
stereo audio signals can also be fed to the SAA7133HL.
The SAA7133HL incorporates analog audio pass-through
and support for the analog audio loop back cable to the
sound card function.
Video is digitized and decoded to YUV. TV sound is
digitized and decoded. The SAA7133HL is able to decode
stereo audio according to BTSC [also including the
Second Audio Program (SAP)] and stereo/dual audio
according to EIAJ. In addition mono decoding of FM and
AM sound is possible. The digital streams are pumped via
DMA into the PCI memory space.
The decoded video streams are fed to the PCI-bus, and
are also applied to a peripheral streaming interface, in ITU,
VIP or VMI format. A possible application extension is
on-board hardware MPEG compression, or other feature
processing. The compressed data as PS or TS is fed back
through the peripheral interface, in parallel or serial format,
to be captured by the system memory through the
PCI-bus. The Transport Stream (TS) from a DTV/DVB
channel decoder can be captured through the peripheral
interface in the same way.
The SAA7133HL incorporates means for legacy analog
audio signal routing. The on-chip audio DACs convert the
digital decoded stereo signal into analog audio. This
analog audio input signal is fed via an analog audio loop
back cable into the line-in of a legacy sound card.
An external audio signal, that would have otherwise
connected directly to the sound card, is now routed
through the SAA7133HL. This analog pass-through is
enabled as default by a system reset, i.e. without any
driver involvement and before system set-up.
Audio, video and transport streams are collected in a
configurable FIFO with a total capacity of 1 kbyte. The
DMA controller monitors the FIFO filling degree and
master-writes the audio and video stream to the
associated DMA channel. The virtual memory address
space (from OS) is translated into physical (bus)
addresses by the on-chip hardware Memory Management
Unit (MMU).
During the power-up procedure, the SAA7133HL will
investigate the on-board EEPROM to load the board
specific system vendor ID and board version ID into the
related places of the PCI configuration space. The board
vendor can store other board specific data in the EEPROM
that is accessible via the I2C-bus.
The application of the SAA7133HL is supported by
reference designs and a set of drivers for the Windows
operating system (Video for Windows and Windows Driver
Model compliant).
2003 Feb 04
SAA7133HL
16
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook,
handbook,full
fullpagewidth
pagewidth
TV CAPTURE PCI CARD
TV cable
or
terrestrial
TV TUNER AND
IF-PLL
I 2C-bus
SIF
CVBS
analog
audio
loop back
cable
CVBS
S-video
audio
DECODER FOR
TV SOUND AND
TV VIDEO
SOUND
CARD
line-in
DMA MASTER
INTO PCI
I 2C-BUS EEPROM
SYSTEM
VENDOR ID
SAA7133HL
PCI-bus:
digital video, digital audio, raw VBI, TS, PS
SOUTH
BRIDGE
NORTH
BRIDGE
AGP
VGA AND
LOCAL MEMORY
ISA
SYSTEM
MEMORY
FSB
CPU AND
CACHE MEMORY
MBL708
Fig.5 Basic TV capture with BTSC and EIAJ stereo decoding.
2003 Feb 04
17
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
Figure 6 shows an application extension with VSB channel
decoding for DTV-ATSC or peripheral MPEG encoding.
The packet structure is maintained in a well-defined buffer
structure in the system memory, and therefore can easily
be sorted (de-multiplexed) by the CPU for proper MPEG
decoding.
A combi-tuner, e.g. Philips NTSC tuner FM1236, provides
a dedicated DTV-IF signal that can be routed directly to the
channel decoder device, which converts also the decoded
signal into a DTV (or BS-digital) Transport Stream (TS).
Alternatively, an external MPEG encoder chip can be
inserted into the data path. This device gets the video data
in ITU-R BT.656 format and the audio data in I2S format
from the SAA7133HL and gives back the MPEG encoded
program stream to the SAA7133HL.
The SAA7133HL captures this TS via the dedicated
peripheral interface into the configurable internal FIFO for
DMA into the PCI memory space.
handbook, full pagewidth
SAA7133HL
HYBRID TV CAPTURE PCI CARD
analog TV cable
or terrestrial
and
DTV-ATSC terrestrial
IF
TV TUNER
DIGITAL
IF-PLL
DTV-VSB
CHANNEL
DECODER (1)
I 2C-bus
IF
ANALOG IF-PLL
SIF
CVBS
TS
PS
CVBS
S-video
audio
ITU
DECODER FOR
TV SOUND AND
TV VIDEO
I2S
line-in
MPEG AV
(1)
ENCODER
SOUND
CARD
analog audio
loop back cable
DMA MASTER
INTO PCI
I 2C-BUS EEPROM
SYSTEM
VENDOR ID
SAA7133HL
PCI-bus:
digital video, digital audio, raw VBI, TS, PS
SOUTH
BRIDGE
NORTH
BRIDGE
AGP
VGA AND
LOCAL MEMORY
ISA
SYSTEM
MEMORY
FSB
CPU AND
CACHE MEMORY
MBL707
(1) Alternatively.
Fig.6 Hybrid TV capture board with MPEG encoding or DTV channel decoder, e.g. VSB-ATSC.
2003 Feb 04
18
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.3
Software support
7.3.1
All platform related drivers support the following:
• Video preview and capture interfaces
DEVICE DRIVER
• Audio control and audio capture interfaces
A complex and powerful software packet is provided for all
PCI chips from the SAA713x family. This packet includes
plug-and-play driver and capture driver installations for all
commonly used 32-bit Windows platforms.
Table 9
SAA7133HL
• Custom application interface, that enables the
development of specialized applications in cases where
the published direct show Application Programmers
Interface (API) may not be sufficient.
Microsoft Operation System (MS-OS) support
MS-OS
DRIVER SUPPORT
Windows 95
Device access is contained within a VxD. The Video for Windows (VfW) capture driver interface is a
16-bit user-mode interface.
Windows NT4
Device access is contained in a kernel-mode driver. The VfW capture driver interface is a 32-bit
user-mode interface.
Windows 98 and Device access is contained in a kernel streaming Windows Driver Model (WDM) driver. The
Windows ME
capture driver interface is based on Microsoft ‘direct show’ technology.
Windows 2000
The driver is binary-compatible with the Windows 98/ME driver and validated for passing the
Microsoft WHQL test for getting the Win2000 driver signature.
Windows XP
The driver is binary-compatible with the Windows 98/ME driver and validated for passing the
Microsoft WHQL test for getting the WinXP driver signature.
7.3.2
SUPPORTING WDM
VBI, together with a crossbar for input source selection
and a TV audio filter for controlling the TV sound
standards. The TV tuner filter is a separate child driver and
supports the control of all common Philips MK2 and MK3
tuners. The typical filter structure is shown in Fig.7.
The WDM driver is implemented as a stream class
mini-driver and provides a Kernel Streaming (KS) filter with
output pins for audio, video preview, video capture and
handbook, full pagewidth
IAMTVTuner
Country / standard
TV / FM Radio
Channelselect
Autoscan
Antenna / cable
IAMCrossbar
Video input channel
Audio input channel
Link related stream
IAMTVAudio
Mono / stereo
Dual language
SAP
IAMAnalogVideoDecoder
Timing constant
Video standard
Signal lock status
IAMVideoProcAmp
Brightness, contrast, saturation
Hue, sharpness
IAudio7134
Enable loopback
TV AUDIO
TV TUNER
external audio input
video preview
CROSSBAR
CVBS input
S-Video input
SAA713x
CAPTURE
DRIVER
video capture
VBI capture
audio capture
MBL700
Fig.7 WDM capture driver filters.
2003 Feb 04
19
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.3.3
SOFTWARE DEVELOPMENT KIT FOR CUSTOMER
COM based class library supports interfaces for c++ as
well as for Visual Basic and provides methods to:
RELATED APPLICATIONS
• Select one SAA713x device (in case that more than one
device is plugged into the PC)
The SAA7133HL device is controlled by a LOW-level
Hardware Abstraction Layer (HAL), contained within a
device driver. This platform-independent HAL initializes
and controls the device and responds to interrupts
forwarded by a device driver. The HAL consists of objects
representing the major device components (video and
audio decoder, GPIO pins, I2C-bus master) and also
provides classes that can be created to represent buffers
and active streams.
• Capture video into a fixed buffer (including clipping)
• Capture audio (baseband stereo input or decoded
TV sound) over the PCI-bus into the memory (for
PC-VCR application)
• Capture video to a stream of buffers over VBI
• Capture transport streams (MPEG data) from a channel
decoder chip (OFDM, VSB, QAM) for supporting digital
TV applications, or from an on-board MPEG encoder
chip that is fed by the video output port of the SAA713x
The driver provides operating system services and
forwards interrupts to the HAL. A set of proxy services
extends the HAL interface out into user-mode. This is
exposed to applications in the form of a COM interface,
34COM.dll. Figure 8 shows these layers of software.
• Capture raw VBI sample stream to a stream of buffers
over the PCI-bus
• Access to the I2C-bus master and GPIO for controlling
other peripheral circuits.
In addition to the capture driver, this API provides the
whole range of functionality to control the device. This
handbook, full pagewidth
SAA7130
SAA7133
SAA7134
URD312.exe
hardware layer
integrated in OS device driver
WDM-CAPTURE
DRIVER
MS-Windows
system layer
driver access
via Microsoft
"DirectShow"
34API.dll
34URD.dll
SAA7135
hardware abstraction layer
3xHAL
WDM
TUNER
DRIVER
SAA7133HL
34COM.dll
MS-Windows layer for
"dynamic link libraries"
<YourTV>.exe
MS-Windows
application layer
MBL701
Fig.8 Software layer structure.
2003 Feb 04
20
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.4
The API adapts to the different kernel-mode
implementations, so that one common 34COM can be
used on all Windows operating systems in the same way
(see Fig.9).
7.4.1
All necessary header and library files are provided.
3xHAL
3xHAL
NT4.0
WDM
VxD
PCI CONFIGURATION REGISTERS
The PCI specification defines a structure of the PCI
configuration space that is investigated during the boot-up
of the system. The configuration registers (see Table 10)
hold information essential for plug-and-play, to allow
system enumeration and basic device set-up without
depending on the device driver, and support association of
the proper software driver. Some of the configuration
information is hard-wired in the device; some information
is loaded during the system start-up.
The provided sample code will introduce the user into
working with this interface.
3xHAL
PCI interface
The PCI interface of the SAA7133HL complies with the
“PCI specification 2.2” and supports power management
and Advanced Configuration and Power Interface (ACPI)
as required by the “PC Design Guide 2001”.
The SDK for the SAA7133HL contains the detailed
description of the important software components such as
API documentation for streaming, I2C-bus and GPIO
access.
handbook, halfpage
SAA7133HL
The device vendor ID is hard coded to 11 31H, which is the
code for Philips as registered with PCI-SIG.
The device ID is hard coded to 71 33H.
34API.dll
During power-up, initiated by PCI reset, the SAA7133HL
fetches additional system information via the I2C-bus from
the on-board EEPROM, to load actual board type specific
codes for the system vendor ID, sub-system ID (board
version) and ACPI related parameters into the
configuration registers.
34COM.dll
MBL699
Fig.9 Adaptation to different kernels.
Table 10 PCI configuration space registers
REGISTER ADDRESS
(HEX)
VALUE
(HEX)
Device vendor ID
00 and 01
11 31
for Philips
Device ID
02 and 03
71 33
for SAA7133HL
Revision ID
08
F0
Class code
09 to 0B
04 80 00
Memory address space
required
10 to 13
XXXXXXXX XXXXXXXX
XXXXX000 00000000 (b)
System (board) vendor ID
2C and 2D
loaded from EEPROM
Sub-system
(board version) ID
2E and 2F
loaded from EEPROM
FUNCTION
Note
1. X = don’t care.
2003 Feb 04
21
REMARK
or higher
multimedia
2 kbytes; note 1
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.4.2
DTV/DVB Transport Streams (TS) and MPEG streams
(PS and TS) into the PCI memory. Each DMA channel
contains inherently the definition of two buffers in the
system address space, e.g. for odd and even fields in case
of interlaced video, or two alternating buffers to capture
continuous audio stream.
ACPI AND POWER STATES
The “PCI specification 2.2” requires support of “Advanced
Configuration and Power Interface specification 1.0”
(ACPI); more details are defined in the “PCI Power
Management Specification 1.0”.
The power management capabilities and power states are
reported in the extended configuration space. The main
purpose of ACPI and PCI power management is to tailor
the power consumption of the device to the actual needs.
The DMA channels share in time and space one common
FIFO pool of 256 Dwords (1024 bytes) total. It is freely
configurable how much FIFO capacity is associated with
which DMA channel. Furthermore, a preferred minimum
burst length can be programmed, i.e. the amount of data
to be collected before the request for the PCI-bus is
issued. This means that latency behaviour per DMA
channel can be tailored and optimized for a given
application.
The SAA7133HL supports all four ACPI device power
states (see Table 11).
The pin PROP_RST of the peripheral interface is switched
active LOW during the PCI reset procedure, and for the
duration of the D3-hot state. Peripheral devices on board
of the add-on card should use the level of this
signal PROP_RST to switch themselves in any
power-save mode (e.g. disable device) and reset to default
settings on the rising edge of signal PROP_RST. The
length of signal PROP_RST is programmable.
7.4.3
SAA7133HL
In the event that the FIFO of a certain channel overflows
due to latency conflict on the bus, graceful overflow
recovery is applied. The mount of data that gets lost
because it could not be transmitted, is monitored (counted)
and the PCI-bus address pointer is incremented
accordingly. Thus new data will be written to the correct
memory place, after the latency conflict is resolved.
DMA AND CONFIGURABLE FIFO
The SAA7133HL supports seven DMA channels to
master-write captured active video, audio, raw VBI and
Table 11 Power management table
POWER STATE
DESCRIPTION
D0
Normal operation: all functions accessible and programmable. The default setting after reset and
before driver interaction (D0 un-initialized) switches most of the circuitry of the SAA7133HL into
the power-down mode, effectively such as D3-hot.
D1
First step of reduced power consumption: no functional operation; program registers are not
accessible, but content is maintained. Most of the circuitry of the SAA7133HL is disabled with
exception of the crystal and real-time clock oscillators, so that a quick recovery from D1 to D0 is
possible.
D2
Second step of reduced power consumption: no functional operation; program registers are not
accessible, but content is maintained. All functional circuitry of the SAA7133HL is disabled,
including the crystal and clock oscillators.
D3-hot
Lowest power consumption: no functional operation. The content of the programming registers
gets lost and is set to default values when returning to D0.
Table 12 FIFO configuration: typical example
DMA
DATA STREAM
DATA RATE
FIFO SIZE PROGRAMMABLE TO
TOLERANT TO LATENCY OF
1
Y
13.5 Mbytes/s
384 bytes
28.4 µs
2
U
6.75 Mbytes/s
256 bytes
37.9 µs
3
V
6.75 Mbytes/s
256 bytes
37.9 µs
4
audio
160 kbytes/s
128 bytes
800 µs
2003 Feb 04
22
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
Table 13 FIFO configuration: fastidious example
DMA
DATA STREAM
DATA RATE
FIFO SIZE PROGRAMMABLE TO
TOLERANT TO LATENCY OF
1
raw VBI
27 Mbytes/s
640 bytes
22.5 µs
active video,
unscaled YUV 4 : 2 : 2
2
−
−
−
−
3
MPEG stream
9.5 Mbit/s
256 bytes
202.1 µs
4
audio
192 kbytes/s
128 bytes
583.3 µs
7.4.4
The association between the virtual (logic) address space
and the fragmented physical address space is defined in
page tables (system files); see Fig.10. The SAA7133HL
incorporates hardware support (MMU) to translate virtual
to physical addresses on the fly, by investigating the
related page table information. This hardware support
reduces the demand for real-time software interaction and
interrupt requests, and therefore saves system resources.
VIRTUAL AND PHYSICAL ADDRESSING
Most operating systems allocate memory to requesting
applications for DMA as continuous ranges in virtual
address space. The data flow over the PCI-bus points to
physical addresses, usually not continuous and split in
pages of 4 kbytes (Intel architecture, most UNIX systems,
Power PC).
physical memory
handbook, full pagewidth
real-time streams
00000H
FIFO
POOL
00007H
DMA DEFINITIONS
(VIRTUAL ADDRESS SPACE)
page table
000H
0000FH
007H
00001000H
00008000H
00009000H
0000A000H
0000D000H
00011000H
00014000H
00016000H
0001E000H
DMA
ADDRESS
GENERATION
VIRTUAL
TO
PHYSICAL
ADDRESS
TRANSLATION
00017H
PCI
TRANSFER AND
CONTROL
015H
0001FH
physical address space on PCI
= allocated memory space
MHB996
= page table
Fig.10 MMU implementation (shown bit width indication is valid for 4 kbytes mode).
2003 Feb 04
23
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.4.5
TV signals that are broadcasted usually conform fairly
accurately to the standards. Transmission over the air or
through a cable can distort the signal with noise, echoes,
crosstalk or other disturbances.
STATUS AND INTERRUPTS ON PCI-BUS
The SAA7133HL provides a set of status information
about internal signal processing, video and audio standard
detection, peripheral inputs and outputs (pins GPIO) and
behaviour on the PCI-bus. This status information can be
conditionally enabled to raise an interrupt on the PCI-bus,
e.g. completion of a certain DMA channel or buffer, or
change in a detected TV standard, or the state of
peripheral devices.
Video signals from local consumer equipment, e.g. VCR,
camcorder, camera, game console, or even DVD player,
often do not follow the standard specification very
accurately.
Playback from video tape cannot be expected to maintain
correct timing, especially not during feature mode (fast
forward, etc.).
The cause of an issued interrupt is reported in a dedicated
register, even if the original condition has changed before
the system was able to investigate the interrupt.
7.5
SAA7133HL
Tables 14, 15 and 16 list some characteristics of the
various TV standards.
Analog TV standards
The SAA7133HL decodes all colour TV standards and
non-standard signals as generated by video tape
recorders e.g. automatic video standard detection can be
applied, with preference options for certain standards, or
the decoder can be forced to a dedicated standard.
Analog TV signals are described in three categories of
standards:
• Basic TV systems: defining frame rate, number of lines
per field, levels of synchronization signals, blanking,
black and white, signal bandwidth and the
RF modulation scheme
The SAA7133HL incorporates BTSC and EIAJ stereo
decoding and TV mono sound decoding on chip.
Baseband stereo audio can be fed into the device as
analog signal.
• Colour transmission: defining colour coding and
modulation method
• Sound and stereo: defining coding for transmission.
Table 14 Overview of basic TV standards
MAIN
PARAMETERS
STANDARD
UNIT
M
N
B
G, H
I
D/K
L
RF channel width
6
6
7
7
8
7
8
MHz
Video bandwidth
4.2
4.2
5
5
5.5
6
6
MHz
1st sound carrier
4.5, FM
4.5, FM
5.5, FM
5.5, FM
6.0, FM
6.5, FM
6.5, AM
MHz
Field rate
59.94006
50
50
50
50
50
50
Hz
Lines per frame
525
625
625
625
625
625
625
−
Line frequency
15.734
15.625
15.625
15.625
15.625
15.625
15.625
kHz
ITU clocks per line
1716
1728
1728
1728
1728
1728
1728
−
Sync, set-up level
−40, 7.5
−40, 7.5
−43, 0
−43, 0
−43, 0
−43, 0
−43, 0
IRE
Gamma correction
2.2
2.2
2.8
2.8
2.8
2.8
2.8
−
Associated colour
TV standards
NTSC,
PAL
PAL
PAL
PAL
PAL
SECAM,
PAL
SECAM
−
Associated stereo
TV sound systems
BTSC,
EIAJ, A2
BTSC
dual FM,
A2
NICAM
NICAM
NICAM,
A2
NICAM
−
Country examples
USA,
Japan,
Brazil
Argentina
part of
Europe,
Australia
Spain,
Malaysia,
Singapore
UK,
Northern
Europe
China,
Eastern
Europe
France,
Eastern
Europe
−
2003 Feb 04
24
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
Table 15 TV system colour standards
MAIN
PARAMETERS
NTSC M
PAL M
PAL N
PAL
BGHID
SECAM
LDGHK
PAL 4.4
(60 Hz)
UNIT
59.94
59.94
50
50
50
≈60
Hz
525
525
625
625
625
525
−
Chrominance
subcarrier
3.580
3.576
3.582
4.434
4.406
4.250
4.434
MHz
fsc to H ratio
227.5
227.25
229.25
283.75
282
272
n.a.
−
−
−
50
50
−
−
n.a.
Hz
−
−
Field rate
Lines per frame
fsc offset (PAL)
Alternating phase
Country
examples
no
yes
yes
yes
USA,
Japan,
Asia-Pacific
Brazil
Middle and
South
America
Europe,
Commonwealth,
China
France,
Eastern Europe,
Africa, Middle East
yes
−
VCR
transcoding
NTSC-tape
to PAL
−
Table 16 TV stereo sound standards
MAIN
PARAMETERS
ANALOG SYSTEMS
DIGITAL CODING
UNIT
MONO
Stereo coding
scheme
−
2nd language
BTSC
EIAJ
A2 (DUAL FM)
internal carrier (mpx)
NICAM
2-Carrier Systems (2CS)
−
AM
FM
2nd FM carrier
DQPSK on FM
−
mono SAP on
internal FM
as alternative
to stereo
as alternative to
stereo
mono on 1st carrier
−
De-emphasis
75
75, dbx-TV
Noise
Reduction
system
50
50 or 75
50 or J17
µs
Audio bandwidth
15
15
15
15
15
kHz
worldwide
USA, South
America
Japan
part of Europe,
Korea
part of Europe, China
−
Country
examples
2003 Feb 04
25
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.6
7.6.1
Video processing
The video decoder of the SAA7133HL incorporates an
automatic standard detection, that does not only
distinguish between 50 and 60 Hz systems, but also
determines the colour standard of the video input signal.
Various preferences (‘look first’) for automatic standard
detection can be chosen, or a selected standard can be
forced directly.
ANALOG VIDEO INPUTS
The SAA7133HL provides five analog video input pins:
• Composite video signals (CVBS), from tuner or external
source
• S-video signals (pairs of Y-C), e.g. from camcorder
• DTV/DVB ‘low-IF’ signal, from an appropriate DTV or
combi-tuner.
7.6.4
Comb filtering achieves higher luminance bandwidth,
resulting in sharper picture and detailed resolution. Comb
filtering further minimizes colour crosstalk artifacts, which
would otherwise produce erroneous colours on detailed
luminance structures.
VIDEO SYNCHRONIZATION AND LINE-LOCKED CLOCK
The SAA7133HL recovers horizontal and vertical
synchronization signals from the selected video input
signal, even under extremely adverse conditions and
signal distortions. Such distortions are ‘noise’, static or
dynamic echoes from broadcast over air, crosstalk from
neighbouring channels or power lines (hum), cable
reflections, time base errors from video tape play-back and
non-standard signal levels from consumer type video
equipment (e.g. cameras, DVD).
The comb filter as implemented in the SAA7133HL is
adaptive in two ways:
• Adaptive to transitions in the picture content
• Adaptive to non-standard signals (e.g. VCR).
The integrated digital delay lines are always exactly
correct, due to the applied unique line-locked sampling
scheme (LLC). Therefore the comb filter does not need to
be switched off for non-standard signals and remains
operating continuously.
The heart of this TV synchronization system is the
generation of the Line-Locked Clock (LLC) of nominal
27 MHz, as defined by ITU-R BT.601. The LLC ensures
orthogonal sampling, and always provides a regular
pattern of synchronization signals, that is a fixed and well
defined number of clock pulses per line. This is important
for further video processing devices connected to the
peripheral video port (pins GPIO). It is very effective to run
under the LLC of 27 MHz, especially for on-board
hardware MPEG encoding devices, since MPEG is
defined on this clock and sampling frequency.
7.6.3
7.6.5
MACROVISION DETECTION
The SAA7133HL detects if the decoded video signal is
copy protected by the Macrovision system. The detection
logic distinguishes the three levels of the copy protection
as defined in rev. 7.01, and are reported as status
information. The Macrovision detection works also for
copy protected video signals, which contain inverted
bursts but no AGC pulses and no pseudo syncs. Those
signals come from some so-called Macrovision-killer
boxes. The decoded video stream is not effected directly,
but application software and Operation System (OS) has
to ensure, that this video stream maintains tagged as ‘copy
protected’, and such video signal would leave the system
only with the reinforced copy protection. The multi-level
Macrovision detection on the video capture side supports
VIDEO DECODING AND AUTOMATIC STANDARD
DETECTION
The SAA7133HL incorporates colour decoding for any
analog TV signal. All colour TV standards and flavours of
NTSC, PAL, SECAM and non-standard signals (VCR) are
automatically recognized and decoded into luminance and
chrominance components, i.e. Y-CB-CR, also known as
YUV.
2003 Feb 04
ADAPTIVE COMB FILTER
The SAA7133HL applies adaptive comb filter techniques
to improve the separation of luminance and chrominance
components in comparison to the separation by a chroma
notch filter, as used in traditional TV colour decoder
technology. The comb filter compares the signals of
neighbouring lines, taking into account the phase shift of
the chroma subcarrier from line to line. For NTSC the
signals of three adjacent lines are investigated, and in the
event of PAL the comb filter taps are spread over four
lines.
Analog anti-alias filters are integrated on chip and
therefore, no external filters are required. The device also
contains automatic clamp and gain control for the video
input signals, to ensure optimum utilization of the ADC
conversion range. The nominal video signal amplitude is
1 V (p-p) and the gain control can adapt deviating signal
levels in the range of +3 dB to −6 dB. The video inputs are
digitized by two ADCs of 9-bit resolution, with a sampling
rate of nominal 27 MHz (the line-locked clock) for analog
video signals.
7.6.2
SAA7133HL
26
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
proper TV re-encoding on the output point, e.g. by Philips
TV encoders SAA712x or SAA7102.
7.6.6
240 lines of an NTSC field to 288 lines to comply with
CCITT video phone formats.
The scaling acquisition definition also includes cropping,
frame rate reduction, and defines the amount of pixels and
lines to be transported through DMA over the PCI-bus.
VIDEO SCALING
The SAA7133HL incorporates a filter and processing unit
to downscale or upscale the video picture in the horizontal
and vertical dimension, and in frame rate
(see Figs 11 and 12). The phase accuracy of the
re-sampling process is 1⁄64 of the original sample distance.
This is equivalent to a clock jitter of less than 1 ns. The
filter depth of the anti-alias filter adapts to the scaling ratio,
from 10 taps horizontally for scaling ratios close to 1 : 1, to
up to 74 taps for an icon sized video picture.
Two programming pages are available to enable
re-programming of the scaler in the ‘shadow’ of the running
processing, without holding or disturbing the flow of the
video stream. Alternatively, the two programming pages
can be applied to support two video destinations or
applications with different scaler settings, e.g. firstly to
capture video to CPU for compression (storage, video
phone), and secondly to preview the picture on the monitor
screen. A separate scaling region is dedicated to capture
raw VBI samples, with a specific sampling rate, and be
written into its own DMA channel.
Most video capture applications will typically require for
downscaling. But some zooming is required for conversion
of ITU sampling to square pixel (SQP), or to convert the
handbook, full pagewidth
VBI first sample
VBI last sample
1st field (odd, FID = 0)
VBI first line
VBI last line
SAA7133HL
VBI DMA
1st buffer (A)
sample rate
VBI region, raw samples
2nd buffer (A)
video region
- cropped
- scaled
scaling
active video area
2nd field (even, FID = 1)
video DMA (A)
e.g. interlaced
sample rate
VBI region, raw samples
1st buffer (upper field)
video first line
2nd buffer (lower field)
video region
- cropped
- scaled
scaling
video last line
active video area
MHB997
video first pixel
video last pixel
The capture acquisition for scaling and DMA has separate programming
parameters for VBI and video region and associated DMA channels.
Fig.11 Scaler processing with DMA interfacing.
2003 Feb 04
27
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
handbook, full pagewidth
1st field (odd, FID = 0)
VBI region, raw samples
VBI DMA
sample rate
1st buffer (A)
video region (A) - cropped
2nd buffer (A)
scaling
task "A"
3rd buffer (B)
4th buffer (B)
active video area
2nd field (even, FID = 1)
VBI region, raw samples
sample rate
video DMA (A)
e.g. interlaced
video region (A) - cropped
1st buffer (upper field)
scaling
2nd buffer (lower field)
active video area
3rd field (odd, FID = 0)
VBI region, raw samples
sample rate
video region (B)
- skipped for field rate reduction
task "B"
video DMA (B)
e.g. single FID
1st buffer
active video area
4th field (even, FID = 1)
VBI region, raw samples
2nd buffer
(next frame)
sample rate
video region - scaled down CIF
MHB998
scaling
active video area
alternating processing task A/B
Two video capture tasks can be processed in an alternating manner, without
need to reprogram any scaling parameters or DMA definition.
Fig.12 Example of scaler task processing with DMA interfacing.
2003 Feb 04
28
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.6.7
along the line (corresponding to a sampling rate of 27 MHz
divided by two), and a certain relationship from level to
number range (see Fig.13).
VBI DATA
The Vertical Blanking Interval (VBI) is often utilized to
transport data over analog video broadcast. Such data can
closely relate to the actual video stream, or just be general
data (e.g. news). Some examples for VBI data types are:
The video components do not use the entire number
range, but leave some margin for overshoots and
intermediate values during processing. For the raw VBI
samples there is no official specification how to code, but
it is common practice to reserve the lower quarter of the
number range for the sync, and to leave some room for
overmodulation beyond the nominal white amplitude (see
Fig.14).
• Closed Caption (CC) for the hearing impaired (CC, on
line 21 of first field)
• Intercast data [in US coded in North-American
Broadcast Text System (NABTS) format, in Europe in
World Standard Teletext (WST)], to transmit internet
related services, optionally associated with actual video
program content
The automatic clamp and gain control at the video input,
together with the automatic chroma gain control of the
SAA7133HL, ensures that the video components stream
at the output comply to the standard levels. Beyond that
additional brightness, contrast, saturation and hue control
can be applied to satisfy special needs of a given
application. The raw VBI samples can be adjusted
independent of the active video.
• Teletext, transporting news services and broadcast
related information, Electronic Program Guide (EPG),
widely used in Europe (coded in WST format)
• EPG, broadcaster specific program and schedule
information, sometimes with proprietary coding scheme
(pay service), usually carried on NABTS, WST, Video
Programming Service (VPS), or proprietary data coding
format
The SAA7133HL incorporates the YUV-to-RGB matrix
(optional), the RGB-to-YUV matrix and a three channel
look-up table in between (see Fig.15). Under nominal
settings, the RGB space will use the same number range
as defined by the ITU and shown in Fig.13a for luminance,
between 16 and 235. As graphic related applications are
based on full-scale RGB, i.e. 0 to 255, the range can be
stretched by applying appropriate brightness, contrast and
saturation values. The look-up table supports gamma
correction (freely definable), and allows other non-linear
signal transformation such as black stretching.
• Video Time Codes (VTC) as inserted in camcorders
e.g. use for video editing
• Copy Guard Management System (CGMS) codes, to
indicate copy protected video material, sometimes
combined with format information [Wide Screen
Signalling (WSS)].
This information is coded in the unused lines of the vertical
blanking interval, between the vertical sync pulse and the
active visible video picture. So-called full-field data
transmission is also possible, utilizing all video lines for
data coding.
The analog TV signal applies a quite strong gamma
pre-compensation (2.2 for NTSC and 2.8 for PAL).
As computer monitors exhibit a gamma (around 2.5), the
difference between gamma pre-compensation and actual
screen gamma has to be corrected, to achieve best
contrast and colour impression.
The SAA7133HL supports capture of VBI data by the
definition of a VBI region to be captured as raw VBI
samples, that will be sliced and decoded by software on
the host CPU. The raw sample stream is taken directly
from the ADC and is not processed or filtered by the video
decoder. The sampling rate of raw VBI can be adjusted to
the needs of the data slicing software.
7.6.8
The SAA7133HL offers a multitude of formats to write
video streams over the PCI-bus: YUV and RGB colour
space, 15-bit, 16-bit, 24-bit and 32-bit representation,
packed and planar formats. For legacy requirements
(VfW) a clipping procedure is implemented, that allows the
definition of 8 overlay rectangles. This process can
alternatively be used to associate ‘alpha’ values to the
video pixels.
SIGNAL LEVELS AND COLOUR SPACE
Analog TV video signals are decoded into its components
luminance and colour difference signals (YUV) or in its
digital form Y-CB-CR. ITU-R BT.601 defines 720 pixels
2003 Feb 04
SAA7133HL
29
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
+255
+235
+128
white
LUMINANCE 100%
SAA7133HL
+255
+240
blue 100%
+255
+240
red 100%
+212
blue 75%
+212
red 75%
+128
colourless
+128
colourless
U-COMPONENT
+16
black
V-COMPONENT
+44
yellow 75%
+44
cyan 75%
+16
yellow 100%
+16
cyan 100%
0
0
0
MGC634
a. Y output range.
b. U output range (CB).
c. V output range (CR).
Fig.13 Nominal digital levels for YUV (Y, CB and CR) in accordance with ITU-R BT.601.
+255
+255
+209
white
+199
LUMINANCE
+71
+60
LUMINANCE
black
black shoulder
+60
black shoulder = black
SYNC
SYNC
1
white
1
sync bottom
sync bottom
MGD700
a. Sources containing 7.5 IRE black
level offset (e.g. NTSC M).
b. Sources not containing black
level offset.
Fig.14 Nominal digital levels for CVBS and raw VBI samples.
2003 Feb 04
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Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
handbook, full pagewidth
SAA7133HL
three channel non-linear transformation
Y
U
V
R
YUV
to
RGB
matrix
R
G
G
B
B
Y
RGB
to
YUV
matrix
U
V
MHB999
Fig.15 Colour space conversion and look-up table.
7.6.9
• Raw DTV/DVB sample stream: 9-bit wide data, clocked
with a copy of signal X_CLK_IN.
VIDEO PORT, ITU AND VIP CODES
The decoded and/or scaled video stream can be captured
via PCI-DMA to the system memory, and/or can be made
available locally through the video side port (VP), using
some of the GPIO pins. Two types of applications are
intended:
The VIP standard is designed to transport scaled video
and discontinuous data stream by allowing the insertion of
‘00’ as marker for empty clock cycles. For the other video
port standards, a data valid flag or gated clock can be
applied.
• Streaming real-time video to a video side port at the
VGA card, e.g. via ribbon cable over the top
7.7
• Feeding video stream to a local MPEG compression
device on the same PCI board, e.g. for a time shift
viewing application.
7.7.1
TV sound
TV SOUND STEREO DECODING
The SAA7133 HL incorporates TV sound decoding from
the Sound Intermediate Frequency (SIF) signal. The
analog SIF signal is taken from the tuner, digitized and
digitally FM or AM demodulated. If one of the supported
TV sound standards is found (BTSC, EIAJ, mono), the
pilot tone is investigated (mono, stereo, dual) and the
signal is properly stereo or dual decoded.
The video port of the SAA7133HL supports the following
8 and 16-bit wide YUV video signalling standards
(see Table 6):
• VMI: 8-bit wide data stream, clocked by LLC = 27 MHz,
with discrete sync signals HSYNC, VSYNC and
VACTIVE
• ITU-R BT.656, parallel: 8-bit wide data stream, clocked
by LLC = 27 MHz, synchronization coded in SAV and
EAV codes
The SAA7133HL supports the stereo audio standards
BTSC (+SAP) and EIAJ and all mono standards on-chip.
dbx-TV Noise Reduction and de-emphasis filters are also
integrated.
• VIP 1.1 and 2.0: 8-bit or 16-bit wide data stream,
clocked by LLC = 27 MHz, synchronization coded in
SAV and EAV codes (with VIP extensions)
• Zoom Video (ZV): 16-bit wide pixel stream, clocked by
LLC/2 = 13.5 MHz, with discrete sync signals HSYNC
and VSYNC
The digital FM demodulation maintains stable phase
accuracy, resulting into improved channel separation,
compared to traditional analog demodulation. TV sound
decoding operates at a 32 kHz sample rate, resulting in an
audio bandwidth of up to 15 kHz.
• ITU-R BT.601 direct (DMSD): 16-bit wide pixel stream,
clocked by LLC = 27 MHz, with discrete sync signals
HSYNC, VSYNC/FID and CREF
The SAA7133HL incorporates baseband stereo audio
ADCs, to capture sound signals associated with external
video sources, e.g. camera, camcorder or VCR.
2003 Feb 04
31
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
frequency (FLC), so that a programmable but constant
number of audio samples is associated with each video
frame. This is especially important for video editing,
compression and recording, e.g. time shift viewing. There
is no drift between the audio and video streams, not even
for longer recording times.
For concurrent capture of audio and video signals, it is
important to maintain synchronization between the two
streams. The spoken word and other sound should match
the displayed picture within a video frame (1/30 s
respectively 1/25 s ‘lip-sync’). The SAA7133HL has special
means to lock the audio sampling clock to the video frame
Table 17 TV sound decoding, supported feature processing and sampling rate
INPUT AND SOUND STANDARD
SUPPORTED
FUNCTION
SIF FROM TUNER
BTSC
EIAJ
BASEBAND AUDIO
FM RADIO OTHER AM/FM
L OR R
L AND R
Decoding
mono or
mono or stereo
stereo or dual
and SAP(1)
mono or
stereo
mono
mono or 2 × mono
stereo
Analog audio output
to loop back cable
mono or stereo
mono or
or SAP
stereo or dual
mono or
stereo
mono
mono or 2 × mono
stereo(2)
mono or stereo
mono or
or SAP
stereo or dual
mono or
stereo
mono
mono or 2 × mono
stereo
I2S output
Signal
Sample rate
32 kHz
32, 44.1 or 48 kHz
PCI (audio streaming)
Signal
mono or stereo
mono or
and/or SAP
stereo or dual
Sample rate
32 kHz
mono or
stereo
mono
32 or 48 kHz
mono or 2 × mono
stereo
32, 44.1 or 48 kHz
Feature processing
Volume and
balance
X
X
X
X
X
X
Bass and treble
X
X
X
X
X
X
Incredible Stereo
X
X
X
−
−
X
Incredible Mono
if SAP
either of dual
−
X
X
−
Notes
1. Simultaneous decoding of stereo and SAP. dbx-TV Noise Reduction either on stereo or on SAP.
2. Default pass-through of L1 and R1.
7.7.2
ADDITIONAL AUDIO FEATURES
The SAA7133HL provides several audio control and enhancement features, like
• Bass, treble, balance and volume control
• Automatic volume levelling (this algorithm lowers louder parts, e.g. commercials)
• Incredible Mono (this algorithm adds stereo-like sound impression to monaural audio signals)
• Incredible Stereo (this algorithm makes stereo sound impression ‘wider’. The distance between the two loudspeakers
seems to become larger)
• FM radio stereo decoding.
2003 Feb 04
32
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
7.7.3
The SAA7133HL supports also capturing of MPEG
elementary and program streams. This expands the
connectivity to MPEG encoders like the Philips
SAA6752HS or similar devices.
AUDIO INTERFACES
The SIF input can handle the sound subcarrier signal from
the tuner. Baseband audio signals can be captured
through the stereo line-in inputs LEFT1, RIGHT1, LEFT2
and RIGHT2 or the I2S-bus input.
7.9
The decoded and possibly enhanced digital audio stream
can be captured through dedicated DMA into the PCI
memory space, or to the output in I2S-bus format, e.g. to a
peripheral digital sound amplifier. The third way is to
re-convert the audio signal to analog via the integrated
audio stereo DACs and feed it directly through the loop
back cable to the sound card or to headphones for local
monitoring.
7.9.1
The I2C-bus interface is multi-master capable and can
assume slave operation too. This allows application of the
device in the stand-alone mode, i.e. with the PCI-bus not
connected. Under the slave mode, all internal
programming registers can be reached via the I2C-bus
with exception of the PCI configuration space.
DEFAULT ANALOG AUDIO PASS-THROUGH AND LOOP
Most operating systems are prepared to deal with audio
input at only one single entry point, namely at the sound
card function. Therefore the sound associated with video
has to get routed through the sound card.
7.9.2
The SAA7133HL supports analog audio pass-through and
the loop back cable on-chip. No external components are
required. The audio signal, that was otherwise connected
to the sound card line-in, e.g. analog sound from a
CD-ROM drive, has to be connected to one of the inputs of
the SAA7133HL. By default, after a system reset and
without involvement of any driver, this audio signal is
passed through to the analog audio output pins, that will
feed the loop back cable to the sound card line-in
connector. The AV capture driver has to open the default
pass-through and switch in the TV sound signal by will.
PROPAGATE RESET
The PCI system reset and ACPI power management
state D3 is propagated to peripheral devices by the
dedicated pin PROP_RST. This signal is switched to
active LOW by reset and D3, and is only switched HIGH
under control of the device driver ‘by will’. The intention is
that peripheral devices will use signal PROP_RST as
Chip-Enable (CE). The peripheral devices should enter a
low power consumption state if pin PROP_RST = LOW,
and reset into default setting at the rising edge.
7.9.3
DTV/DVB channel decoding and MPEG TS or
PS capture
GPIO
The SAA7133HL offers a set of General Purpose
Input/Output (GPIO) pins, to interface to on-board
peripheral circuits; see also Table 6. These GPIOs are
intended to take over dedicated functions:
The SAA7133HL also supports application extension to
cover the reception of digital TV broadcast [DTV/ATSC,
DVB (T/C/S) or BS-digital]. The low IF signal from a hybrid
tuner is fed to a peripheral channel decoder, to decode it
into the transport stream. This TS, accompanied by a clock
and handshake signals [Start Of Packet (SOP), etc.] can
be captured by the SAA7133HL, in serial or parallel format.
The TS packets are written in a structured way in
dedicated DMA definition into the PCI memory space.
Toggling between two DMA buffers is supported
automatically.
2003 Feb 04
I2C-BUS MASTER
At PCI reset time, the I2C-bus master receives board
specific information from the on-board EEPROM to update
the PCI configuration registers.
BACK CABLE
7.8
Control of peripheral devices
The SAA7133HL incorporates an I2C-bus master to set-up
and control peripheral devices such as tuner, DTV/DVB
channel decoder, audio DSP co-processors, etc. The
I2C-bus interface itself is controlled from the PCI-bus on a
command level, reading and writing byte by byte. The
actual I2C-bus status is reported (status register) and, as
an option, can raise error interrupts on the PCI-bus.
A master clock output (A_CLK_master) for synchronous
clocking of external devices is available via a GPIO output.
The audio block is also able to work synchronously to an
external audio reference clock (A_REF_CLK).
7.7.4
SAA7133HL
• Digital video port output: 8-bit or 16-bit wide (including
raw DTV)
• Digital audio serial output: i.e. I2S-bus output
• Transport stream input:
– parallel (also applicable for program stream and
elementary stream)
– serial (also applicable as I2S-bus input)
33
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
• Peripheral interrupt input: four GPIO pins of the
SAA7133HL can be enabled to raise an interrupt on the
PCI-bus. By this means, peripheral devices can directly
intercept with the device driver on changed status or
error conditions.
BST-test can be found in the specification “IEEE Std.
1149.1”. A file containing the detailed Boundary Scan
Description Language (BSDL) description of the
SAA7133HL is available on request.
8.1
Any GPIO pin that is not used for a dedicated function is
available for direct read and write access via the PCI-bus.
Any GPIO pin can be selected individually as input or
output (masked write). By these means, very tailored
interfacing to peripheral devices can be created via the
SAA7133HL capture driver running on Windows operating
systems.
Initialization of boundary scan circuit
The Test Access Port (TAP) controller of an IC should be
in the reset state (TEST_LOGIC_RESET) when the IC is
in the functional mode. This reset state also forces the
instruction register into a functional instruction such as
IDCODE or BYPASS.
To solve the power-up reset, the standard specifies that
the TAP controller will be forced asynchronously to the
TEST_LOGIC_RESET state if pin TRST is at LOW level.
At system reset (PCI reset) all GPIO pins will be set to
3-state and input, and the logic level present on the GPIO
pins at that moment will be saved into a special ‘strap’
register. All GPIO pins have an internal pull-down resistor
(LOW level), but can be strapped externally with a 4.7 kΩ
resistor to the supply voltage (HIGH level). The device
driver can investigate the strap register for information
about the hardware configuration of a given board.
8
SAA7133HL
8.2
Device identification codes
When the IDCODE instruction is loaded into the BST
instruction register, the identification register will be
connected internally between pins TDI and TDO of the IC.
The identification register will load a component specific
code during the CAPTURE_DATA_REGISTER state of
the TAP controller and this code can subsequently be
shifted out. At board level, this code can be used to verify
component manufacturer, type and version number. The
device identification register contains 32 bits, numbered
31 to 0, where bit 31 is the most significant bit (nearest to
TDI) and bit 0 is the least significant bit (nearest to TDO)
(see Fig.16).
BOUNDARY SCAN TEST
The SAA7133HL has built-in logic and five dedicated pins
to support boundary scan testing which allows board
testing without special hardware (nails). The SAA7133HL
follows the “IEEE Std. 1149.1 - Standard Test Access Port
and Boundary - Scan Architecture” set by the Joint Test
Action Group (JTAG) chaired by Philips.
A device identification register is specified in “IEEE Std.
1149.1b-1994”. It is a 32-bit register which contains fields
for the specification of the IC manufacturer, the IC part
number and the IC version number. Its biggest advantage
is the possibility to check for the correct ICs mounted after
production and determination of the version number of ICs
during field service.
The 5 special pins are: Test Mode Select (TMS), Test
Clock (TCK), Test Reset (TRST), Test Data Input (TDI)
and Test Data Output (TDO).
The Boundary Scan Test (BST) functions BYPASS,
EXTEST, SAMPLE, CLAMP and IDCODE are all
supported (see Table 18). Details about the JTAG
Table 18 BST instructions supported by the SAA7133HL
INSTRUCTION
DESCRIPTION
BYPASS
This mandatory instruction provides a minimum length serial path (1 bit) between pins TDI and TDO
when no test operation of the component is required.
EXTEST
This mandatory instruction allows testing of off-chip circuitry and board level interconnections.
SAMPLE
This mandatory instruction can be used to take a sample of the inputs during normal operation of
the component. It can also be used to preload data values into the latched outputs of the boundary
scan register.
CLAMP
This optional instruction is useful for testing when not all ICs have BST. This instruction addresses
the bypass register while the boundary scan register is in external test mode.
IDCODE
This optional instruction will provide information on the components manufacturer, part number and
version number.
2003 Feb 04
34
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
MSB
handbook, full pagewidth
31
TDI
LSB
28 27
12 11
1
0
TDO
0001
0111000100110011
00000010101
1
4-bit
version
code
16-bit part number
11-bit manufacturer
identification
mandatory
MBL706
Fig.16 32 bits of identification code.
9 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); all ground pins connected together and
grounded (0 V); all supply pins connected together.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
VDDD
digital supply voltage
−0.5
+4.6
V
VDDA
analog supply voltage
−0.5
+4.6
V
∆VSS
voltage difference between pins VSSA and
VSSD
−
100
mV
VIA
input voltage at analog inputs
−0.5
+4.6
V
VI(n)
input voltage at pins XTALI, SDA and SCL
−0.5
VDDD + 0.5 V
VID
input voltage at digital I/O stages
outputs in 3-state;
−0.5 V < VDDD < 3.0 V
−0.5
+4.6
V
outputs in 3-state;
3.0 V < VDDD < 3.6 V
−0.5
+5.5
V
−65
+150
°C
Tstg
storage temperature
Tamb
ambient temperature
Vesd
electrostatic discharge voltage
0
70
°C
note 1
−250
+200
V
note 2
−3500 +3500
V
Notes
1. Machine model: L = 0.75 µH, C = 200 pF and R = 0 Ω.
2. Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor.
10 THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
PARAMETER
CONDITIONS
thermal resistance from junction to ambient in free air
VALUE
UNIT
30.7(1)
K/W
Note
1. The overall Rth(j-a) value can differ between 35 K/W and 30 K/W depending on the board layout. To minimize the
effective Rth(j-a) all power and ground pins must be connected to the power and ground layers directly. An ample
copper area direct under the SAA7133HL with a number of through-hole plating, which connect to the ground layer
(four-layer board: second layer), can also reduce the effective Rth(j-a). Please do not use any solder-stop varnish
under the chip. In addition the usage of soldering glue with a high thermal conductance after curing is recommended.
2003 Feb 04
35
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
11 CHARACTERISTICS
For minimum and maximum values: VDDD = 3.0 to 3.6 V; VDDA = 3.0 to 3.6 V; Tamb = 0 to 70 °C;
for typical values: VDDD = 3.3 V; VDDA = 3.3 V; Tamb = 25 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDDD
digital supply voltage
3.0
3.3
3.6
V
VDDA
analog supply voltage
3.0
3.3
3.6
V
P
power dissipation
D0 for typical application −
1.35
1.6
W
D0 after reset
−
0.15
−
W
D1
−
0.2
−
W
D2
−
0.15
−
W
D3-hot
−
−
0.02
W
crystal 1; see Table 19
−
32.11
−
MHz
crystal 2; see Table 19
−
24.576 −
power state
Crystal oscillator
fxtal(nom)
nominal crystal frequency
MHz
10−6
∆fxtal(n)
permissible nominal
frequency deviation
−
−
±70 ×
fxtal
oscillator frequency range
24
32.11
33
MHz
Pdrive
crystal power level of drive
at pin XTALO
−
0.5
−
mW
tj
oscillator clock jitter
−
−
±100
ps
VIH(XTALI)
HIGH-level input voltage at
pin XTALI
2
−
VDDD + 0.3
V
VIL(XTALI)
LOW-level input voltage at
pin XTALI
−0.3
−
+0.8
V
2
−
5.75
V
PCI-bus inputs and outputs
VIH
HIGH-level input voltage
VIL
LOW-level input voltage
−0.5
−
+0.8
V
ILIH
HIGH-level input leakage
current
VI = 2.7 V; note 1
−
−
10
µA
ILIL
LOW-level input leakage
current
VI = 0.5 V; note 1
−
−
−10
µA
VOH
HIGH-level output voltage
IO = −2 mA
2.4
−
−
V
VOL
LOW-level output voltage
IO = 3 or 6 mA; note 2
−
−
0.55
V
Ci
input capacitance at
pin PCI_CLK
5
−
12
pF
pin IDSEL
−
−
8
pF
other input pins
−
−
10
pF
SRr
output rise slew rate
0.4 to 2.4 V; note 3
1
−
5
V/ns
SRf
output fall slew rate
2.4 to 0.4 V; note 3
1
−
5
V/ns
2003 Feb 04
36
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
tval
PARAMETER
CLK to signal valid delay
SAA7133HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
see Fig.17; note 4
bused signals
2
−
11
ns
point-to-point signals
2
−
12
ns
ton
float-to-active delay
see Fig.17; note 5
2
−
−
ns
toff
active-to-float delay
see Fig.17; note 5
−
−
28
ns
tsu
input set-up time to CLK
see Fig.17; note 4
bused signals
7
−
−
ns
point-to-point signals
10 (12)
−
−
ns
th
input hold time from CLK
see Fig.17
0
−
−
ns
trst(CLK)
reset active time after CLK
stable
note 6
100
−
−
µs
trst(off)
reset active to output float
delay
notes 5, 6 and 7
−
−
40
ns
0
−
400
kbits/s
−0.5
−
0.3VDD(I2C)
V
I2C-bus interface, compatible to 3.3 and 5 V signalling (pins SDA and SCL)
fbit
bit frequency rate
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
note 8
0.7VDD(I2C) −
VDD(I2C) + 0.5 V
VOL
LOW-level output voltage
Io(sink) = 3 mA
−
−
0.4
V
note 8
Analog video inputs
INPUTS (PINS CV0 TO CV4)
Iclamp
clamping current
DC input voltage VI = 0.9 V −
±8
−
µA
Vi(p-p)
input voltage
(peak-to-peak value)
note 9
0.375
0.75
1.07
V
Ci
input capacitance
−
−
10
pF
9-BIT ANALOG-TO-DIGITAL CONVERTERS
αcs
channel crosstalk
fi < 5 MHz
−
−
−50
dB
B
analog bandwidth
at −3 dB; ADC only;
note 10
−
7
−
MHz
φdif
differential phase
amplifier plus anti-alias
filter bypassed
−
2
−
deg
Gdif
differential gain
amplifier plus anti-alias
filter bypassed
−
2
−
%
LEDC(d)
DC differential linearity
error
−
1.4
−
LSB
LEDC(i)
DC integral linearity error
−
2
−
LSB
S/N
signal-to-noise ratio
fi = 4 MHz; anti-alias filter
bypassed; AGC = 0 dB
−
50
−
dB
ENOB
effective number of bits
fi = 4 MHz; anti-alias filter
bypassed; AGC = 0 dB
−
8
−
bit
2003 Feb 04
37
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
PARAMETER
SAA7133HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Analog sound input (pin SIF)
input level adjustment at
0 dB
−
941
−
mV
input level adjustment at
−10 dB
−
2976
−
mV
minimum input voltage for
lower limit of AGC
(peak-to-peak value)
input level adjustment at
0 dB
−
59
−
mV
input level adjustment at
−10 dB
−
188
−
mV
AGC
AGC range of sound input
in addition to 0 and −10 dB −
switch
24
−
dB
Vi(max)(p-p)
Vi(min)(p-p)
maximum input voltage
(peak-to-peak value)
fi
input frequency
Ri
input resistance
Ci
input capacitance
default pre-gain selection
for pin SIF (0 dB)
3
−
12
MHz
10
−
−
kΩ
−
7.5
11
pF
Analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) and outputs (pins OUT_LEFT and
OUT_RIGHT)
Vi(nom)(rms)
nominal input voltage
(RMS value)
note 11
−
200
−
mV
Vi(max)(rms)
maximum input voltage
(RMS value)
THD < 3%; note 12
−
1
2
V
Vo(nom)(rms)
nominal output voltage
(RMS value)
note 11
−
180
−
mV
Vo(max)(rms)
maximum output voltage
(RMS value)
THD < 3%
−
1
−
V
Ri
input resistance
Vi(max) = 1 V (RMS)
−
145
−
kΩ
Vi(max) = 2 V (RMS)
−
48
−
kΩ
Ro
output resistance
150
250
375
Ω
RL(AC)
AC load resistance
10
−
−
kΩ
CL
output load capacitance
−
−
12
nF
Voffset(DC)
static DC offset voltage
−
10
30
mV
THD + N
total harmonic
distortion-plus-noise
Vi = Vo = 1 V (RMS);
fi = 1 kHz; bandwidth
B = 20 Hz to 20 kHz
−
0.1
0.3
%
S/N
signal-to-noise ratio
reference voltage
70
Vo = 1 V (RMS); fi = 1 kHz;
“ITU-R BS.468” weighted;
quasi peak
75
−
dB
αct
crosstalk attenuation
between any analog input
pairs; fi = 1 kHz
60
−
−
dB
αcs
channel separation
between left and right of
each input pair
60
−
−
dB
2003 Feb 04
38
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
PARAMETER
SAA7133HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Sound demodulator performance; note 13
AUDIO AM MONO CHARACTERISTICS (DDEP STANDARD CODE = 10)
S/NAM
AM demodulator
signal-to-noise ratio
AM carrier 6.5 MHz;
54% AM; fi = 1 kHz;
second SIF AGC off;
“ITU-R BS.468” weighted;
quasi peak
−
47
−
dB
THD + NAM
total harmonic
distortion-plus-noise of
AM demodulator
AM carrier 6.5 MHz;
54% AM; fi = 1 kHz;
second SIF AGC off;
“ITU-R BS.468” weighted;
quasi peak
−
0.43
−
%
Gresp(AM)
AM frequency response
from 20 Hz to 15 kHz
reference f = 1 kHz;
no clipping
−
−0.5 to −
+0.1
dB
BTSC stereo with L or R
only; 100% modulation;
fi = 1 kHz;
unweighted RMS
−
77
−
dB
THD + NBTSC total harmonic
distortion-plus-noise of
BTSC decoder output
BTSC stereo with L or R
only; 100% modulation;
fi = 1 kHz;
unweighted RMS
−
0.23
−
%
S/NSAP
SAP decoder output
signal-to-noise ratio
100% modulation;
fi = 1 kHz;
compromise de-emphasis
(SAPDBX = 0); bandwidth
B = 0 to 15 kHz;
unweighted RMS
−
59
−
dB
THD + NSAP
total harmonic
distortion-plus-noise of
SAP decoder output
100% modulation;
fi = 1 kHz;
compromise de-emphasis
(SAPDBX = 0); bandwidth
B = 0 to 15 kHz;
unweighted RMS
−
0.27
−
%
αct
crosstalk attenuation
1 kHz L or R or SAP;
100% modulation;
spectral at 1 kHz
BTSC to SAP
−
>80
−
dB
SAP to BTSC
−
>80
−
dB
10% EIM
−
≥32
−
dB
1 to 66% EIM
−
≥27
−
dB
AUDIO M STANDARD BTSC CHARACTERISTICS (DDEP STANDARD CODE = 13)
S/NBTSC
αcs(stereo)
2003 Feb 04
BTSC decoder output
signal-to-noise ratio
BTSC stereo channel
separation
L or R only;
50 Hz to 10 kHz
39
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
Gresp(BTSC)
PARAMETER
BTSC frequency response
SAA7133HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
30% modulation;
reference f = 1 kHz
stereo; L or R only
−
−0.4 to −
+1.5
dB
mono; L = R
−
−0.2 to −
+0.04
dB
AUDIO M STANDARD EIAJ CHARACTERISTICS (DDEP STANDARD CODE = 14)
S/NEIAJ
EIAJ decoder output
signal-to-noise ratio
EIAJ stereo with L or R;
100% modulation;
fi = 1 kHz;
unweighted RMS
−
61
−
dB
THD + NEIAJ
total harmonic
distortion-plus-noise of
EIAJ decoder output
EIAJ stereo with L or R;
100% modulation;
fi = 1 kHz;
unweighted RMS
−
0.17
−
%
S/NSUB
EIAJ sub-channel decoder EIAJ dual;
output signal-to-noise ratio 100% modulation;
fi = 1 kHz;
unweighted RMS
−
59
−
dB
THD + NSUB
total harmonic
distortion-plus-noise of
EIAJ sub-channel decoder
output
EIAJ dual;
100% modulation;
fi = 1 kHz;
unweighted RMS
−
0.8
−
%
αct
EIAJ dual crosstalk
attenuation
100% modulation;
fi = 1 kHz
main to sub-channel
−
80
−
dB
sub to main channel
−
80
−
dB
100 Hz to 5 kHz
−
38
−
dB
50 Hz to 8 kHz
−
28
−
dB
EIAJ stereo;
15% modulation;
reference f = 1 kHz
−
−0.9 to −
+0.1
dB
−
dB
αcs(stereo)
Gresp(EIAJ)
EIAJ stereo channel
separation
EIAJ frequency response
from 20 Hz to 12 kHz
50% modulation;
selective RMS; L or R
AUDIO FM RADIO CHARACTERISTICS (DDEP STANDARD CODE = 15 TO 18)
S/Nradio
2003 Feb 04
FM radio decoder output
signal-to-noise ratio
FM radio stereo with L or R −
only; 10.7 MHz carrier;
100% modulation;
fi = 1 kHz;
75 µs de-emphasis;
unweighted RMS
40
55
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
PARAMETER
SAA7133HL
CONDITIONS
MIN.
THD + Nradio
total harmonic
distortion-plus-noise of
FM radio decoder output
FM radio stereo with L or R −
only; 10.7 MHz carrier;
100% modulation;
fi = 1 kHz;
75 µs de-emphasis;
unweighted RMS
αcs(stereo)
FM radio stereo channel
separation
60% modulation;
selective RMS;
pre-emphasis off;
100 Hz to 14 kHz
Gresp(radio)
FM radio frequency
response from
20 Hz to 15 kHz
FM radio stereo;
10.7 MHz carrier;
75 µs de-emphasis;
30% modulation;
reference f = 1 kHz
TYP.
MAX.
UNIT
0.2
−
%
−
45 to
55
−
dB
−
−0.2 to −
+0.4
dB
European system
−
10
−
%
Japanese system
−
21
−
%
M standard (EIAJ) stereo;
slow mode
−
981.9
to
983.0
−
Hz
M standard (EIAJ) stereo;
fast mode
−
979.7
to
985.1
−
Hz
M standard (EIAJ) dual;
slow mode
−
921.8
to
923.0
−
Hz
M standard (EIAJ) dual;
fast mode
−
919.3
to
925.8
−
Hz
slow mode
−
2
−
s
fast mode
−
0.5
−
s
AUDIO IDENTIFICATION OF EIAJ MONO/STEREO (JAPANESE) STANDARDS
mpilot
fident(EIAJ)
tident
modulation degree of pilot
tone
identification frequency
window
total identification time on
or off
nominal pilot level and
identification frequency;
no overmodulation
AUDIO AUTOMATIC STANDARD DETECTION (ASD) TIMING; STDSEL = 1DH
tASD(mono)
time to auto-detect mono
sound standard
default threshold settings
−
65
−
ms
tASD(stereo)
time to auto-detect stereo
or multi-channel sound
standard
BTSC stereo
−
0.25
−
s
BTSC SAP
−
0.3
−
s
EIAJ
−
0.5
−
s
2003 Feb 04
41
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
PARAMETER
SAA7133HL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
All digital I/Os: GPIO pins and BST test pins (5 V tolerant)
PINS GPIO0 TO GPIO23, V_CLK, GPIO25 TO GPIO27, TDI, TDO, TMS, TCK AND TRST
VIH
HIGH-level input voltage
2.0
−
5.5
VIL
LOW-level input voltage
−0.3
−
+0.8
V
ILI
input leakage current
−
−
1
µA
IL(I/O)
I/O leakage current
3.3 V signal levels at
VDDD ≥ 3.3 V
−
−
10
µA
V
Ci
input capacitance
I/O at high-impedance
−
−
8
pF
Rpd
pull-down resistance
VI = VDDD
−
50
−
kΩ
Rpu
pull-up resistance
VI = 0
−
50
−
kΩ
VOH
HIGH-level output voltage
IO = −2 mA
2.4
−
VDDD + 0.5
V
VOL
LOW-level output voltage
IO = 2 mA
0
−
0.4
V
Audio-video port outputs (digital video stream from comb filter decoder or scaler, digital audio from sound
decoder or baseband audio inputs via I2S-bus)
LLC AND LLC2 CLOCK OUTPUT ON PIN V_CLK (see Fig.18)
CL
load capacitance
Tcy
cycle time
δ
duty factor
15
−
50
pF
LLC active
35
−
39
ns
LLC2 active
70
−
78
ns
LCC active
35
−
65
%
LCC2 active
35
−
65
%
CL = 40 pF; note 14
tr
rise time
0.4 to 2.4 V
−
−
5
ns
tf
fall time
2.4 to 0.4 V
−
−
5
ns
VIDEO DATA OUTPUT WITH RESPECT TO SIGNAL V_CLK ON PINS GPIO0 TO GPIO17, GPIO22 AND GPIO23 (see Fig.18)
CL
load capacitance
th
data hold time
tPD
propagation delay from
positive edge of
signal V_CLK
15
−
50
pF
LLC active
5
−
−
ns
LLC2 active
15
−
−
ns
LLC active
−
−
28
ns
LLC2 active
−
−
55
ns
27.8
37
333
ns
notes 15 and 16
notes 15 and 16
Raw DTV/DVB outputs (reuse of video ADCs in DVB/TV applications)
CLOCK INPUT SIGNAL X_CLK_IN ON PIN GPIO18
Tcy
cycle time
δ
duty factor
note 14
40
50
60
%
tr
rise time
0.8 to 2.0 V
−
−
5
ns
tf
fall time
2.0 to 0.8 V
−
−
5
ns
−
−
25
pF
CLOCK OUTPUT SIGNAL ADC_CLK ON PIN V_CLK
CL
2003 Feb 04
load capacitance
42
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SYMBOL
PARAMETER
SAA7133HL
CONDITIONS
MIN.
27.8
TYP.
−
MAX.
−
UNIT
Tcy
cycle time
ns
δ
duty factor
CL = 40 pF; note 14
40
−
60
%
tr
rise time
0.4 to 2.4 V
−
−
5
ns
tf
fall time
2.4 to 0.4 V
−
−
5
ns
25
−
50
pF
VSB DATA OUTPUT SIGNALS WITH RESPECT TO SIGNAL ADC_CLK
CL
load capacitance
th
data hold time
inverted and not delayed;
note 15
5
−
−
ns
tPD
propagation delay from
positive edge of
signal ADC_CLK
inverted and not delayed;
notes 15 and 17
−
−
23
ns
TS capture inputs with parallel transport streaming (TS-P); e.g. DVB applications
CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19)
−
333
−
ns
note 14
40
−
60
%
rise time
0.8 to 2.0 V
−
−
5
ns
fall time
2.0 to 0.8 V
−
−
5
ns
Tcy
cycle time
δ
duty factor
tr
tf
DATA AND CONTROL INPUT SIGNALS ON TS-P PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO0 TO GPIO7,
GPIO16, GPIO19 AND GPIO22 (see Fig.19)
tsu(D)
input data set-up time
3
−
−
ns
th(D)
input data hold time
8
−
−
ns
TS capture inputs with serial transport streaming (TS-S); e.g. DVB applications
CLOCK INPUT SIGNAL TS_CLK ON PIN GPIO20 (see Fig.19)
Tcy
cycle time
37
−
−
ns
δ
duty factor
note 14
40
−
60
%
tr
rise time
0.8 to 2.0 V
−
−
5
ns
tf
fall time
2.0 to 0.8 V
−
−
5
ns
DATA AND CONTROL INPUT SIGNALS ON TS-S PORT (WITH RESPECT TO SIGNAL TS_CLK) ON PINS GPIO16, GPIO19,
GPIO21 AND GPIO22 (see Fig.19)
tsu(D)
input data set-up time
3
−
−
ns
th(D)
input data hold time
8
−
−
ns
Notes
1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with 3-state outputs.
2. Pins without pull-up resistors must have a 3 mA output current. Pins requiring pull-up resistors must have 6 mA;
these are pins FRAME#, TRDY#, IRDY#, DEVSEL#, SERR#, PERR#, INT_A and STOP#.
3. This parameter is to be interpreted as the cumulative edge rate across the specified range, rather than the
instantaneous rate at any point within the transition range.
4. REQ# and GNT# are point-to-point signals and have different output valid delay and input set-up times than bused
signals. GNT# has a set-up time of 10 ns. REQ# has a set-up time of 12 ns.
2003 Feb 04
43
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
5. For purposes of active or float timing measurements, the high-impedance or ‘off’ state is defined to be when the total
current delivered through the device is less than or equal to the leakage current specification.
6. RST is asserted and de-asserted asynchronously with respect to CLK.
7. All output drivers floated asynchronously when RST is active.
8. VDD(I2C) is the extended pull-up voltage of the I2C-bus (3.3 or 5 V bus).
9. Nominal analog video input signal is to be terminated by 75 Ω that results in 1 V (p-p) amplitude. This termination
resistor should be split into 18 Ω and 56 Ω, and the dividing tap should feed the video input pin, via a coupling
capacitor of 47 nF, to achieve a control range from −3 dB (attenuation) to +6 dB (amplification) for the internal
automatic gain control. See also the application note of the SAA7133HL.
10. See user manual SAA7133HL for Anti-Alias Filter (AAF).
11. Definition of levels and level setting:
a) The full-scale level for analog audio signals VFS = 0.8 V (RMS). The nominal level at the digital crossbar switch
is defined at −15 dB (FS).
b) Nominal audio input levels: external, mono, Vi = 180 mV (RMS); −15 dB (FS).
12. The analog audio inputs (pins LEFT1, RIGHT1, LEFT2 and RIGHT2) are supported by two input levels: 1 V (RMS)
and 2 V (RMS), selectable independently per stereo input pair, LEFT1, RIGHT1 and LEFT2, RIGHT2.
13. VDDA = 3.3 V; Vi(SIF) = 196 mV (RMS); level and gain settings according to note 11; for external components see the
application diagram in SAA7133HL application notes; unless otherwise specified.
tH
14. The definition of the duty factor: δ = ------T cy
15. The output timing must be measured with the load of a 30 pF capacitor to ground and a 500 Ω resistor to 1.4 V.
16. Signal V_CLK inverted; not delayed (default set-up).
17. tPD = 6 ns + 0.6TADC_CLK in ns (TADC_CLK = 28 ns).
2.4 V
handbook, full pagewidth
CLK
1.5 V
0.4 V
tval
OUTPUT
DELAY
1.5 V
3-STATE
OUTPUT
ton
toff
tsu
th
2.4 V
INPUT
1.5 V
input valid
1.5 V
0.4 V
MGG280
Fig.17 PCI I/O timing.
2003 Feb 04
44
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
t PD
handbook, full pagewidth
th
video data and
control output
(pins GPIO0 to GPIO 17,
GPIO 22 and GPIO23)
2.4 V
0.4 V
tH
tL
2.4 V
clock output
(pin V_CLK)
1.5 V
0.4 V
tr
tf
MHC002
Fig.18 Data output timing (video data, control outputs and raw DTV/DVB).
handbook, full pagewidth
TS data and
2.0 V
control input
(pins GPIO0 to GPIO 7,
GPIO 16, GPIO19
and GPIO21)
0.8 V
t su(D)
t h(D)
2.0 V
TS_CLK
(pin GPIO20)
1.5 V
0.8 V
tr
Fig.19 Data input timing (TS data and control inputs).
2003 Feb 04
45
tf
MHC003
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
Table 19 Specification of crystals and related applications (examples); note 1
CRYSTAL FREQUENCY
32.11 MHz
24.576 MHz
STANDARD
UNIT
FUNDAMENTAL
3rd HARMONIC
FUNDAMENTAL
3rd HARMONIC
1B
1C
1A
2B
2C
2A
Typical load
capacitance
20
8
8
20
8
10
pF
Maximum series
resonance resistance
30
60
50
30
60
80
Ω
Typical motional
capacitance
20
13.5
1.5
20
1
1.5
fF
Maximum parallel
capacitance
7
3 ±1
4.3
7
3.3
3.5
pF
Crystal specification
Maximum permissible
deviation
±30 × 10−6 ±30 × 10−6
±30 × 10−6
±30 × 10−6 ±30 × 10−6
±50 × 10−6
Maximum temperature
deviation
±30 × 10−6 ±30 × 10−6
±30 × 10−6
±30 × 10−6 ±30 × 10−6
±20 × 10−6
External components
Typical load
capacitance at
pin XTALI
33
10
15
27
5.6
18
pF
Typical load
capacitance at
pin XTALO
33
10
15
27
5.6
18
pF
Typical capacitance of
LC filter
n.a.
n.a.
1
n.a.
n.a.
1
nF
Typical inductance of
LC filter
n.a.
n.a.
4.7
n.a.
n.a.
4.7
µH
Note
1. For oscillator application, see the application note of the SAA7133HL.
2003 Feb 04
46
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
12 PACKAGE OUTLINE
LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm
SOT425-1
c
y
X
A
65
102
64
103
ZE
e
E HE
A A2 A
1
(A 3)
θ
wM
Lp
bp
pin 1 index
L
detail X
39
128
1
38
v M A
ZD
wM
bp
e
D
B
HD
v M B
0
5
10 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
mm
1.6
0.15
0.05
1.45
1.35
0.25
0.27
0.17
0.20
0.09
20.1
19.9
14.1
13.9
0.5
HD
HE
22.15 16.15
21.85 15.85
L
Lp
v
w
y
1.0
0.75
0.45
0.2
0.12
0.1
Z D(1) Z E(1)
θ
0.81
0.59
7
0o
0.81
0.59
o
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT425-1
136E28
MS-026
2003 Feb 04
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
00-01-19
47
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
If wave soldering is used the following conditions must be
observed for optimal results:
13 SOLDERING
13.1
Introduction to soldering surface mount
packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
13.2
SAA7133HL
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
13.3
13.4
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
2003 Feb 04
Manual soldering
48
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
13.5
SAA7133HL
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable(3)
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not
PLCC(4), SO, SOJ
suitable
LQFP, QFP, TQFP
SSOP, TSSOP, VSO, VSSOP
REFLOW(2)
suitable
suitable
suitable
not
recommended(4)(5)
suitable
not
recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2003 Feb 04
49
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
SAA7133HL
14 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
15 DEFINITIONS
16 DISCLAIMERS
Short-form specification  The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Life support applications  These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Limiting values definition  Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
at these or at any other conditions above those given in the
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Right to make changes  Philips Semiconductors
reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
Application information  Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
no representation or warranty that such applications will be
suitable for the specified use without further testing or
modification.
2003 Feb 04
50
Philips Semiconductors
Product specification
PCI audio and video broadcast decoder
ICs with MPEG-audio/AC-3 audio functionality 
Purchase of a Philips IC with an MPEG-audio and/or AC-3
audio functionality does not convey an implied license
under any patent right to use this IC in any MPEG-audio or
AC-3 audio application. For more information please
contact the nearest Philips Semiconductors sales office or
e-mail: [email protected].
SAA7133HL
ICs with MPEG-2 functionality  Use of this product in
any manner that complies with the MPEG-2 Standard is
expressly prohibited without a license under applicable
patents in the MPEG-2 patent portfolio, which license is
available from MPEG LA, L.L.C., 250 Steele Street, Suite
300, Denver, Colorado 80206.
17 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
2003 Feb 04
51
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
SCA75
© Koninklijke Philips Electronics N.V. 2003
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753505/01/pp52
Date of release: 2003
Feb 04
Document order number:
9397 750 10353