CYPRESS CY62146ESL

CY62146ESL MoBL
4-Mbit (256K x 16) Static RAM
Features
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Placing the device into standby
mode reduces power consumption by more than 99% when
deselected (CE HIGH). The input and output pins (I/O0 through
I/O15) are placed in a high impedance state when the device is
deselected (CE HIGH), the outputs are disabled (OE HIGH),
both Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH) or during a write operation (CE LOW and WE LOW).
■
Very high speed: 45 ns
■
Wide voltage range: 2.2 V to 3.6 V and 4.5 V to 5.5 V
■
Ultra low standby power
❐ Typical Standby current: 1 A
❐ Maximum Standby current: 7 A
■
Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■
Easy memory expansion with CE and OE features
■
Automatic power down when deselected
■
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■
Available in Pb-free 44-pin thin small outline package (TSOP) II
package
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O0 through I/O7) is written into the location
specified on the address pins (A0 through A17). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O8 through
I/O15) is written into the location specified on the address pins
(A0 through A17).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on I/O0 to I/O7. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O8 to I/O15. See the “Truth Table” on page 11 for a
complete description of read and write modes.
Functional Description
The CY62146ESL is a high performance CMOS static RAM
organized as 256K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life (MoBL) in portable
Logic Block Diagram
SENSE AMPS
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW DECODER
DATA IN DRIVERS
256K x 16
RAM Array
I/O0–I/O7
I/O8–I/O15
Cypress Semiconductor Corporation
Document #: 001-43142 Rev. *C
•
BHE
WE
CE
OE
BLE
A17
A16
A15
A13
A14
A12
A11
COLUMN DECODER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 29, 2011
CY62146ESL MoBL
Contents
Pin Configuration ............................................................. 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
Electrical Characteristics ................................................. 4
Capacitance ...................................................................... 5
Thermal Resistance .......................................................... 5
Data Retention Characteristics ....................................... 6
Switching Characteristics ................................................ 7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 11
Document #: 001-43142 Rev. *C
Package Diagram ............................................................ 12
Ordering Information ...................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
CY62146ESL MoBL
Pin Configuration
Figure 1. 44-Pin TSOP II (Top View) [1]
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
VSS
I/O4
I/O5
I/O6
I/O7
WE
A17
A16
A15
A14
A13
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
BHE
BLE
I/O15
I/O14
I/O13
I/O12
VSS
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
A12
Product Portfolio
Power Dissipation
Product
CY62146ESL
Range
Industrial
VCC Range (V)[2]
2.2 V–3.6 V and 4.5 V–5.5 V
Speed
(ns)
45
Operating ICC, (mA)
f = 1MHz
f = fmax
Standby, ISB2
(A)
Typ[3]
Max
Typ[3]
Max
Typ [3]
Max
2
2.5
15
20
1
7
Notes
1. NC pins are not connected on the die.
2. Datasheet specifications are not guaranteed for VCC in the range of 3.6 V to 4.5 V
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
Document #: 001-43142 Rev. *C
Page 3 of 15
CY62146ESL MoBL
Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Static discharge voltage............................................. >2001V
(MIL-STD-883, Method 3015)
Storage temperature................................. –65 °C to +150 °C
Latch up current....................................................... >200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Supply voltage to ground potential .................–0.5 V to 6.0 V
Device
DC voltage applied to outputs
in High-Z State[4, 5] .........................................–0.5 V to 6.0 V
CY62146ESL
DC input voltage[4, 5] .......................................–0.5 V to 6.0 V
Ambient
Temperature
Range
VCC[6]
Industrial –40 °C to +85 °C 2.2 V–3.6 V,
and
4.5 V–5.5 V
Output current into outputs (LOW) .............................. 20 mA
Electrical Characteristics
Over the Operating Range
45 ns
Parameter
VOH
VOL
VIH
VIL
Description
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Test Conditions
Max
2.2 < VCC < 2.7
IOH = –0.1 mA
2.0
IOH = –1.0 mA
2.4
4.5 < VCC < 5.5
IOH = –1.0 mA
2.4
2.2 < VCC < 2.7
IOL = 0.1 mA
0.4
2.7 < VCC < 3.6
IOL = 2.1mA
0.4
4.5 < VCC < 5.5
IOL = 2.1mA
0.4
Unit
V
2.2 < VCC < 2.7
1.8
VCC + 0.3
2.7 < VCC < 3.6
2.2
VCC + 0.3
V
V
4.5 < VCC < 5.5
2.2
VCC + 0.5
2.2 < VCC < 2.7
–0.3
0.6
2.7 < VCC < 3.6
–0.3
0.8
4.5 < VCC < 5.5
–0.5
0.8
GND < VI < VCC
–1
+1
A
–1
+1
A
15
20
mA
2
2.5
1
7
A
1
7
A
Input Leakage Current
IOZ
Output Leakage Current GND < VO < VCC, Output Disabled
ICC
VCC Operating Supply
Current
ISB2[8]
Typ [7]
2.7 < VCC < 3.6
IIX
ISB1[8]
Min
f = fmax = 1/tRC
f = 1 MHz
VCC = VCCmax
IOUT = 0 mA, CMOS levels
Automatic CE Power
CE > VCC 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
down Current — CMOS f = fmax (Address and Data Only), I/O
Inputs
f = 0 (OE, BHE, BLE and WE), VCC = VCC(max)
Automatic CE Power
CE > VCC – 0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V,
down Current — CMOS f = 0, VCC = VCC(max)
V
Inputs
Notes
4. VIL(min) = –2.0V for pulse durations less than 20 ns.
5. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
6. Full Device AC operation assumes a 100 s ramp time from 0 to VCC (min) and 200 s wait time after VCC stabilization.
7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
8. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
Document #: 001-43142 Rev. *C
Page 4 of 15
CY62146ESL MoBL
Capacitance
Parameter[9]
Description
CIN
Input capacitance
COUT
Output capacitance
Test Conditions
Max
Unit
10
pF
10
pF
TSOP II
Unit
77
C/W
13
C/W
TA = 25 °C, f = 1 MHz,
VCC = VCC(typ)
Thermal Resistance
Parameter[9]
Description
Test Conditions
JA
Thermal resistance
(Junction to ambient)
JC
Thermal resistance
(Junction to case)
Still Air, soldered on a 3 × 4.5 inch, two-layer
printed circuit board
Figure 2. AC Test Loads and Waveforms
All Input Pulses
R1
VCC
Output
VCC
10%
GND
R2 Rise Time = 1 V/ns
30 pF
Including
JIG and
Scope
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to:
Thé venin Equivalent
RTH
OUTPUT
V TH
Parameters
2.5 V
3.0 V
5.0 V
Unit
R1
16667
1103
1800

R2
15385
1554
990

RTH
8000
645
639

VTH
1.20
1.75
1.77
V
Note
9. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-43142 Rev. *C
Page 5 of 15
CY62146ESL MoBL
Data Retention Characteristics
Over the Operating Range
Parameter
Description
Conditions
Min
Typ[10]
Max
1.5
Unit
VDR
VCC for data retention
ICCDR[11]
Data retention current
tCDR [12]
Chip deselect to data
retention time
0
ns
tR [13]
Operation recovery time
45
ns
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
VCC = 1.5 V
V
1
A
7
Figure 3. Data Retention Waveform
DATA RETENTION MODE
VCC
VCC(min)
tCDR
VDR > 1.5 V
VCC(min)
tR
CE
Notes
10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 3 V, and VCC = 5 V, TA = 25 °C.
11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating.
12. Tested initially and after any design or process changes that may affect these parameters.
13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
Document #: 001-43142 Rev. *C
Page 6 of 15
CY62146ESL MoBL
Switching Characteristics
Over the Operating Range
Parameter[14]
Description
45 ns
Min
Max
Unit
Read Cycle
tRC
Read cycle time
tAA
Address to data valid
45
tOHA
Data hold from address change
tACE
CE LOW to data valid
45
ns
tDOE
OE LOW to data valid
22
ns
18
ns
LOW-Z[15]
tLZOE
OE LOW to
tHZOE
OE HIGH to High-Z[15, 16]
tLZCE
CE LOW to Low-Z[15]
tHZCE
CE HIGH to
ns
45
10
ns
5
ns
10
High-Z[15, 16]
ns
ns
18
ns
tPU
CE LOW to power up
tPD
CE HIGH to power down
45
ns
tDBE
BLE/BHE LOW to data valid
22
ns
tLZBE
tHZBE
BLE/BHE LOW to
Low-Z[15]
BLE/BHE HIGH to
HIGH-Z[15, 16]
0
ns
5
ns
18
ns
Write Cycle[17]
tWC
Write cycle time
45
ns
tSCE
CE LOW to write end
35
ns
tAW
Address setup to write end
35
ns
tHA
Address hold from write end
0
ns
tSA
Address setup to Write Start
0
ns
tPWE
WE pulse width
35
ns
tBW
BLE/BHE LOW to write end
35
ns
tSD
Data Setup to write end
25
ns
tHD
Data Hold from write end
0
ns
tHZWE
tLZWE
WE LOW to
High-Z[15, 16]
WE HIGH to
Low-Z[15]
18
10
ns
ns
Notes
14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the AC Test Loads and Waveforms on page 5.
15. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
16. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high-impedance state.
17. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
Document #: 001-43142 Rev. *C
Page 7 of 15
CY62146ESL MoBL
Switching Waveforms
Figure 4. Read Cycle No.1: Address Transition Controlled. [18, 19]
tRC
RC
ADDRESS
tAA
tOHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Figure 5. Read Cycle No. 2: OE Controlled [19, 20]
ADDRESS
tRC
CE
tPD
tHZCE
tACE
OE
tHZOE
tDOE
tLZOE
BHE/BLE
tHZBE
tDBE
tLZBE
DATA OUT
HIGH
IMPEDANCE
HIGHIMPEDANCE
DATA VALID
tLZCE
tPU
VCC
SUPPLY
CURRENT
ICC
50%
50%
ISB
Notes
18. The device is continuously selected. OE, CE = VIL, BHE, BLE, or both = VIL.
19. WE is HIGH for read cycle.
20. Address valid before or similar to CE, BHE, BLE transition LOW.
Document #: 001-43142 Rev. *C
Page 8 of 15
CY62146ESL MoBL
Switching Waveforms (continued)
Figure 6. Write Cycle No 1: WE Controlled [21, 22, 23]
tWC
ADDRESS
tSCE
CE
tAW
tHA
tSA
tPWE
WE
tBW
BHE/BLE
OE
DATA I/O
tSD
NOTE 24
tHD
DATAIN
tHZOE
Figure 7. Write Cycle 2: CE Controlled [21, 22, 23]
tWC
ADDRESS
tSCE
CE
tSA
tAW
tHA
tPWE
WE
tBW
BHE/BLE
OE
tSD
DATA I/O
tHD
DATAIN
NOTE 24
tHZOE
Notes
21. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE, BLE or both = VIL. All signals must be active to initiate a write and any of these
signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the write.
22. Data I/O is high impedance if OE = VIH.
23. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
24. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-43142 Rev. *C
Page 9 of 15
CY62146ESL MoBL
Switching Waveforms (continued)
Figure 8. Write Cycle 3: WE controlled, OE LOW [25]
tWC
ADDRESS
tSCE
CE
tBW
BHE/BLE
tAW
tHA
tSA
tPWE
WE
tSD
DATA I/O
NOTE 26
tHD
DATAIN
tLZWE
tHZWE
Figure 9. Write Cycle 4: BHE/BLE Controlled, OE LOW [25]
tWC
ADDRESS
CE
tSCE
tAW
tHA
tBW
BHE/BLE
tSA
tPWE
WE
tHZWE
DATA I/O
NOTE 26
tSD
tHD
DATAIN
tLZWE
Notes
25. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state.
26. During this period, the I/Os are in output state. Do not apply input signals.
Document #: 001-43142 Rev. *C
Page 10 of 15
CY62146ESL MoBL
Truth Table
CE[27]
WE
OE
BHE
BLE
H
X
X
X
X
High-Z
Deselect/Power down
Standby (ISB)
L
X
X
H
H
High-Z
Output disabled
Active (ICC)
L
H
L
L
L
Data Out (I/O0–I/O15)
Read
Active (ICC)
L
H
L
H
L
Data Out (I/O0–I/O7);
I/O8–I/O15 in High-Z
Read
Active (ICC)
L
H
L
L
H
Data Out (I/O8–I/O15);
I/O0–I/O7 in High-Z
Read
Active (ICC)
L
H
H
L
L
High-Z
Output disabled
Active (ICC)
L
H
H
H
L
High-Z
Output disabled
Active (ICC)
L
H
H
L
H
High-Z
Output disabled
Active (ICC)
L
L
X
L
L
Data In (I/O0–I/O15)
Write
Active (ICC)
L
L
X
H
L
Data In (I/O0–I/O7);
I/O8–I/O15 in High-Z
Write
Active (ICC)
L
L
X
L
H
Data In (I/O8–I/O15);
I/O0–I/O7 in High-Z
Write
Active (ICC)
Inputs/Outputs
Mode
Power
Note
27. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Document #: 001-43142 Rev. *C
Page 11 of 15
CY62146ESL MoBL
Ordering Information
Speed
(ns)
Package
Diagram
Ordering Code
45
CY62146ESL-45ZSXI
Operating
Range
Package Type
51-85087 44-pin TSOP Type II (Pb-free)
Industrial
Ordering Code Definitions
CY 621 4
6
E SL
-
xx
xxx
I
Temperature Range: x = I = Industrial
ZSX = 44-pin TSOP II (Pb-free)
xx = Speed Grade
Separator
SL = Voltage range (3 V typical; 5 V typical)
E = Process Technology 90 nm
Buswidth = × 16
Density = 4-Mbit
Family Code: MoBL SRAM family
Company ID: CY = Cypress
Package Diagram
Figure 10. 44-Pin TSOP II, 51-85087
PIN 1 I.D.
11.938 (0.470)
11.735 (0.462)
1
10.262 (0.404)
10.058 (0.396)
22
23
Z Z Z
Z X Z
AA
44
BOTTOM VIEW
TOP VIEW
0.800 BSC
(0.0315)
0.400(0.016)
0.300 (0.012)
EJECTOR MARK
(OPTIONAL)
CAN BE LOCATED
ANYWHERE IN THE
BOTTOM PKG
BASE PLANE
10.262 (0.404)
10.058 (0.396)
0.10 (.004)
18.517 (0.729)
18.313 (0.721)
0.150 (0.0059)
0.050 (0.0020)
1.194 (0.047)
0.991 (0.039)
DIMENSION IN MM (INCH)
MAX
MIN.
Document #: 001-43142 Rev. *C
0.210 (0.0083)
0.120 (0.0047)
0°-5°
SEATING
PLANE
0.597 (0.0235)
0.406 (0.0160)
51-85087 *C
Page 12 of 15
CY62146ESL MoBL
Acronyms
Acronym
Description
BHE
byte high enable
BLE
byte low enable
CE
chip enable
CMOS
complementary metal oxide semiconductor
I/O
input/output
OE
output enable
SRAM
static random access memory
TSOP
thin small outline package
VFBGA
very fine ball gird array
WE
write enable
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
A
microamperes
mA
milliamperes
MHz
megahertz
ns
nanoseconds
pF
picofarads
V
volts

ohms
W
watts
Document #: 001-43142 Rev. *C
Page 13 of 15
CY62146ESL MoBL
Document History Page
Document Title: CY62146ESL MoBL 4-Mbit (256K x 16) Static RAM
Document Number: 001-43142
REV.
ECN NO.
Issue Date
Orig. of
Change
Description of Change
**
1875228
See ECN
*A
2944332
06/04/2010
VKN
*B
3109186
12/13/2010
PRAS
Changed Table Footnotes to Footnotes.
Added Ordering Code Definitions.
*C
3296704
06/29/2011
RAME
Removed reference to AN1064 SRAM system guidelines.
Added footnote 9 to parameter sections of Capacitance and Thermal
Resistance.
Added ISB1 to footnote 8.
Added footnote 11.
Changed tRC value as 45 in Data Retention Characteristics table.
Footnote 14 moved to parameter section in Switching Characteristics
Added Units of Measure.
Document #: 001-43142 Rev. *C
VKN/AESA New Data Sheet
Added Contents
Added footnote for ISB2 parameter in Electrical Characteristics
Added footnote related to chip enable in Truth Table
Updated Package Diagram
Added Sales, Solutions, and Legal Information
Page 14 of 15
CY62146ESL MoBL
Sales, Solutions, and Legal Information
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assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43142 Rev. *C
Revised June 29, 2011
Page 15 of 15
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.