CY62137FV18 MoBL® 2-Mbit (128 K × 16) Static RAM 2-Mbit (128 K × 16) Static RAM Features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), both the Byte High Enable and the Byte Low Enable are disabled (BHE, BLE HIGH), or during an active write operation (CE LOW and WE LOW). ■ Very high speed: 55 ns ■ Wide voltage range: 1.65 V to 2.25 V ■ Pin compatible with CY62137CV18 ■ Ultra low standby power ❐ Typical standby current: 1 A ❐ Maximum standby current: 5 A ■ Ultra low active power ❐ Typical active current: 1.6 mA @ f = 1 MHz ■ Ultra low standby power ■ Easy memory expansion with CE and OE features ■ Automatic power down when deselected ■ Complementary metal oxide semiconductor (CMOS) for optimum speed and power ■ Byte power-down feature ■ Available in a Pb-free 48-ball Very fine-pitch ball grid package (VFBGA) package To write to the device, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7) is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16). To read from the device, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from the memory appears on I/O8 to I/O15. See the Truth Table on page 11 for a complete description of read and write modes. Functional Description The CY62137FV18 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features Logic Block Diagram SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 128K x 16 RAM Array I/O0–I/O7 I/O8–I/O15 COLUMN DECODER Cypress Semiconductor Corporation Document #: 001-08030 Rev. *I BHE WE CE OE BLE • A16 A15 A14 A13 BHE BLE A11 CE A12 POWER DOWN CIRCUIT 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 17, 2011 [+] Feedback CY62137FV18 MoBL® Contents Product Portfolio .............................................................. 3 Pin Configuration ............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 Electrical Characteristics ................................................. 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 Switching Characteristics ................................................ 7 Switching Waveforms ...................................................... 8 Document #: 001-08030 Rev. *I Truth Table ...................................................................... 11 Ordering Information ...................................................... 12 Ordering Code Definitions ......................................... 12 Package Diagram ............................................................ 13 Acronyms ........................................................................ 14 Document Conventions ................................................. 14 Units of Measure ....................................................... 14 Document History Page ................................................. 15 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC Solutions ......................................................... 16 Page 2 of 16 [+] Feedback CY62137FV18 MoBL® Product Portfolio Power Dissipation VCC Range (V) Product CY62137FV18LL Min Typ [1] Max 1.65 1.8 2.25 Pin Configuration Operating ICC (mA) Speed (ns) 55 f = 1 MHz Standby ISB2 (A) f = fmax Typ [1] Max Typ [1] Max Typ [1] Max 1.6 2.5 13 18 1 5 Figure 1. 48-ball VFBGA Pinout [2, 3] Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 NC A7 VCC D VCC NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O12 I/O3 I/O15 NC A12 A13 WE I/O7 G NC A8 A9 A10 A11 NC H Notes 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 2. NC pins are not connected on the die. 3. Pins D3, H1, G2, H6 and H3 in the VFBGA package are address expansion pins for 4 Mb, 8 Mb, 16 Mb, and 32 Mb and 64 Mb respectively. Document #: 001-08030 Rev. *I Page 3 of 16 [+] Feedback CY62137FV18 MoBL® DC Input Voltage [4, 5] ..................................–0.2 V to 2.45 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. User guidelines are not tested. Storage temperature ............................... –65 °C to + 150 °C Ambient temperature with power applied ......................................... –55 °C to + 125 °C Supply voltage to ground potential ....................................................–0.2 V to + 2.45 V DC voltage applied to outputs in High Z State [4, 5] ......................................–0.2 V to 2.45 V Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage ........................................ > 2001 V (MIL-STD-883, Method 3015) Latch up Current .................................................... > 200 mA Operating Range Device CY62137FV18 Range Ambient Temperature VCC [6] Industrial –40 °C to +85 °C 1.65 V to 2.25 V Electrical Characteristics Over the Operating Range Parameter Description Test Conditions 55 ns Unit Min Typ[7] Max 1.4 – – V – – 0.2 V VOH Output high voltage IOH = –0.1 mA VOL Output low voltage IOL = 0.1 mA VIH Input high voltage VCC = 1.65 V to 2.25 V 1.4 – VCC + 0.2 V V VIL Input low voltage VCC = 1.65 V to 2.25 V –0.2 – 0.4 V IIX Input leakage current GND < VI < VCC –1 – +1 A IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 A ICC VCC operating supply current f = fmax = 1/tRC VCC(max) = 2.25 V IOUT = 0 mA CMOS levels – 13 18 mA f = 1 MHz VCC(max) = 2.25 V – 1.6 2.5 mA [8] Automatic power-down CE > VCC0.2 V, or VCC(max) = 2.25 V current–CMOS inputs (BHE and BLE) > VCC0.2 V, VIN > VCC – 0.2 V, VIN < 0.2 V, f = fmax (address and data only), f = 0 (OE, WE) – 1 5 A ISB2 [8] Automatic power-down CE > V – 0.2 V, or VCC(max) = 2.25 V CC current–CMOS inputs (BHE and BLE) > VCC0.2 V, VIN > VCC – 0.2 V, or VIN < 0.2 V, f = 0 – 1 5 A ISB1 Notes 4. VIL(min) = –2.0 V for pulse durations less than 20 ns. 5. VIH(max)=VCC + 0.5 V for pulse durations less than 20 ns. 6. Full device AC operation assumes a minimum of 100 s ramp time from 0 to VCC(min) and 200 s wait time after VCC stabilization. 7. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C 8. Chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. Document #: 001-08030 Rev. *I Page 4 of 16 [+] Feedback CY62137FV18 MoBL® Capacitance Parameter [9] CIN Description Test Conditions Input capacitance COUT TA = 25 °C, f = 1 MHz, VCC = VCC(typ) Output capacitance Max Unit 10 pF 10 pF Thermal Resistance Parameter [9] Description JA Thermal resistance (Junction to Ambient) Thermal resistance JC (Junction to case) Test Conditions 48-ball VFBGA Unit Still air, soldered on a 3 × 4.5 inch, two-layer printed circuit 75 C/W board 10 C/W AC Test Loads and Waveforms Figure 2. AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF R2 INCLUDING JIG AND SCOPE Parameters R1 R2 RTH VTH 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V 1.80 V 13500 10800 6000 0.80 Unit V Note 9. Tested initially and after any design or process changes that may affect these parameters. Document #: 001-08030 Rev. *I Page 5 of 16 [+] Feedback CY62137FV18 MoBL® Data Retention Characteristics Over the Operating Range Parameter VDR ICCDR Description Conditions VCC for data retention [11] Data retention current VCC = 1.0 V, CE > VCC – 0.2 V, or (BHE and BLE) > VCC0.2 V, VIN > VCC – 0.2 V or VIN < 0.2 V Min Typ [10] Max Unit 1.0 – – V – 1 4 A tCDR [12] Chip deselect to data retention time 0 – – ns tR [13] Operation recovery time 55 – – ns Data Retention Waveform Figure 3. Data Retention Waveform [14] VCC CE or VCC(min) tCDR DATA RETENTION MODE VDR > 1.0 V VCC(min) tR BHE.BLE Notes 10. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C. 11. Chip enable (CE) and byte enables (BHE and BLE) must be tied to CMOS levels to meet the ISB1 / ISB2 / ICCDR spec. Other inputs can be left floating. 12. Tested initially and after any design or process changes that may affect these parameters. 13. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. 14. BHE.BLE is the AND of both BHE and BLE. Deselect the chip by either disabling chip enable signals or by disabling both BHE and BLE. Document #: 001-08030 Rev. *I Page 6 of 16 [+] Feedback CY62137FV18 MoBL® Switching Characteristics Over the Operating Range Parameter [15, 16] Description 55 ns Min Max Unit Read Cycle tRC Read cycle time 55 – ns tAA Address to data valid – 55 ns tOHA Data hold from address change 10 – ns tACE CE LOW to data valid – 55 ns tDOE OE LOW to data valid – 25 ns tLZOE OE LOW to low Z [17] 5 – ns tHZOE OE HIGH to high Z [17, 18] – 18 ns 10 – ns [17] tLZCE CE LOW to low Z tHZCE CE HIGH to high Z [17, 18] – 18 ns tPU CE LOW to power up 0 – ns tPD CE HIGH to power down – 55 ns tDBE BLE/BHE LOW to data valid – 55 ns tLZBE BLE/BHE LOW to low Z [17] 10 – ns tHZBE BLE/BHE HIGH to high Z [17, 18] – 18 ns tWC Write cycle time 45 – ns tSCE CE LOW to write end 35 – ns tAW Address setup to write end 35 – ns tHA Address hold from write end 0 – ns tSA Address setup to write start 0 – ns tPWE WE pulse width 35 – ns tBW BLE/BHE LOW to write end 35 – ns tSD Data setup to write end 25 – ns tHD Data hold from write end 0 – ns tHZWE WE LOW to high Z [17, 18] – 18 ns tLZWE WE HIGH to low Z [17] 10 – ns Write Cycle [19] Notes 15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1V/ns or less, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5. 16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Please see application note AN13842 for further clarification. 17. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 18. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state 19. The internal write time of the memory is defined by the overlap of WE, CE = VIL, BHE and/or BLE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 001-08030 Rev. *I Page 7 of 16 [+] Feedback CY62137FV18 MoBL® Switching Waveforms Figure 4. Read Cycle No.1 (Address Transition Controlled) [20, 21] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/BLE tHZBE tDBE tLZBE DATA OUT HIGHIMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE tPU VCC SUPPLY CURRENT 50% 50% ICC ISB Notes 20. The device is continuously selected. OE, CE = VIL, BHE and/or BLE = VIL. 21. WE is HIGH for read cycle. 22. Address valid before or similar to CE and BHE, BLE transition LOW. Document #: 001-08030 Rev. *I Page 8 of 16 [+] Feedback CY62137FV18 MoBL® Switching Waveforms (continued) Figure 6. Write Cycle No. 1 (WE Controlled) [23, 24] tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE/BLE OE DATA I/O tSD NOTE 25 tHD DATAIN tHZOE Figure 7. Write Cycle No. 2 (CE Controlled) [23, 24] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tBW BHE/BLE OE tSD DATA I/O tHD DATAIN NOTE 25 tHZOE Notes 23. Data I/O is high impedance if OE = VIH. 24. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 25. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-08030 Rev. *I Page 9 of 16 [+] Feedback CY62137FV18 MoBL® Switching Waveforms (continued) Figure 8. Write Cycle No. 3 (WE Controlled) [26] tWC ADDRESS tSCE CE tBW BHE/BLE tAW tHA tSA WE tPWE tSD DATA I/O NOTE 27 tHD DATAIN tLZWE tHZWE Figure 9. Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) [26] tWC ADDRESS CE tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tHZWE DATA I/O NOTE 27 tSD tHD DATAIN tLZWE Notes 26. If CE goes HIGH simultaneously with WE = VIH, the output remains in a high impedance state. 27. During this period, the I/Os are in output state. Do not apply input signals. Document #: 001-08030 Rev. *I Page 10 of 16 [+] Feedback CY62137FV18 MoBL® Truth Table CE WE OE BHE BLE [28] [28] High Z Deselect or power down Standby (ISB) X X Inputs or Outputs Mode Power H X X X[28] X X H H High Z Deselect or power down Standby (ISB) L H L L L Data out (I/O0–I/O15) Read Active (ICC) L H L H L Data out (I/O0–I/O7); I/O8–I/O15 in High Z Read Active (ICC) L H L L H Data out (I/O8–I/O15); I/O0–I/O7 in High Z Read Active (ICC) L H H L L High Z Output disabled Active (ICC) L H H H L High Z Output disabled Active (ICC) L H H L H High Z Output disabled Active (ICC) L L X L L Data in (I/O0–I/O15) Write Active (ICC) L L X H L Data in (I/O0–I/O7); I/O8–I/O15 in High Z Write Active (ICC) L L X L H Data in (I/O8–I/O15); I/O0–I/O7 in High Z Write Active (ICC) Note 28. The ‘X’ (Don’t care) state for the Chip enable (CE) and Byte enables (BHE and BLE) in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these pins is not permitted. Document #: 001-08030 Rev. *I Page 11 of 16 [+] Feedback CY62137FV18 MoBL® Ordering Information Speed (ns) 55 Ordering Code CY62137FV18LL-55BVXI Package Diagram Package Type 51-85150 48-ball VFBGA (Pb-free) Operating Range Industrial Contact your local Cypress sales representative for availability of other parts. Ordering Code Definitions CY 621 3 7 F V18 LL - 55 BV X I Temperature Grade: I = Industrial Pb-free Package Type: BV = 48-ball VFBGA Speed Grade: 55 ns Low Power Voltage Range: 1.8 V typical Process Technology: 90 nm Bus width = × 16 Density = 2-Mbit Family Code: MoBL SRAM family Company ID: CY = Cypress Document #: 001-08030 Rev. *I Page 12 of 16 [+] Feedback CY62137FV18 MoBL® Package Diagram Figure 10. 48-ball VFBGA (6 × 8 × 1 mm) BV48/BZ48, 51-85150 51-85150 *F Document #: 001-08030 Rev. *I Page 13 of 16 [+] Feedback CY62137FV18 MoBL® Acronyms Acronym Document Conventions Description Units of Measure BHE byte high enable BLE byte low enable °C degree Celsius CE chip enable MHz Mega Hertz CMOS complementary metal oxide semiconductor A micro Amperes I/O input/output s micro seconds OE output enable mA milli Amperes SRAM static random access memory mm milli meter VFBGA very fine-pitch ball grid array ns nano seconds WE write enable ohms % percent pF pico Farad V Volts W Watts Document #: 001-08030 Rev. *I Symbol Unit of Measure Page 14 of 16 [+] Feedback CY62137FV18 MoBL® Document History Page Document Title: CY62137FV18 MoBL®, 2-Mbit (128 K × 16) Static RAM Document Number: 001-08030 REV. ECN NO. Submission Date Orig. of Change Description of Change ** 463660 See ECN NXR New datasheet *A 469180 See ECN NSI Minor change: moved to external web *B 569125 See ECN NXR Converted from preliminary to final Replaced 45 ns speed bin with 55 ns speed bin Changed the ICC(max) value from 2.25 mA to 2.5 mA for test condition f=1 MHz Changed the ISB2(typ) value from 0.5 A to 1 A Changed the ISB2(max) value from 2.5 A to 5 A Changed the ICCDR(typ) value from 0.5 A to 1 A and ICCDR(max) value from 2.5 A to 4 A *C 869500 See ECN VKN Added footnote #12 related to tACE *D 908120 See ECN VKN Added footnote #8 related to ISB2 and ICCDR Made footnote #13 applicable to AC parameters from tACE Changed tWC specification from 45 ns to 55 ns Changed tSCE, tAW, tPWE, tBW specification from 35 ns to 40 ns Changed tHZWE specification from 18 ns to 20 ns *E 1274728 See ECN *F 2943752 06/03/2010 VKN *G 3055165 10/12/2010 RAME Added Contents Added Acronyms and Units of Measure Update Package Diagram from *E to *F Added Ordering Code Definitions details. Changed ISB1/ISB2/ICCDR test conditions to reflect byte power down feature *H 3061313 10/15/2010 RAME Minor Changes: Corrected CE to CE and WE to WE in Figures 7 and 8 *I 3263825 06/17/2011 RAME Replaced CE and OE with CE and OE in all instances in page 1. Updated Functional Description (Removed “For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.”). Updated in new template. Document #: 001-08030 Rev. *I VKN/AESA Changed tWC specification from 55 ns to 45 ns Changed tSCE, tAW, tPWE, tBW specification from 40 ns to 35 ns Changed tHZWE specification from 20 ns to 18 ns Added Contents Added footnote related to Chip enable and Byte enables in Truth Table Updated Package Diagram Added Sales, Solutions, and Legal Information Page 15 of 16 [+] Feedback CY62137FV18 MoBL® Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2006-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-08030 Rev. *I Revised June 17, 2011 Page 16 of 16 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback