DG2015 Vishay Siliconix Low-Voltage, Low RON, Dual DPDT Analog Switch DESCRIPTION FEATURES The DG2015 is a dual double-pole/double-throw monolithic CMOS analog switch designed for high performance switching of analog signals. Combining low power, high speed, low on-resistance and small physical size, the DG2015 is ideal for portable and battery powered applications requiring high performance and efficient use of board space. The DG2015 is built on Vishay Siliconix’s low voltage JI2 process. An epitaxial layer prevents latchup. Break-beforemake is guaranteed. The switch conducts equally well in both directions when on, and blocks up to the power supply level when off. • Halogen-free according to IEC 61249-2-21 Definition • Low Voltage Operation (2.7 V to 3.3 V) • Low On-Resistance - RON: 0.85 • 3 dB Loss at 100 MHz • Fast Switching: tON = 40 ns tOFF = 35 ns • QFN-16 Package • Compliant to RoHS Directive 2002/95/EC BENEFITS • • • • • Reduced Power Consumption High Accuracy Reduced Board Space Reduce Board Space TTL/1.8 V Logic Compatible APPLICATIONS • • • • • Cellular Phones Speaker Headset Switching Audio and Video Signal Routing PCMCIA Cards Battery Operated Systems FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION DG2015 QFN-16 (4 x 4) NC1 COM1 GND COM4 16 15 14 13 NO1 1 12 NC4 INA 2 11 NO4 TRUTH TABLE NO2 3 10 INB NC2 4 9 NO3 5 6 COM2 V+ 7 Logic NC1, 2, 3 and 4 NO1, 2, 3 and 4 0 ON OFF 1 OFF ON 8 COM3 NC3 Top View ORDERING INFORMATION Temp Range - 40 °C to 85 °C Document Number: 71971 S11-1185-Rev. C, 13-Jun-11 Package 16-pin QFN (4 mm x 4 mm) Part Number DG2015DN-T1-E4 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG2015 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Limit Reference V+ to GND Unit - 0.3 to + 6 IN, COM, NC, NOa V - 0.3 to (V+ + 0.3) Current (Any terminal except NO, NC or COM) 30 Continuous Current (NO, NC, or COM) ± 150 Peak Current (Pulsed at 1 ms, 10 % duty cycle) ± 200 Storage Temperature (D Suffix) mA - 65 to 150 d Package Solder Reflow Conditions 16-pin QFN (4 mm x 4 mm) 240 Power Dissipation (Packages)b QFN-16c 1880 °C mW Notes: a. Signals on NC, NO, or COM or IN exceeding V+ will be clamped by internal diodes. Limit forward diode current to maximum current ratings. b. All leads welded or soldered to PC Board. c. Derate 23.5 mW/°C above 70 °C. d. Manual soldering with iron is not recommended for leadless components. The QFN is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper lip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. SPECIFICATIONS (V+ = 3 V) Parameter Symbol Test Conditions Otherwise Unless Specified V+ = 3 V, ± 10 %, VIN = 0.4 V or 2 Ve Limits - 40 °C to 85 °C Temp.a Min.b Full 0 Typ.c Unit Max.b Analog Switch Analog Signal Ranged On-Resistance RON Flatness RON Match Switch Off Leakage Current Channel-On Leakage Current Digital Control VNO, VNC VCOM RON V+ = 2.7 V, VCOM = 0.2 V/1.5 V, INO, INC = 100 mA RON Flatness RON V+ = 2.7 V, VCOM = 0 V to V+, INO, INC = 100 mA INO(off) INC(off) ICOM(off) ICOM(on) V+ = 3.3 V VNO, VNC = 1 V/3 V, VCOM = 3 V/1 V V+ = 3.3 V, VNO, VNC = VCOM = 1 V/3 V Room Full 0.85 Room 0.16 Room 0.15 1 10 Room Full Room Full -1 - 10 -1 - 10 1 10 1 10 2 VINH Full VINL Full Cin IINL or IINH Input Current 0.4 Full VIN = 0 V or V+ -1 - 10 Input Low Voltage Full 4 -1 V 1.6 1.7 Room Full Input High Voltage Input Capacitance V+ nA V pF 1 µA Dynamic Characteristics Turn-On Time tON Turn-Off Time tOFF Break-Before-Make Time d Charge Injection d td QINJ Off-Isolation OIRR Crosstalkd XTALK NO, NC Off Capacitanced Channel-On Capacitanced www.vishay.com 2 VNO or VNC = 2 V, RL = 300 , CL = 35 pF Room Full Room Full Full CL = 1 nF, VGEN = 0 V, RGEN = 0 RL = 50 , CL = 5 pF, f = 1 MHz 40 35 1 7 Room - 67 Room - 70 Room 63 CNC(off) Room 67 Room 200 Room 196 CNC(on VIN = 0 V or V+, f = 1 MHz ns 3 Room CNO(off) CNO(on) 65 67 60 62 pC dB pF Document Number: 71971 S11-1185-Rev. C, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG2015 Vishay Siliconix SPECIFICATIONS (V+ = 3 V) Parameter Limits - 40 °C to 85 °C Test Conditions Otherwise Unless Specified V+ = 3 V, ± 10 %, VIN = 0.4 V or 2 Ve Symbol Temp.a Min.b Typ.c Unit Max.b Power Supply Power Supply Range V+ Power Supply Current I+ Power Consumption PC 2.7 VIN = 0 V or V+ 3.3 V Full 1 µA Full 3.3 µW Notes: a. Room = 25 °C, full = as determined by the operating suffix. b. Typical values are for design aid only, not guaranteed nor subject to production testing. c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. d. Guarantee by design, nor subjected to production test. e. VIN = input voltage to perform proper function. f. Guaranteed by 5 V leakage testing, not production tested. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2.5 T = 25 °C IS = 100 mA IS = 100 mA 2.0 RON - On-Resistance () R ON - On-Resistance () 2.0 2.5 1.5 V+ = 3.0 V, 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 V+ = 3 V 85 °C 1.5 25 °C - 40 °C 1.0 0.5 0.0 0.0 3.0 0.5 VCOM - Analog Voltage (V) RON vs. VCOM and Supply Voltage 1.5 2.0 2.5 3.0 RON vs. Analog Voltage and Temperature 100 10 mA V+ = 3 V VIN = 0 V 1 mA I+ - Supply Current (A) I+ - Supply Current (nA) 1.0 VCOM - Analog Voltage (V) 10 1 V+ = 3 V 100 µA 10 µA 1 µA 100 nA 10 nA 1 nA 0.1 - 60 100 pA - 40 - 20 0 20 40 60 80 Temperature (°C) Supply Current vs. Temperature Document Number: 71971 S11-1185-Rev. C, 13-Jun-11 100 10 100 1K 10 K 100 K 1M 10 M Input Switching Frequency (Hz) Supply Current vs. Input Switching Frequency www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG2015 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 800 1000 600 Leakage Current (pA) Leakage Current (pA) V+ = 3 V 100 ICOM(on) ICOM(off) 10 INO(off), IINC(off) V+ = 3 V ICOM(off) 400 ICOM(on) 200 0 - 200 INO(off), IINC(off) - 400 - 600 1 - 60 - 40 - 20 0 20 40 60 80 100 - 800 0.0 Temperature (°C) 0.5 Leakage Current vs. Temperature 2.5 3.0 LOSS - 10 Loss, OIRR, X TALK (dB) 50 tON V+ = 3 V 40 tOFF V+ = 3 V 30 - 30 - 50 OIRR XTA LK V+ = 3 V RL = 50 - 70 - 40 - 20 0 20 40 60 80 - 90 100 K 100 1M Temperature (°C) 10 M 100 M 1G Frequency (Hz) Switching Time vs. Temperature Insertion Loss, Off-Isolation Crosstalk vs. Frequency 3.0 30 2.5 25 Q - Charge Injection (pC) - Switching Threshold (V) 2.0 10 20 - 60 VT 1.5 Leakage vs. Analog Voltage 60 t ON / t OFF - Switching Time (s) 1.0 VCOM, V NO, V NC - Analog Voltage (V) 2.0 1.5 1.0 20 15 V+ = 3 V 10 5 0.5 0 0.0 0 1 2 3 4 5 V+ - Supply Voltage (V) 6 7 0 1 2 3 4 VCOM - Analog Voltage (V) 5 6 Switching Threshold vs. Supply Voltage Charge Injection vs. Analog Voltage www.vishay.com 4 Document Number: 71971 S11-1185-Rev. C, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG2015 Vishay Siliconix TEST CIRCUITS V+ VINH Logic Input V+ NO or NC Switch Input VINL Switch Output COM tr < 5 ns tf < 5 ns 50 % VOUT 0.9 x V OUT IN Logic Input RL 300 GND Switch Output CL 35 pF 0V tOFF tON 0V Logic "1" = Switch On Logic input waveforms inverted for switches that have the opposite logic sense. CL (includes fixture and stray capacitance) V OUT = V COM RL R L + R ON Figure 1. Switching Time V+ Logic Input V+ VNO VNC COM NO VINH tr < 5 ns tf < 5 ns VINL VO NC RL 300 IN CL 35 pF GND VNC = V NO VO 90 % Switch 0V Output tD tD CL (includes fixture and stray capacitance) Figure 2. Break-Before-Make Interval V+ Rgen VOUT V+ COM NC or NO VOUT VOUT + IN IN Vgen CL = 1 nF VIN = 0 – V+ On Off On GND Q = VOUT x CL IN depends on switch configuration: input polarity determined by sense of switch. Figure 3. Charge Injection Document Number: 71971 S11-1185-Rev. C, 13-Jun-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 DG2015 Vishay Siliconix TEST CIRCUITS V+ 10 nF V+ NC or NO 0V, 2.4 V IN COM COM RL Analyzer GND VCOM Off Isolation = 20 log V NO/ NC Figure 4. Off-Isolation V+ 10 nF V+ COM Meter IN 0 V, 2.4 V NC or NO HP4192A Impedance Analyzer or Equivalent GND f = 1 MHz Figure 5. Channel Off/On Capacitance Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71971. www.vishay.com 6 Document Number: 71971 S11-1185-Rev. C, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix QFN−16 (4 4 mm) JEDEC Part Number: MO-220 D -B- ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ Index Area (Dń2 Eń2) 4 D/2 AA E/2 BB E -ACC DD aaa C 2 X aaa C 2 X Detail A Top View // ccc C Nx 9 Seating Plane 0.08 C -C- Side View A A1 A3 D2 N L Detail B D2/2 Datum A or B N r E2/2 6 (NE-1) x e E2 2 Exposed Pad N b N N-1 8 e/2 5 e 5 5 bbb M C A B Detail A Terminal Tip Terminal Tip 1 e (ND-1) x e Even Terminal/Side 8 Odd Terminal/Side Detail B Bottom View Document Number: 71921 19-Aug-02 www.vishay.com 1 Package Information Vishay Siliconix QFN−16 (4 4 mm) JEDEC Part Number: MO-220 MILLIMETERS* Dim Min Nom A 0.80 0.90 A1 0 0.02 A3 0.20 Ref AA 0.345 aaa 0.25 BB 0.345 b 0.23 0.30 bbb 0.10 CC 0.18 ccc 0.10 D 4.00 BSC D2 2.00 2.15 DD 0.18 E 4.00 BSC E2 2.00 2.15 e 0.65 BSC L 0.45 0.55 N 16 ND 4 NE 4 r b(min)/2 * Use millimeters as the primary measurement. INCHES Max Min Nom Max 1.00 0.05 0.38 - 0.0315 0 0.0091 - 0.0394 0.0020 0.0150 - 2.25 - 0.0787 - 2.25 0.0787 0.65 0.0177 - b(min)/2 0.0354 0.0008 0.0079 0.0136 0.0098 0.0136 0.0118 0.0039 0.0071 0.0039 0.1575 BSC 0.0846 0.0071 0.1575 BSC 0.0846 0.0256 BSC 0.0217 16 4 4 - Notes 5 0.0886 0.0886 0.0256 - 3, 7 6 6 ECN: S-21437—Rev. A, 19-Aug-02 DWG: 5890 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5M-1994. 2. All dimensions are in millimeters. All angels are in degrees. 3. N is the total number of terminals. 4. The terminal #1 identifier and terminal numbering convention shall conform to JESD 95-1 SPP-012. Details of terminal #1 identifier are optional, but must be located within the zone indicated. The terminal #1 identifier may be either a molded or marked feature. The X and Y dimension will vary according to lead counts. 5. Dimension b applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from the terminal tip. 6. ND and NE refer to the number of terminals on the D and E side respectively. 7. Depopulation is possible in a symmetrical fashion. 8. Variation HHD is shown for illustration only. 9. Coplanarity applies to the exposed heat sink slug as well as the terminals. www.vishay.com 2 Document Number: 71921 19-Aug-02 AN505 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR QFN-16 (4 x 4 MM BODY) C1 X2 16 15 14 13 E 12 1 2 C2 11 Keep Out Zone Y2 3 10 4 9 5 6 7 8 Y1 X1 Inches Millimeters C1 0.142 3.60 C2 0.142 3.60 E 0.026 0.65 X1 0.014 0.35 X2 0.089 2.25 Y1 0.037 0.95 Y2 0.089 2.25 Note: QFN-16 (4 x 4) has an exposed center pad that must not come into contact with any metalized structure on the PCB. This area is considered a Keep Out Zone. Document Number: 74976 19-Apr-07 www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1