VISHAY DG9434DQ-T1-E3

DG9432, DG9433, DG9434
Vishay Siliconix
Low-Voltage Dual SPST Analog Switch
DESCRIPTION
FEATURES
The DG9432, DG9433, DG9434 is a dual single-pole/singlethrow monolithic CMOS analog switch designed for high
performance switching of analog signals. Combining low
power, high speed (tON: 25 ns, tOFF: 20 ns), the DG9432,
DG9433, DG9434 is ideal for portable and battery powered
applications requiring high performance and efficient use of
board space.
•
•
•
•
The DG9432, DG9433, DG9434 is built on Vishay Siliconix’s
low voltage BCD-15 process. An epitaxial layer prevents
latchup. Break-before-make is guaranteed for DG9432,
DG9433, DG9434.
Each switch conducts equally well in both directions when
on, and blocks up to the power supply level when off.
Wide operation voltage (+ 2.7 V to + 12 V)
Low charge injection - QINJ: 1 pC
Low power consumption
TTL/CMOS logic compatible over the full
operating voltage range
• Available in MSOP-8 and SOT23-8
• Compliant to RoHS Directive 2002/95/EC
BENEFITS
•
•
•
•
Reduced power consumption
Simple logic interface
High accuracy
Reduce board space
APPLICATIONS
•
•
•
•
•
•
•
Battery operated systems
Portable test equipment
Sample and hold circuits
Cellular phones
Communication systems
Military radio
PBX, PABX guidance and control systems
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION - DG9432
DG9432, SOT23-8
DG9432, MSOP-8
NC1
1
8
V+
NC1
1
8
COM1
COM1
2
7
IN1
V+
2
7
IN1
IN2
3
6
COM2
IN2
3
6
GND
GND
4
5
NC2
COM2
4
5
NC2
Top View
Top View
Device Marking: 9432
Device Marking: 4G
TRUTH TABLE DG9432
Document Number: 72311
S11-1029-Rev. B, 23-May-11
Logic
Switch
0
On
1
Off
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1
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION - DG9433/DG9434
DG9433. SOT23-8
DG9433, MSOP-8
NO1
1
8
V+
NO1
1
8
COM1
COM1
2
7
IN1
V+
2
7
IN1
IN2
3
6
COM2
IN2
3
6
GND
GND
4
5
NO2
COM2
4
5
NO2
Top View
Top View
Device Marking: 9433
Device Marking: 4H
TRUTH TABLE DG9433
Logic
Switch
0
Off
1
On
DG9434. SOT23-8
DG9434, MSOP-8
NO
1
8
V+
NO1
1
8
COM1
COM1
2
7
IN1
V+
2
7
IN1
IN2
3
6
COM2
IN2
3
6
GND
GND
4
5
NC2
COM2
4
5
NC2
Top View
Top View
Device Marking: 9434
Device Marking: 4I
TRUTH TABLE DG9434
Logic
Switch-1
0
Off
Switch-2
On
1
On
Off
Package
Part Number
DG9432DQ-T1-E3
MSOP-8
DG9433DQ-T1-E3
ORDERING INFORMATION
Temp. Range
DG9434DQ-T1-E3
- 40 °C to 85 °C
DG9432DS-T1-E3
SOT23-8
DG9433DS-T1-E3
DG9433DS-T1-E3
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Document Number: 72311
S11-1029-Rev. B, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Parameter
Limit
Reference V+ to GND
Unit
- 0.3 to + 13.5
IN, COM, NC, NOa
V
- 0.3 to (V+ + 0.3)
Continuous Current (Any terminal)
± 10
Peak Current (Pulsed at 1 ms, 10 % duty cycle)
± 20
Storage Temperature (D suffix)
mA
- 65 to 150
Power Dissipation (Packages)b
c
MSOP-8
320
SOT23-8c
515
°C
mW
Notes:
a. Signals on SX, DX, or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings.
b. All leads welded or soldered to PC board.
c. Derate 6.5 mW/°C above 75 °C.
SPECIFICATIONS V+ = 3 V
Test Conditions
Otherwise Unless Specified
V+ = 3.3 V, ± 10 %, VIN = 0.4 V or 1.8 Ve
Limits
- 40 °C °C to 85 °C
Temp.a
Min.c
VANALOG
Full
V-
Drain-Source On- Resistance
R(on)
RON Matchd
Ron
Parameter
Symbol
Unit
Typ.b
Max.c
V+
V
Room
Full
81
100
120

Room
0.4
3.0
Switch On Resistance
Analog Signal Rangee
V+ = 2.7 V, ICOM = 1 mA, VCOM = 1.5 V
Digital Control
Input, High Voltage
VINH
Input, Low Voltage
VINL
Input Current
IINH
V+ Ranges 2.7 to 5 V
Full
1.8
Full
0.4
-1
1
V
µA
Dynamic Characteristics
Break-Before-Maked,g
tOPEN
Room
Full
60
80
100
Room
Full
14
25
35
Q
CL = 1 nF, RGEN = 0 , Vg = 0 V
Room
0.16
OIRR
CL = 5 pF, RL = 50 , f = 1 MHz
Room
77
CL = 5 pF, RL = 50 , f = 10 MHz
Room
55
XTALK
RL = 50 , f = 1 MHz, V+ = 2.5 V
Room
98
CNO/NC(off)
f = 1 MHz, VNC/NO = 0 V
Room
7.5
Room
7.8
Room
22
tON
Turn-Off Timed
tOFF
Off-Isolationd
Crosstalk
d
Source Off Capacitanced
1
V+ = 3 V, RL = 300 
VNO = VNC = 1.5 V
CL = 35 pF, VIN = 0 V, 3 V
Turn-On Timed
Charge Injectiond
Room
Full
Drain Off Capacitanced
CCOM(off)
Drain On Capacitanced
CCOM(on)
f = 1 MHz VCOM = 0 V
ns
pC
dB
pF
V+ = 3.3 V, VIN = 0 or V+
Room
-1
-1
µA
Supply Current
I+
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
d. Guarantee by design, not subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by 12 V leakage testing, not production tested.
g. Applies for DG9434 only.
Document Number: 72311
S11-1029-Rev. B, 23-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
SPECIFICATIONS V+ = 5 V
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 5 V, ± 10 %, VIN = 0.4 V or 1.8 Ve
Limits
- 40 °C °C to 85 °C
Temp.a
Min.c
Full
V-
Typ.b
Unit
Max.c
Switch On Resistance
Analog Signal Rangee
Drain-Source On-Resistance
RDS(on) Match
VANALOG

V+ = 4.5 V, ICOM = 1 mA
VCOM = 2.5 V or 3.5 V
Room
Full
39
60
70
R(on)
V+ = 4.5 V, ICOM = 1 mA, VCOM = 3.5 V
Room
0.3
3.0
Currentf
ICOM(off)
Channel On Leakage Currentf
V
R(on)
INC/NO(off)
Switch Off Leakage
V+
V+ = 5 V, VCOM = 0.5 V, 4.5 V
VNC/NO = 4.5 V, 0.5 V
ICOM(on)
Room
Full
-1
- 10
0.3
1
10
Room
Full
-1
- 10
0.3
1
10
Room
Full
-1
- 10
0.3
1
10
Full
1.8
nA
Digital Control
Input, High Voltage
VINH
Input, Low Voltage
VINL
Input Current
IINH
V+ Ranges 2.7 to 5 V
Full
0.4
-1
V
1
µA
ns
Dynamic Characteristics
Break-Before-Maked,g
tOPEN
60
70
Room
Full
10
20
30
CL = 1 nF, RGEN = 0 , Vg = 0 V
Room
0.56
OIRR
CL = 5 pF, RL = 50 , f = 1 MHz
Room
76
CL = 5 pF, RL = 50 , f = 10 MHz, V+ = 5 V
Room
54
XTALK
RL = 50 , f = 1 MHz, V+ = 5 V
Room
96
CNC/NO(off)
f = 1 MHz, VNC/NO = 0 V
Turn-Off Time
tOFF
Q
d
Crosstalk
Source Off Capacitanced
d
Drain Off Capacitance
d
Drain On Capacitance
Supply Current
1
33
tON
Off-Isolationd
Room
Full
Room
Full
Turn-On Time
Charge Injectiond
V+ = 5 V, RL = 300 
VNO = VNC = 3 V
CL = 35 pF, VIN = 0 V, 5 V
CCOM(off)
CCOM(on)
I+
f = 1 MHz, VCOM = 0 V
V+ = 5.5 V, VIN = 0 or V+
Room
7.5
Room
7.8
Room
Room
pC
dB
pF
22
-1
-1
µA
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
d. Guarantee by design, not subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by 12 V leakage testing, not production tested.
g. Applies for DG9434 only.
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Document Number: 72311
S11-1029-Rev. B, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
SPECIFICATIONS V+ = 12 V
Parameter
Symbol
Test Conditions
Otherwise Unless Specified
V+ = 12 V, ± 10 %, VIN = 0.8 V or 2.4 Ve
Limits
- 40 °C °C to 85 °C
Temp.a
Min.c
Full
V-
Typ.b
Unit
Max.c
Switch On Resistance
Analog Signal Rangee
Drain-Source On-Resistance
VANALOG
R(on)
R(on)
RDS(on) Match
V+ = 10.8 V, ICOM = 1 mA, VCOM = 9 V
INC/NO(off)
Switch Off Leakage Currenta
ICOM(off)
Channel On Leakage Currenta
V+ = 12 V, VS = 1/11 V, VCOM = 11/1 V
ICOM(on)
V+
V

Room
Full
19
30
40
Room
0.3
3.0
Room
Full
-1
- 10
0.3
1
10
Room
Full
-1
- 10
0.3
1
10
Room
Full
-1
- 10
0.3
1
10
nA
Digital Control
Input, High Voltage
VINH
Input, Low Voltage
VINL
Input Current
IINH
V+ = 12 V
Full
Full
2.4
0.8
-1
V
1
µA
ns
Dynamic Characteristics
Break-Before-Maked,g
tOPEN
Room
Full
21
35
40
Room
Full
6
18
25
CL = 1 nF, RGEN = 0 , Vg = 0 V, V+ = 5 V
Room
0.36
OIRR
CL = 5 pF, RL = 50 , f = 1 MHz
Room
75
CL = 5 pF, RL = 50 , f = 10 MHz
Room
53
XTALK
RL = 50 , f = 1 MHz, V+ = 5 V
Room
96
CNO/NC(off)
f = 1 MHz, VNC/NO = 0 V
Room
7.5
Room
7.8
Room
22
tON
Turn-Off Time
tOFF
Q
Off-Isolationd
Crosstalk
d
Source Off Capacitanced
d
CCOM(off)
Drain On Capacitanced
CCOM(on)
Drain Off Capacitance
Supply Current
1
V+ = 12 V, RL = 300 
VNO = VNC = 8 V
CL = 35 pF, VIN = 0 V, 12 V
Turn-On Time
Charge Injectiond
Room
Full
I+
f = 1 MHz, VCOM = 0 V
V+ = 12 V, VIN = 0 or V+
Room
-1
pC
dB
pF
-1
µA
Notes:
a. Room = 25 °C, Full = as determined by the operating suffix.
b. Typical values are for design aid only, not guaranteed nor subject to production testing.
c. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this datasheet.
d. Guarantee by design, not subjected to production test.
e. VIN = input voltage to perform proper function.
f. Guaranteed by 12 V leakage testing, not production tested.
g. Applies for DG9434 only.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Document Number: 72311
S11-1029-Rev. B, 23-May-11
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
150
120
T = 25 °C
IS = 1 mA
A = 85 °C
B = 25 °C
C = - 40 °C
ICOM = 1 mA
125
V+ = 2.5 V
R ON - On-Resistance (Ω)
R ON - On-Resistance (Ω)
100
80
60
V+ = 5 V
40
V+ = 10 V
100
V+ = 2.5 V
A
75
V+ = 12 V
B
V+ = 5 V
C
50
25
20
A
A
B
C
B
C
V+ = 12 V
0
0
0
2
4
6
8
10
0
12
2
4
VCOM - Analog Voltage (V)
RON vs. VCOM and Single Supply Voltage
8
10
12
RON vs. Analog Voltage and Temperature
200
100
V+ = 12 V
150
INO(off)
10
100
ICOM(off)
Leakage Current (pA)
Leakage Current (pA)
6
VCOM - Analog Voltage (V)
ICOM(on)
ICOM(off)
ICOM(on)
50
0
- 50
INO(off)/INC(off)
- 100
- 150
1
- 60
- 200
- 40
- 20
0
20
40
60
80
0
100
2
6
8
10
12
VCOM, V NO, V NC - Analog Voltage
Temperature (°C)
Leakage Current vs. Analog Voltage
Leakage Current vs. Temperature
100
1000
tON V+ = 2.5 V
80
I+ - Supply Current (pA)
tON, tOFF - Switching Time (ns)
4
60
tON V+ = 5 V
40
100
V+ = 5 V
VIN = 0 V
10
1
20
tOFF V+ = 2.5 V
tOFF V+ = 5 V
0
- 60
- 40
- 20
0
20
40
60
80
Temperature (°C)
Switching Time vs. Temperature
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100
0.1
- 60
- 40
- 20
0
20
40
60
80
100
Temperature (°C)
Supply Current vs. Temperature
Document Number: 72311
S11-1029-Rev. B, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
0.8
2.5
0.6
V+ = 2.5 V
0.4
V+ = 5 V
0.2
1.5
Qinj (pc)
VT - Switching Threshold
2.0
- 0.0
- 0.2
1.0
- 0.4
- 0.6
0.5
- 0.8
0.0
- 1.0
0
2
4
6
8
10
12
0
14
1
3
4
5
6
VCOM - Analog Voltage (V)
V+ - Supply Voltage
Switching Threshold vs. Supply Voltage
Charge Injection at Source
1000
20
0
2
Insertion Loss
- 3 dB = 260 MHz
Loss (dB)
- 20
I+ Supply Current (µA)
800
V+ = 3 V, 5 V
RL = 50 Ω
- 40
OIRR
- 60
- 80
600
400
200
Crosstalk
- 100
0
- 120
100K
1M
10M
100M
Frequency (MHz)
Insertion Loss, Off Isolation and Crosstalk
vs. Frequency
Document Number: 72311
S11-1029-Rev. B, 23-May-11
1G
0
2M
4M
6M
8M
10M
Input Switching Frequency
Supply Current vs. Input Switching Frequency
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This document is subject to change without notice.
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DG9432, DG9433, DG9434
Vishay Siliconix
TEST CIRCUITS
V+
Logic
Input
50 %
V+
NO or NC
Switch
Input
tr < 20 ns
tf < 20 ns
0V
Switch Output
COM
VOUT
0.9 x V OUT
Switch
Output
IN
Logic
Input
RL
300 Ω
GND
CL
35 pF
0V
tON
tOFF
0V
Logic "1" = Switch On
Logic input waveforms inverted for switches that have
the opposite logic sense.
CL (includes fixture and stray capacitance)
RL
VOUT = VCOM
R L + R ON
Figure 1. Switching Time
V+
Logic
Input
V+
V1
NO or NC
COM1
NO or NC
COM2
V2
tr < 5 ns
tf < 5 ns
0V
RL
300 Ω
CL
35 pF
GND
VNC = VNO
VO
Switch
Output
90 %
0V
tD
tD
CL (includes fixture and stray capacitance)
Figure 2. Break-Before-Make Interval
V+
Rgen
ΔVOUT
V+
NC or NO
COM
VOUT
VOUT
+
IN
Vgen
CL
3V
IN
On
Off
On
GND
Q = ΔVOUT x CL
IN depends on switch configuration: input polarity
determined by sense of switch.
Figure 3. Charge Injection
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Document Number: 72311
S11-1029-Rev. B, 23-May-11
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
DG9432, DG9433, DG9434
Vishay Siliconix
TEST CIRCUITS
V+
10 nF
V+
COM
IN
COM
0 V, 2.4 V
NC or NO
V NC/ NO
Off Isolation = 20 log
RL
GND
V COM
Analyzer
Figure 4. Off-Isolation
V+
10 nF
V+
COM
Meter
IN
0 V, 2.4 V
NC or NO
GND
HP4192A
Impedance
Analyzer
or Equivalent
f = 1 MHz
Figure 5. Channel Off/On Capacitance
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?72311.
Document Number: 72311
S11-1029-Rev. B, 23-May-11
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This document is subject to change without notice.
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Package Information
Vishay Siliconix
MSOP:
8−LEADS
JEDEC Part Number: MO-187, (Variation AA and BA)
(N/2) Tips)
2X
5
A B C 0.20
N N-1
0.60
0.48 Max
Detail “B”
(Scale: 30/1)
Dambar Protrusion
E
1 2
0.50
N/2
0.60
0.08 M C B S
b
A S
7
Top View
b1
e1
With Plating
e
A
See Detail “B”
c1
0.10 C
-H-
A1
D
6
Seating Plane
c
Section “C-C”
Scale: 100/1
(See Note 8)
Base Metal
-A-
3
See Detail “A”
Side View
0.25
BSC
C
Parting Line
0.07 R. Min
2 Places
Seating Plane
ς
A2
0.05 S
C
E1
-B-
L 4
T
-C-
3
0.95
End View
Detail “A”
(Scale: 30/1)
N = 8L
NOTES:
1.
Die thickness allowable is 0.203"0.0127.
2.
Dimensioning and tolerances per ANSI.Y14.5M-1994.
3.
Dimensions “D” and “E1” do not include mold flash or protrusions, and are
measured at Datum plane -H- , mold flash or protrusions shall not exceed
0.15 mm per side.
4.
Dimension is the length of terminal for soldering to a substrate.
5.
Terminal positions are shown for reference only.
6.
Formed leads shall be planar with respect to one another within 0.10 mm at
seating plane.
7.
The lead width dimension does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08 mm total in excess of the lead width
dimension at maximum material condition. Dambar cannot be located on the
lower radius or the lead foot. Minimum space between protrusions and an
adjacent lead to be 0.14 mm. See detail “B” and Section “C-C”.
8.
Section “C-C” to be determined at 0.10 mm to 0.25 mm from the lead tip.
9.
Controlling dimension: millimeters.
10. This part is compliant with JEDEC registration MO-187, variation AA and BA.
11. Datums -A- and -B- to be determined Datum plane -H- .
MILLIMETERS
Dim
Min
Nom
Max
A
A1
A2
b
b1
c
c1
D
E
E1
e
e1
L
N
T
-
-
1.10
0.05
0.10
0.15
0.75
0.85
0.95
0.25
-
0.38
8
0.25
0.30
0.33
8
0.13
-
0.23
0.15
0.18
0.13
3.00 BSC
Note
3
4.90 BSC
2.90
3.00
3.10
3
0.70
4
0.65 BSC
1.95 BSC
0.40
0.55
8
0_
4_
5
6_
ECN: T-02080—Rev. C, 15-Jul-02
DWG: 5867
12. Exposed pad area in bottom side is the same as teh leadframe pad size.
Document Number: 71244
12-Jul-02
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Package Information
Vishay Siliconix
SOT−23 :
8−LEAD
b
e
CL
E1
CL
E
e1
D
CL
A
CL
A2
T
A1
DATUM A
- A-
E1
C
0.10
L
MILLIMETERS
NOTES:
1.
All dimensions are in millimeters.
2.
Foot length measured at intercept point between Datum A and
lead surface.
3.
4.
5.
2
0.20
- A-
Package outline exclusive of mold flash and metal burr.
Package outline inclusive of solder plating.
No molding flash allowed on the top and bottom lead surface.
Dim
Min
A
A1
A2
b
C
D
E
E1
e
e1
L
T
INCHES
Nom
Max
Min
Nom
Max
0.90
1.27
1.45
0.00
0.0762
0.15
0.035
0.05
0.057
0.000
0.003
0.90
1.20
0.006
1.30
0.035
0.047
0.051
0.22
0.09
0.30
0.38
0.009
0.012
0.015
0.152
0.20
0.004
0.006
2.80
0.008
2.9
3.00
0.11
0.114
0.118
2.60
2.8
23.00
0.102
0.11
0.118
1.50
1.65
1.75
0.059
0.065
0.069
0.65 REF
0.026 REF
1.95 REF
0.077 REF
0.35
0.45
0.55
0.014
0.018
0.022
0_
4_
8_
0_
4_
8_
ECN: C-03085—Rev. A, 07-Apr-03
DWG: 5895
Document Number: 72207
09-Apr-03
www.vishay.com
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Legal Disclaimer Notice
Vishay
Disclaimer
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Document Number: 91000
Revision: 11-Mar-11
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