HEF4511B BCD to 7-segment latch/decoder/driver Rev. 06 — 7 December 2009 Product data sheet 1. General description The HEF4511B is a BCD to 7-segment latch/decoder/driver with four address inputs (D0 to D3), an active HIGH latch enable input (LE), an active LOW ripple blanking input (BL), an active LOW lamp test input (LT), and seven active HIGH NPN bipolar transistor segment outputs (Qa to Qg). When LE is LOW and BL is HIGH, the state of the segment outputs (Qa to Qg) is determined by the data on D0 to D3. When LE goes HIGH, the last data present on D0 to D3 is stored in the latches and the segment outputs remain unchanged. When LT is LOW, all of the segment outputs are HIGH independent of all other input conditions. With LT HIGH, a LOW on BL forces all segment outputs LOW. The inputs LT and BL do not affect the latch circuit. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range −40 °C to +125 °C Complies with JEDEC standard JESD 13-B 3. Applications Automotive and industrial 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number Package Name Description Version HEF4511BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4 HEF4511BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 5. Functional diagram 7 1 2 6 D0 D1 D2 D3 5 LE LATCHES 4 BL DECODER 3 LT DRIVERS Qg Qf Qe Qd Qc Qb Qa 14 15 9 10 11 12 13 001aae675 Fig 1. Functional diagram VDD driver logic IOH + VOH − VSS Fig 2. 001aae677 Schematic diagram of output stage HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 2 of 19 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx D1 D Q D2 D Q D latch CP 2 latch CP 1 Q BL D latch CP 3 Q Q D3 NXP Semiconductors HEF4511B_6 Product data sheet D0 Q latch CP 4 Q Q LE Rev. 06 — 7 December 2009 Qf Qe Qd Qc Qb Qa 3 of 19 © NXP B.V. 2009. All rights reserved. 001aae679 Fig 3. Logic diagram HEF4511B Qg BCD to 7-segment latch/decoder/driver LT HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 6. Pinning information 6.1 Pinning HEF4511B D1 1 16 VDD D2 2 15 Qf LT 3 14 Qg BL 4 13 Qa LE 5 12 Qb D3 6 11 Qc D0 7 10 Qd VSS 8 9 Qe 001aae676 Fig 4. Pin configuration DIP16 and SO16 6.2 Pin description Table 2. Pin description Symbol Pin Description LT 3 lamp test input (active LOW) BL 4 ripple blanking input (active LOW) LE 5 latch enable input (active HIGH) D0 to D3 7, 1, 2, 6 address (data) input VSS 8 ground supply voltage Qa to Qg 13, 12, 11, 10, 9, 15, 14 segment output VDD 16 supply voltage HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 4 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 7. Functional description Function table[1] Table 3. Inputs Outputs LE BL X X L X X X X H H H H H H H 8 X L H X X X X L L L L L L L blank L H H L L L L H H H H H H L 0 L H H L L L H L H H L L L L 1 L H H L L H L H H L H H L H 2 L H H L L H H H H H H L L H 3 L H H L H L L L H H L L H H 4 L H H L H L H H L H H L H H 5 L H H L H H L L L H H H H H 6 L H H L H H H H H H L L L L 7 L H H H L L L H H H H H H H 8 L H H H L L H H H H L L H H 9 L H H H L H X L L L L L L L blank L H H H H X X L L L L L L L blank H H H X X X X N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. [1] LT D3 D2 D1 D0 Qa Qb Display Qc Qd Qe Qf Qg H = HIGH voltage level; L = LOW voltage level; X = don’t care; N.C. = no change. a f e g d b c 001aaj494 Fig 5. Seven segment digital display with segment designation HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 5 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IOH HIGH-level output current IDD supply current - Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +125 °C Ptot total power dissipation P power dissipation Conditions Min VI < −0.5 V or VI > VDD + 0.5 V Max −0.5 +18 V - ±10 mA −0.5 VO < −0.5 V or VO > VDD + 0.5 V VDD + 0.5 ±10 - ±10 [1] Unit −25 - V mA mA mA 50 mA Tamb = 125 °C DIP16 package [2] - 750 mW SO16 package [3] - 500 mW - 100 mW per output [1] A destructive high current mode may occur if VI and VO are not constrained to the range VSS ≤ VI or VO ≤ VDD. [2] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [3] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VDD supply voltage Conditions 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air −40 - +125 °C Δt/ΔV input transition rise and fall rate VDD = 5 V - - 3.75 μs/V VDD = 10 V - - 0.5 μs/V VDD = 15 V - - 0.08 μs/V HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 6 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VIH VIL HIGH-level input voltage LOW-level input voltage Conditions see Table 7 VOL LOW-level output voltage |IO| < 1 μA IOL HIGH-level output current LOW-level output current II input leakage current IDD supply current CI input capacitance Tamb = +125 °C Unit Max Min Max Min Max Min Max 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V - - - - - - - - - - 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V VO = 2.5 V 5V −1.7 - −1.4 - −1.1 - −1.1 - mA VO = 4.6 V 5V −0.64 - −0.5 - −0.36 - −0.36 - mA VO = 9.5 V 10 V −1.6 - −1.3 - −0.9 - −0.9 - mA VO = 13.5 V 15 V −4.2 - −3.4 - −2.4 - −2.4 - mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 μA 5V - 5 - 5 - 150 - 150 μA 10 V - 10 - 10 - 300 - 300 μA 15 V - 20 - 20 - 600 - 600 μA - - - - 7.5 - - - - pF IO = 0 A HEF4511B_6 Product data sheet Tamb = +85 °C Min |IO| < 1 μA HIGH-level output voltage Tamb = −40 °C Tamb = +25 °C 5V |IO| < 1 μA VOH IOH VDD © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 7 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver Table 7. Static characteristics for VOH VSS = 0 V. Symbol VOH Parameter HIGH-level output voltage IOH VDD Tamb = −40 °C Tamb = +85 °C Tamb = +125 °C mA V Min Min Typ Min Min 0 5V 4.10 4.10 4.40 4.10 4.10 V 10 V 9.10 9.10 9.90 9.10 9.10 V 15 V 14.10 14.10 14.40 14.10 14.10 V 5V - - 4.30 - - V 10 V - - 9.30 - - V 15 V - - 14.30 - - V 5 10 15 20 25 Tamb = +25 °C Unit 5V 3.60 3.60 4.25 3.30 3.20 V 10 V 8.75 8.75 9.25 8.45 8.35 V 15 V 13.75 13.75 14.30 13.45 13.35 V 5V - - 4.20 - - V 10 V - - 9.20 - - V 15 V - - 14.20 - - V 5V 2.80 2.80 4.20 2.50 2.30 V 10 V 8.10 8.10 9.20 7.80 7.60 V 15 V 13.10 13.10 14.20 12.80 12.60 V 5V - - 4.15 - - V 10 V - - 9.20 - - V 15 V - - 14.20 - - V 11. Dynamic characteristics Table 8. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8. Symbol Parameter Conditions tPHL HIGH to LOW propagation delay Dn → Qn; see Figure 6 LE → Qn; see Figure 6 BL → Qn; see Figure 6 LT → Qn; see Figure 6 Extrapolation formula[1] Min Typ Max Unit 5V 128 ns + (0.55 ns/pF)CL - 155 310 ns 10 V 49 ns + (0.23 ns/pF)CL - 60 120 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns VDD 5V 133 ns + (0.55 ns/pF)CL - 160 320 ns 10 V 49 ns + (0.23 ns/pF)CL - 60 120 ns 15 V 37 ns + (0.16 ns/pF)CL - 45 90 ns 5V 93 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns 15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns 5V 52 ns + (0.55 ns/pF)CL - 80 160 ns 10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns 15 V 12 ns + (0.16 ns/pF)CL - 20 40 ns HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 8 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver Table 8. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 8. Symbol Parameter Conditions tPLH LOW to HIGH propagation delay Dn → Qn; see Figure 6 LE → Qn; see Figure 6 BL → Qn; see Figure 6 LT → Qn; see Figure 6 HIGH to LOW output see Figure 6 transition time tTHL LOW to HIGH output see Figure 6 transition time tTLH set-up time tsu hold time th pulse width tW [1] Extrapolation formula[1] Min Typ Max Unit 5V 108 ns + (0.55 ns/pF)CL - 135 270 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 133 ns + (0.55 ns/pF)CL - 160 320 ns 10 V 59 ns + (0.23 ns/pF)CL - 70 140 ns 15 V 42 ns + (0.16 ns/pF)CL - 50 100 ns 5V 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns VDD Dn → LE; see Figure 7 Dn → LE; see Figure 7 LE input LOW; minimum width; see Figure 7 5V 33 ns + (0.55 ns/pF)CL - 60 120 ns 10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V 20 ns + (1.00 ns/pF)CL - 25 50 ns 10 V 13 ns + (0.06 ns/pF)CL - 16 32 ns 15 V 10 ns + (0.06 ns/pF)CL - 26 ns 13 5V 50 25 - ns 10 V 25 12 - ns 15 V 20 9 - ns 5V 60 30 - ns 10 V 30 15 - ns 15 V 25 12 - ns 5V 80 40 - ns 10 V 40 20 - ns 15 V 35 17 - ns The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 9. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (μW) where: 5V PD = 1000 × fi + Σ(fo × CL) × VDD 2 10 V PD = 4000 × fi + Σ(fo × CL) × VDD 2 15 V PD = 10000 × fi + Σ(fo × CL) × VDD2 fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VDD = supply voltage in V; Σ(fo × CL) = sum of the outputs. HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 9 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 12. Waveforms VI LE VM VM VSS VI VM D2 VSS VI LT VSS tPHL VI VM BL VSS tPLH tPHL VOH tPLH tPHL tPLH tPLH tPHL 90 % VM Qg 10 % VOL tTHL tTLH 001aaj495 Conditions: D3 = LOW and D0 = D1 = HIGH. Measurement points are given in Table 10. Fig 6. Propagation delays and output transition times HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 10 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver VI VM LE input VSS tW VI D2 input VM VSS tsu th VOH Qg output VOL 001aae682 The shaded area indicates where the input is permitted to change for predictable output performance. Conditions: D3 = LOW and D0 = D1 = BL = LT = HIGH. Measurement points are given in Table 10. Fig 7. Waveforms showing minimum LE pulse width, set-up, and hold time for Dn to LE HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 11 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver tW VI 90 % negative pulse VM VM 10 % 0V tf tr tr tf VI 90 % positive pulse VM VM 10 % 0V tW 001aaj781 a. Input waveforms VDD VI VO G DUT RT CL 001aag182 b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 8. Test circuit for measuring switching times Table 10. Measurement points and test data Supply voltage 5 V to 15 V Input Load VI VM tr, tf CL VDD 0.5VI ≤ 20 ns 50 pF HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 12 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 13. Application information • • • • • Driving LED displays Driving incandescent displays Driving fluorescent displays Driving LCD displays Driving gas discharge displays common anode LED VDD VDD ≈ 1.7 V common cathode LED ≈ 1.7 V VSS VSS 001aae683 Fig 9. Connection to common cathode LED display readout 001aae684 Fig 10. Connection to common anode LED display readout VDD VDD VDD direct (low brightness) (1) to filament supply VSS VSS VSS 001aae685 001aae686 (1) A filament pre-warm resistor is recommended to reduce filament thermal shock and increase the effective cold resistance of the filament. Fig 11. Connection to incandescent display readout Fig 12. Connection to fluorescent display readout HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 13 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver VDD appropriate voltage exitation VDD (square wave; VSS to VDD) 1/4 HEF4070B VSS VSS 001aae687 001aae688 Direct DC drive of LCDs not recommended for life of LCD readouts. Fig 13. Connection to gas discharge display readout Fig 14. Connection to LCD readout HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 14 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 15. Package outline SOT38-4 (DIP16) HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 15 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 16. Package outline SOT109-1 (SO16) HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 16 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4511B_6 20091207 Product data sheet - HEF4511B_5 Modifications: • Section 9 “Recommended operating conditions”: Δt/ΔV values updated. HEF4511B_5 20090813 Product data sheet - HEF4511B_4 HEF4511B_4 20090305 Product data sheet - HEF4511B_CNV_3 HEF4511B_CNV_3 19950101 Product specification - HEF4511B_CNV_2 HEF4511B_CNV_2 19950101 Product specification - - HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 17 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4511B_6 Product data sheet © NXP B.V. 2009. All rights reserved. Rev. 06 — 7 December 2009 18 of 19 HEF4511B NXP Semiconductors BCD to 7-segment latch/decoder/driver 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended operating conditions. . . . . . . . 6 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Application information. . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 7 December 2009 Document identifier: HEF4511B_6