HEF4027B Dual JK flip-flop Rev. 05 — 10 November 2008 Product data sheet 1. General description The HEF4027B is a edge-triggered dual JK flip-flop which features independent set-direct (SD), clear-direct (CD), clock (CP) inputs and outputs (Q, Q). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) inputs are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over the full industrial (−40 °C to +85 °C) temperature range. 2. Features n n n n n n Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the full industrial temperature range −40 °C to +85 °C Complies with JEDEC standard JESD 13-B ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V 3. Applications n Registers n Counters n Control circuits 4. Ordering information Table 1. Ordering information Tamb from −40 °C to +85 °C. Type number Package Name Description Version HEF4027BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4 HEF4027BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4027B NXP Semiconductors Dual JK flip-flop 5. Functional diagram FF 1 9 1SD 10 1J 13 1CP 11 1K 1Q 15 1Q 14 2Q 1 2Q 2 1CD 12 FF 2 7 2SD 6 2J 3 2CP 5 2K 2CD 4 001aae593 Fig 1. Functional diagram CP C J Q C C C C C C C Q K C C CD SD 001aae595 Fig 2. Logic diagram of one flip-flop HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 2 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 6. Pinning information 6.1 Pinning HEF4027B 2Q 1 16 VDD 2Q 2 15 1Q 2CP 3 14 1Q 2CD 4 13 1CP 2K 5 12 1CD 2J 6 11 1K 2SD 7 10 1J VSS 8 9 1SD 001aae594 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description VSS 8 ground supply voltage 1SD, 2SD 9, 7 asynchronous set-direct input (active HIGH) 1J, 2J 10, 6 synchronous input 1K, 2K 11, 5 synchronous input 1CD, 2CD 12, 4 asynchronous clear-direct input (active HIGH) 1CP, 2CP 13, 3 clock input (LOW-to-HIGH edge-triggered) 1Q, 2Q 14, 2 complement output 1Q, 2Q 15, 1 true output VDD 16 supply voltage 7. Functional description Table 3. Function table[1] Inputs Outputs nSD nCD nCP nJ nK nQ nQ H L X X X H L L H X X X L H H H X X X H H HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 3 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop Table 3. Function table[1] …continued Inputs Outputs nSD nCD nCP nJ nK nQ nQ L L ↑ L L no change no change L L ↑ H L H L L L ↑ L H L H L L ↑ H H nQ nQ [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.; ↑ = positive-going transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current Conditions Min Max −0.5 VI < 0.5 V or VI > VDD + 0.5 V +18 V ±10 −0.5 VO < 0.5 V or VO > VDD + 0.5 V Unit mA VDD + 0.5 V - ±10 mA - ±10 mA IDD supply current - Tstg storage temperature −65 +150 °C Tamb ambient temperature in free air −40 +85 °C Ptot total power dissipation Tamb −40 °C to +125 °C P power dissipation 50 mA DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Max Unit VDD supply voltage Conditions 3 15 V VI input voltage 0 VDD V Tamb ambient temperature in free air −40 +85 °C ∆t/∆V input transition rise and fall rate VDD = 5 V - 3.75 ns/V VDD = 10 V - 0.5 ns/V VDD = 15 V - 0.08 ns/V HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 4 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol VIH VIL VOH VOL IOH IOL Parameter HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage HIGH-level output current LOW-level output current II input leakage current IDD supply current CI input capacitance Conditions VDD |IO| < 1 µA Tamb = −40 °C Tamb = 85 °C Unit Min Max Min Max Min Max 5V 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 V |IO| < 1 µA |IO| < 1 µA |IO| < 1 µA VO = 2.5 V 5V −1.7 - −1.4 - −1.1 - mA VO = 4.6 V 5V −0.52 - −0.44 - −0.36 - mA VO = 9.5 V 10 V −1.3 - −1.1 - −0.9 - mA VO = 13.5 V 15 V −3.6 - −3.0 - −2.4 - mA VO = 0.4 V 5V 0.52 - 0.44 - 0.36 - mA VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA 15 V - ±0.3 - ±0.3 - ±1.0 µA 5V - 4.0 - 4.0 - 30 µA 10 V - 8.0 - 8.0 - 60 µA 15 V - 16.0 - 16.0 - 120 µA - - - - 7.5 - - pF IO = 0 A HEF4027B_5 Product data sheet Tamb = 25 °C © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 5 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter tPHL HIGH to LOW propagation delay Conditions CP → Q, Q; see Figure 4 CD → Q; see Figure 4 SD → Q; see Figure 4 tPLH LOW to HIGH propagation delay CP → Q, Q; see Figure 4 CD → Q; see Figure 4 SD → Q; see Figure 4 Extrapolation formula[1] VDD tsu th tW transition time set-up time hold time pulse width see Figure 4 J, K → CP; see Figure 5 J, K → CP; see Figure 5 CP LOW; minimum width see Figure 5 SD, CD HIGH; minimum width see Figure 6 trec recovery time SD, CD inputs; see Figure 6 Max Unit 78 ns + (0.55 ns/pF)CL - 105 210 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 93 ns + (0.55 ns/pF)CL - 120 240 ns 10 V 33 ns + (0.23 ns/pF)CL - 45 90 ns 15 V 27 ns + (0.16 ns/pF)CL - 35 70 ns 5V 113 ns + (0.55 ns/pF)CL - 140 280 ns 10 V 44 ns + (0.23 ns/pF)CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF)CL - 40 80 ns 5V 58 ns + (0.55 ns/pF)CL - 85 170 ns 10 V 27 ns + (0.23 ns/pF)CL - 35 70 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 48 ns + (0.55 ns/pF)CL - 75 150 ns 10 V 24 ns + (0.23 ns/pF)CL - 35 70 ns 15 V 17 ns + (0.16 ns/pF)CL - 25 50 ns 5V 43 ns + (0.55 ns/pF)CL - 70 140 ns 10 V 19 ns + (0.23 ns/pF)CL - 30 60 ns 17 ns + (0.16 ns/pF)CL - 25 50 ns 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V [2] 5V 50 25 - ns 10 V 30 10 - ns 15 V 20 5 - ns 5V 25 0 - ns 10 V 20 0 - ns 15 V 15 5 - ns 5V 80 40 - ns 10 V 30 15 - ns 15 V 24 12 - ns 5V 90 45 - ns 10 V 40 20 - ns 15 V 30 15 - ns 5V +20 −15 - ns 10 V +15 −10 - ns 15 V +10 −5 - ns HEF4027B_5 Product data sheet Typ 5V 15 V tt Min © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 6 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol Parameter Conditions fmax CP input; J = K = HIGH; see Figure 5 maximum frequency Extrapolation formula[1] VDD Min Typ Max Unit 5V 4 8 - MHz 10 V 12 25 - MHz 15 V 15 30 - MHz [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). [2] tt is the same as tTLH and tTHL. Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter dynamic power dissipation VDD Typical formula for PD (µW) PD = 900 × fi + Σ(fo × CL) × VDD 5V Where: 2 10 V PD = 4500 × fi + Σ(fo × CL) × VDD2 15 V PD = 13200 × fi + Σ(fo × CL) × VDD fi = input frequency in MHz; fo = output frequency in MHz; 2 CL = output load capacitance in pF; VDD = supply voltage in V; Σ(CL × fo) = sum of the outputs. 12. Waveforms tr VI tf 90 % SD, CD or CP INPUT 0V VM 10 % tPLH VOH tPHL 90 % Q or Q OUTPUT VOL VM 10 % tTLH tTHL 001aah863 VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig 4. Waveforms showing rise, fall and transition times and propagation delays 1/fmax tW CP INPUT VM th J,K INPUT VM tsu 001aae596 Measurement points are given in Table 9. Fig 5. Waveforms showing set-up and hold times and minimum clock pulse width HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 7 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop VI SD INPUT VM 0V tW VI VM CD INPUT 0V tW trec trec VI VM CP INPUT 0V VOH Q OUTPUT VOL 001aae597 VOH and VOL are typical output voltages levels that occur with the output load. Measurement points are given in Table 9. Fig 6. Waveforms showing pulse widths and recovery times Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD VI VO G DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Test circuit Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 8 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 8. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 9 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 10 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 14. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4027B_5 20081110 Product data sheet - HEF4027B_4 Modifications: • • • Maximum Tamb changed to 85 °C and Tamb = 125 °C parameter data removed throughout. Section 1 “General description” temperature range statement modified. Section 10 “Static characteristics” IDD, IOL, IOH and II values revised. HEF4027B_4 20080703 Product specification - HEF4027B_CNV_3 HEF4027B_CNV_3 19950101 Product specification - HEF4027B_CNV_2 HEF4027B_CNV_2 19950101 Product specification - - HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 11 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4027B_5 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 05 — 10 November 2008 12 of 13 HEF4027B NXP Semiconductors Dual JK flip-flop 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Contact information. . . . . . . . . . . . . . . . . . . . . 12 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 November 2008 Document identifier: HEF4027B_5