HEF4021B 8-bit static shift register Rev. 04 — 10 November 2008 Product data sheet 1. General description The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (D0 to D7) and buffered parallel outputs from the last three stages (Q5 to Q7). Each register stage is a D-type master-slave flip-flop with a set direct (SD) and clear direct (CD) input. Information on D0 to D7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW-to-HIGH transition of CP. Schmitt trigger action makes the clock input highly tolerant of slower rise and fall times. It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. It is also suitable for use over both the industrial (−40 °C to +85 °C) and automotive (−40 °C to +125 °C) temperature ranges. 2. Features n n n n n n n Tolerant of slower rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Operates across the automotive temperature range −40 °C to +125 °C Complies with JEDEC standard JESD 13-B ESD protection: u HBM JESD22-A114E exceeds 2000 V u MM JESD22-A115-A exceeds 200 V 3. Applications n Industrial and automotive HEF4021B NXP Semiconductors 8-bit static shift register 4. Ordering information Table 1. Ordering information All types operate from −40 °C to +125 °C. Type number Package Version Name Description HEF4021BP DIP16 plastic dual in-line package; 16-leads (300 mil) SOT38-4 HEF4021BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 2 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 5. Functional diagram 7 6 5 4 13 14 15 1 D0 D1 D2 D3 D4 D5 D6 D7 9 PL SD/CD D 11 DS 10 CP CP SHIFT REGISTER 8-BITS Q5 Q6 Q7 2 12 3 001aae608 Fig 1. Functional diagram D0 D5 SD SD DS O D CP SD O D D7 D6 CP SD O D O D CP CP FF 1 FF 6 FF 7 FF 8 CD CD CD CD PL CP Q5 Q6 Q7 001aae610 Fig 2. Logic diagram HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 3 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 6. Pinning information 6.1 Pinning HEF4021B D7 1 16 VDD Q5 2 15 D6 Q7 3 14 D5 D3 4 13 D4 D2 5 12 Q6 D1 6 11 DS D0 7 10 CP VSS 8 9 PL 001aae609 Fig 3. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description Q5 to Q7 2, 12, 3 buffered parallel output from the last three stages D0 to D7 7, 6, 5, 4, 13, 14,15, 1 parallel data input VSS 8 ground supply voltage PL 9 parallel load input CP 10 clock input (LOW-to-HIGH edge-triggered) DS 11 serial data input VDD 16 supply voltage 7. Functional description Table 3. Function table[1] Number of clock Inputs transitions CP Outputs DS PL Q5 Q6 Q7 Serial operation 1 ↑ data 1 L X X X 2 ↑ data 2 L X X X 3 ↑ data 3 L X X X 6 ↑ X L data 1 X X 7 ↑ X L data 2 data 1 X HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 4 of 14 HEF4021B NXP Semiconductors 8-bit static shift register Table 3. Function table[1] …continued Number of clock Inputs transitions CP 8 Outputs DS PL Q5 Q6 Q7 ↑ X L data 3 data 2 data 1 ↓ X L no change no change no change X X H D5 D6 D7 Parallel operation [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW to HIGH clock transition; ↓ = HIGH to LOW clock transition; data n = data (HIGH or LOW) on the DS input at the nth ↑ CP transition. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current Conditions Min Max −0.5 VI < 0.5 V or VI > VDD + 0.5 V +18 V ±10 −0.5 VO < 0.5 V or VO > VDD + 0.5 V Unit mA VDD + 0.5 V - ±10 mA - ±10 mA IDD supply current - Tstg storage temperature −65 +150 °C Tamb ambient temperature −40 +125 °C Ptot total power dissipation P power dissipation 50 mA Tamb −40 °C to +125 °C DIP16 package [1] - 750 mW SO16 package [2] - 500 mW - 100 mW per output [1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 °C. [2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C. 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Min Typ Max Unit VDD supply voltage Conditions 3 - 15 V VI input voltage 0 - VDD V Tamb ambient temperature in free air −40 - +125 °C ∆t/∆V input transition rise and fall rate VDD = 5 V - - 3.75 ns/V VDD = 10 V - - 0.5 ns/V VDD = 15 V - - 0.08 ns/V HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 5 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions VDD Tamb = −40 °C Min VIH VIL VOH VOL IOH HIGH-level input voltage LOW-level input voltage |IO| < 1 µA |IO| < 1 µA LOW-level output voltage |IO| < 1 µA Tamb = 85 °C Min Min Max Max Tamb = 125 °C Unit Min Max 5V 3.5 - 3.5 - 3.5 - 3.5 - V 10 V 7.0 - 7.0 - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.0 - 3.0 V 15 V - 4.0 - 4.0 - 4.0 - 4.0 V 5V 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V 15 V - 0.05 - 0.05 - 0.05 - 0.05 V |IO| < 1 µA HIGH-level output voltage Max Tamb = 25 °C HIGH-level VO = 2.5 V output current V = 4.6 V O 5V −1.7 - −1.4 - −1.1 - −1.1 - mA 5V −0.64 - −0.5 - −0.36 - −0.36 - mA VO = 9.5 V 10 V −1.6 - −1.3 - −0.9 - −0.9 - mA VO = 13.5 V 15 V −4.2 - −3.4 - −2.4 - −2.4 - mA LOW-level VO = 0.4 V output current V = 0.5 V O 5V 0.64 - 0.5 - 0.36 - 0.36 - mA 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA II input leakage VDD = 15 V current 15 V - ±0.1 - ±0.1 - ±1.0 - ±1.0 µA IDD supply current 5V - 5 - 5 - 150 - 150 µA 10 V - 10 - 10 - 300 - 300 µA 15 V - 20 - 20 - 600 - 600 µA - - - - 7.5 - - - - pF IOL CI IO = 0 A input capacitance 11. Dynamic characteristics Table 7. Dynamic characteristics VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol tPHL Parameter HIGH to LOW propagation delay Conditions CP to Qn see Figure 4 PL to Qn see Figure 4 VDD Extrapolation formula Min Typ Max Unit 98 ns + (0.55 ns/pF) CL - 125 250 ns 10 V 44 ns + (0.23 ns/pF) CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns 5V 93 ns + (0.55 ns/pF) CL - 120 240 ns 10 V 44 ns + (0.23 ns/pF) CL - 55 110 ns 15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns 5V [1] HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 6 of 14 HEF4021B NXP Semiconductors 8-bit static shift register Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 °C; for test circuit see Figure 7; unless otherwise specified. Symbol tPLH Parameter LOW to HIGH propagation delay Conditions VDD CP to Qn see Figure 4 Extrapolation formula Min Typ Max Unit 88 ns + (0.55 ns/pF) CL - 115 230 ns 39 ns + (0.23 ns/pF) CL - 50 100 ns 15 V 32 ns + (0.16 ns/pF) CL - 40 80 ns 5V 78 ns + (0.55 ns/pF) CL - 105 210 ns 10 V 39 ns + (0.23 ns/pF) CL - 50 100 ns 32 ns + (0.16 ns/pF) CL - 40 80 ns 5V [1] 10 V PL to Qn see Figure 4 15 V transition time tt set-up time tsu Qn; see Figure 4 DS to CP; see Figure 5 Dn to PL; see Figure 6 hold time th DS to CP; see Figure 5 Dn to PL; see Figure 6 pulse width tW CP = LOW; minimum width; see Figure 5 PL = HIGH; minimum width; see Figure 6 recovery time trec fclk(max) [1] maximum clock frequency PL input; see Figure 6 CP input; see Figure 5 5V [1] 10 ns + (1.00 ns/pF) CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF) CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF) CL - 20 40 ns 5V +25 −15 - ns 10 V +25 −10 - ns 15 V +15 −5 - ns 5V 50 25 - ns 10 V 30 10 - ns 15 V 20 5 - ns 5V 40 20 - ns 10 V 20 10 - ns 15 V 15 8 - ns 5V +15 −10 - ns 10 V 15 0 - ns 15 V 15 0 - ns 5V 70 35 - ns 10 V 30 15 - ns 15 V 24 12 - ns 5V 70 35 - ns 10 V 30 15 - ns 15 V 24 12 - ns 5V 50 10 - ns 10 V 40 5 - ns 15 V 35 5 - ns 5V 6 13 - MHz 10 V 15 30 - MHz 15 V 20 40 - MHz The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 7 of 14 HEF4021B NXP Semiconductors 8-bit static shift register Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf ≤ 20 ns; Tamb = 25 °C. Symbol PD Parameter VDD dynamic power dissipation 5V Typical formula for PD (µW) PD = 900 × fi + Σ(fo × CL) × VDD where: 2 fi = input frequency in MHz, 10 V PD = 4300 × fi + Σ(fo × CL) × VDD2 15 V PD = 12000 × fi + Σ(fo × CL) × VDD fo = output frequency in MHz, 2 CL = output load capacitance in pF, VDD = supply voltage in V, Σ(CL × fo) = sum of the outputs. 12. Waveforms VDD CP or PL INPUT VM VSS tPHL VOH tPLH VY Qn OUTPUT VM VX VOL tt Fig 4. tt 001aaj060 Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times 1 / fclk(max) VDD CP INPUT VM VSS tsu th tW VDD DS INPUT VM VSS 001aae611 Fig 5. Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS. HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 8 of 14 HEF4021B NXP Semiconductors 8-bit static shift register VDD CP INPUT VM VSS tW trec VDD PL INPUT VM VSS tsu VDD th 90 % Dn INPUT VM 10 % VSS tf tr 001aae612 Set-up times and hold times are shown as positive values but may be specified as negative values; Measurement points are given in Table 9. Fig 6. Waveforms showing minimum pulse width and recovery time for PL; set-up and hold times for Dn to PL. Table 9. Measurement points Supply voltage Input Output VDD VM VM VX VY 5 V to 15 V 0.5VDD 0.5VDD 0.1VDD 0.9VDD VDD VI VO G DUT CL RT 001aag182 Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 7. Test circuit Table 10. Test data Supply voltage Input Load VDD VI tr, tf CL 5 V to 15 V VSS or VDD ≤ 20 ns 50 pF HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 9 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 13. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.38 1.25 0.85 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.60 3.05 8.25 7.80 10.0 8.3 0.254 0.76 inches 0.17 0.02 0.13 0.068 0.051 0.021 0.015 0.049 0.033 0.014 0.009 0.77 0.73 0.26 0.24 0.1 0.3 0.14 0.12 0.32 0.31 0.39 0.33 0.01 0.03 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 95-01-14 03-02-13 SOT38-4 Fig 8. EUROPEAN PROJECTION Package outline SOT38-4 (DIP16) HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 10 of 14 HEF4021B NXP Semiconductors 8-bit static shift register SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. Fig 9. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Package outline SOT109-1 (SO16) HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 11 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 14. Abbreviations Table 11. Abbreviations Acronym Description DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4021B_4 20081110 Product data sheet - HEF4021B_CNV_3 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • • • Legal texts have been adapted to the new company name where appropriate. • • Section 2 “Features” added. Pins renamed throughout, see Figure 3 “Pin configuration” and Table 2 “Pin description”. Maximum temperature increased throughout and 125 °C data added to Table 6 “Static characteristics”. Package version SOT38-1 changed to SOT38-4 in Section 4, and Figure 8. Package SOT74 removed from Section 4. • • Table 1 “Ordering information” restructured. • • • • • • IDD, IOL, IOH and II values updated in Section 10 “Static characteristics”. Section 8 “Limiting values” and Section 10 “Static characteristics” added, taken from the HE4000B Family Specifications data sheet. Section 9 “Recommended operating conditions” added. Figure references added to table Table 7 “Dynamic characteristics”. thold, tWCPL, tWPLH and tRPL changed to th, tW and trec for Table 7, Figure 5 and Figure 6. 50 % changed to VM for Figure 5 and 6. Table 9 “Measurement points”, Figure 7 “Test circuit” and Table 10 “Test data” added. HEF4021B_CNV_3 19950101 Product specification - HEF4021B_CNV_2 HEF4021B_CNV_2 19950101 Product specification - - HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 12 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 16.3 Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4021B_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev. 04 — 10 November 2008 13 of 14 HEF4021B NXP Semiconductors 8-bit static shift register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 4 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 10 November 2008 Document identifier: HEF4021B_4