FAIRCHILD 74F573SJ

Revised August 1999
74F573
Octal D-Type Latch with 3-STATE Outputs
General Description
Features
The 74F573 is a high speed octal latch with buffered common Latch Enable (LE) and buffered common Output
Enable (OE) inputs.
■ Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
This device is functionally identical to the 74F373 but has
different pinouts.
■ Functionally identical to 74F373
■ Useful as input or output port for microprocessors
■ 3-STATE outputs for bus interfacing
■ Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number
Package Number
Package Description
74F573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74F573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74F573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
© 1999 Fairchild Semiconductor Corporation
DS009566
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74F573 Octal D-Type Latch with 3-STATE Outputs
April 1988
74F573
Unit Loading/Fan Out
Pin Names
Description
U.L.
Input IIH/IIL
HIGH/LOW
Output IOH/IOL
D0–D7
Data Inputs
1.0/1.0
20 µA/−0.6 mA
LE
Latch Enable Input (Active HIGH)
1.0/1.0
20 µA/−0.6 mA
OE
3-STATE Output Enable Input (Active LOW)
O0–O7
3-STATE Latch Outputs
1.0/1.0
20 µA/−0.6 mA
150/40(33.3)
−3 mA/24 mA (20 mA)
Function Table
Functional Description
The 74F573 contains eight D-type latches with 3-state output buffers. When the Latch Enable (LE) input is HIGH,
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-state buffers are controlled by the Output
Enable (OE) input. When OE is LOW, the buffers are in the
bi-state mode. When OE is HIGH the buffers are in the high
impedance mode but this does not interfere with entering
new data into the latches.
Inputs
Outputs
OE
LE
D
O
L
H
H
H
L
H
L
L
L
L
X
O0
H
X
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
O0 = Value stored from previous clock cycle
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Recommended Operating
Conditions
Storage Temperature
−65°C to +150°C
Ambient Temperature under Bias
−55°C to +125°C
Free Air Ambient Temperature
Junction Temperature under Bias
−55°C to +150°C
Supply Voltage
0°C to +70°C
+4.5V to +5.5V
−0.5V to +7.0V
VCC Pin Potential to Ground Pin
Input Voltage (Note 2)
−0.5V to +7.0V
Input Current (Note 2)
−30 mA to +5.0 mA
Voltage Applied to Output
in HIGH State (with VCC = 0V)
Standard Output
−0.5V to VCC
3-STATE Output
−0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
in LOW State (Max)
ESD Last Passing Voltage (Min)
4000V
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
VCC
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
Min
VOH
Output HIGH
10% VCC
2.5
Voltage
10% VCC
2.4
5% VCC
2.7
V
Min
5% VCC
2.7
VOL
Output LOW
Voltage
IIH
IBVI
2.0
Units
VIH
V
IOD
IOL = 24 mA
µA
Max
VIN = 2.7V
7.0
µA
Max
VIN = 7.0V
50
µA
Max
VOUT = VCC
V
0.0
3.75
µA
0.0
−0.6
mA
Max
VIN = 0.5V
50
µA
Max
VOUT = 2.7V
20.0
5.0
Input HIGH Current
Output HIGH
4.75
Output Leakage
Circuit Current
IIL
Input LOW Current
IOZH
Output Leakage Current
IOZL
Output Leakage Current
IOS
Output Short-Circuit Current
IZZ
Bus Drainage Test
ICCL
Power Supply Current
ICCZ
Power Supply Current
IOH = −1 mA
Min
Current
Test
IOH = −3 mA
V
0.5
10% VCC
Input HIGH
Input Leakage
IIN = −18 mA
IOH = −3 mA
Leakage Current
VID
Recognized as a LOW Signal
IOH = −1 mA
Breakdown Test
ICEX
Conditions
Recognized as a HIGH Signal
IID = 1.9 µA
All Other Pins Grounded
VIOD = 150 mV
All Other Pins Grounded
−50
µA
Max
VOUT = 0.5V
−150
mA
Max
VOUT = 0V
500
µA
0.0V
VOUT = 5.25V
35
55
mA
Max
VO = LOW
35
55
mA
Max
VO = HIGH Z
−60
3
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74F573
Absolute Maximum Ratings(Note 1)
74F573
AC Electrical Characteristics
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
TA = 0°C to +70°C
VCC = +5.0V
VCC = +5.0V
VCC = +5.0V
CL = 50 pF
CL = 50 pF
CL = 50 pF
Min
Typ
Max
Min
Max
Min
Max
tPLH
Propagation Delay
3.0
5.3
7.0
3.0
9.0
3.0
8.0
tPHL
Dn to On
2.0
3.7
6.0
2.0
7.0
2.0
6.5
tPLH
Propagation Delay
5.0
9.0
11.0
5.0
13.5
5.0
12.0
tPHL
LE to On
3.0
5.2
7.0
3.0
7.5
3.0
7.0
tPZH
Output Enable Time
2.0
5.0
8.0
2.0
10.0
2.0
9.0
2.0
5.6
8.5
2.0
10.0
2.0
9.5
1.5
4.5
5.5
1.5
7.0
1.5
6.5
1.5
3.8
5.5
1.5
5.5
1.5
5.5
tPZL
tPHZ
Output Disable Time
tPLZ
Units
ns
ns
ns
AC Operating Requirements
Symbol
Parameter
TA = +25°C
TA = −55°C to +125°C
VCC = +5.0V
VCC = +5.0V
Min
Max
Min
Max
TA = 0°C to +70°C
VCC = +5.0V
Min
tS(H)
Setup Time, HIGH or LOW
2.0
2.0
2.0
tS(L)
Dn to LE
2.0
2.0
2.0
tH(H)
Hold Time, HIGH or LOW
3.0
3.0
3.0
tH(L)
Dn to LE
3.5
4.0
3.5
tW(H)
LE Pulse Width, HIGH
4.0
4.0
4.0
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Units
Max
ns
ns
74F573
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
Package Number M20B
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
5
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74F573 Octal D-Type Latch with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
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user.
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