Revised July 1999 74F843 9-Bit Transparent Latch General Description Features The 74F843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. ■ 3-STATE output Ordering Code: Order Number Package Number Package Description 74F843SC M24B 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 74F843SPC N24C 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE © 1999 Fairchild Semiconductor Corporation DS009453 www.fairchildsemi.com 74F843 9-Bit Transparent Latch January 1988 74F843 Unit Loading/Fan Out Input IIH/IIL U.L. Pin Names Description HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA D0–D8 Data Inputs 1.0/1.0 OE Output Enable Input 1.0/1.0 20 µA/−0.6 mA LE Latch Enable 1.0/1.0 20 µA/−0.6 mA CLR Clear 1.0/1.0 20 µA/−0.6 mA PRE Preset 1.0/1.0 20 µA/−0.6 mA O0–O8 3-STATE Data Outputs 150/40 −3 mA/24 mA Function Table Functional Description The 74F843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the 74F843 has a Clear (CLR) pin and a Preset (PRE). These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the Outputs are HIGH if OE is LOW. Preset overrides CLR. Inputs Internal Output Function CLR PRE OE LE D Q O H H X X X X Z High Z H H H H L L Z High Z H H H H H H Z High Z H H H L X NC Z Latched H H L H L L L Transparent H H L H H H H Transparent H H L L X NC NC Latched H L L X X H H Preset L H L X X L L Clear L L L X X H H Preset L H H L X L Z Latched H L H L X H Z Latched H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.fairchildsemi.com 2 Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage VCC Pin Potential to Ground Pin −0.5V to +7.0V Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA 0°C to +70°C +4.5V to +5.5V Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. Current Applied to Output in LOW State (Max) twice the rated IOL (mA) DC Electrical Characteristics Symbol Parameter Min Typ Max VCC Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min VOH Output HIGH 10% VCC 2.5 Voltage 10% VCC 2.4 V Min 5% VCC 2.7 5% VCC 2.7 V Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = −18 mA IOH = −1 mA IOH = −3 mA IOH = −1 mA IOH = −3 mA 0.5 V Min IOL = 24 mA Input HIGH Current 5.0 µA Max VIN = 2.7V Input HIGH Current 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 IID = 1.9 µA 3.75 µA 0.0 VIOD = 150 mV −0.6 mA Max VIN = 0.5V 50 µA Max VOUT = 2.7V −50 µA Max VOUT = 0.5V −150 mA Max VOUT = 0V 500 µA 0.0V VOUT = 5.25V 90 mA Max VOL Output LOW Voltage IIH IBVI 2.0 Units VIH 10% VCC Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage 4.75 Test IOD All other pins grounded Output Leakage Circuit Current IIL Input LOW Current IOZH Output Leakage Current IOZL Output Leakage Current IOS Output Short-Circuit Current IZZ Bus Drainage Test ICC Power Supply Current All other pins grounded −60 65 3 www.fairchildsemi.com 74F843 Absolute Maximum Ratings(Note 1) 74F843 AC Electrical Characteristics Symbol Parameter TA = +25°C TA = 0°C to +70°C VCC = +5.0V VCC = +5.0V CL = 50 pF CL = 50 pF Units Min Typ Max Min Max tPLH Propagation Delay 2.5 5.4 8.0 2.0 9.0 tPHL Dn to On 1.5 4.2 6.5 1.5 7.0 tPLH Propagation Delay 5.0 8.5 12.0 4.5 13.5 tPHL LE to On 2.0 4.7 7.5 2.0 8.0 tPLH Propagation Delay 3.0 7.3 10.0 2.5 11.0 ns ns PRE to On tPHL Propagation Delay 3.0 6.9 10.0 2.5 11.0 tPZH Output Enable Time 2.5 5.0 8.5 2.0 9.5 tPZL OE to On 2.5 6.1 9.0 2.0 10.0 tPHZ Output Disable Time 1.0 3.6 6.5 1.0 7.5 tPLZ OE to On 1.0 3.4 6.5 1.0 7.5 CLR to On ns ns ns ns AC Operating Requirements TA = +25°C Symbol VCC = +5.0V Parameter Min Max TA = 0°C to +70°C VCC = +5.0V Min Units Max tS(H) Setup Time, HIGH or LOW 2.0 2.5 tS(L) Dn to LE 2.0 2.5 tH(H) Hold Time, HIGH or LOW 2.5 3.0 tH(L) Dn to LE 3.0 3.5 tW(H) LE Pulse Width, HIGH 4.0 4.0 ns tW(L) PRE Pulse Width, LOW 5.0 5.0 ns tW(L) CLR Pulse Width, LOW 5.0 5.0 ns tREC PRE Recovery Time 10.0 10.0 ns tREC CLR Recovery Time 12.0 13.0 ns www.fairchildsemi.com 4 ns 74F843 Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide) Package Number M24B 5 www.fairchildsemi.com 74F843 9-Bit Transparent Latch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-100, 0.300 Wide Package Number N24C Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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