PD - 96199A
IRF1324PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
D
G
S
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
24V
1.2m:
1.5m:
353A
ID (Package Limited)
195A
c
S
D
G
TO-220AB
IRF1324PbF
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25°C
ID @ TC = 100°C
ID @ TC = 25°C
IDM
PD @TC = 25°C
VGS
Parameter
Max.
353
249
195
1412
300
2.0
± 20
0.46
d
Pulsed Drain Current
Maximum Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
(1.6mm from case)
f
dv/dt
TJ
TSTG
Avalanche Characteristics
EAS (Thermally limited)
IAR
EAR
Single Pulse Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
d
Thermal Resistance
Symbol
RθJC
RθCS
RθJA
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e
g
Parameter
j
Junction-to-Case
Case-to-Sink, Flat Greased Surface
Junction-to-Ambient
j
Units
c
c
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Silicon Limited)
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
A
W
W/°C
V
V/ns
-55 to + 175
°C
300
270
See Fig. 14, 15, 22a, 22b
mJ
A
mJ
Typ.
Max.
Units
–––
0.50
–––
0.50
–––
62
°C/W
1
09/24/09
IRF1324PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
V(BR)DSS
∆V(BR)DSS/∆TJ
RDS(on)
VGS(th)
IDSS
IGSS
RG
Parameter
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
Min. Typ. Max. Units
24
–––
–––
2.0
–––
–––
–––
–––
–––
–––
22
1.2
–––
–––
–––
–––
–––
2.3
Conditions
–––
V VGS = 0V, ID = 250µA
––– mV/°C Reference to 25°C, ID = 5.0mA
1.5
mΩ VGS = 10V, ID = 195A
4.0
V VDS = VGS, ID = 250µA
20
µA VDS = 24V, VGS = 0V
VDS = 24V, VGS = 0V, TJ = 125°C
250
200
nA VGS = 20V
VGS = -20V
-200
–––
Ω
d
g
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Conditions
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
180
–––
–––
–––
–––
Turn-On Delay Time
–––
Rise Time
–––
Turn-Off Delay Time
–––
Fall Time
–––
Input Capacitance
–––
Output Capacitance
–––
Reverse Transfer Capacitance
–––
Effective Output Capacitance (Energy Related) –––
Effective Output Capacitance (Time Related)
–––
–––
160
84
49
76
17
190
83
120
7590
3440
1960
4700
4490
–––
240
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
VDS = 10V, ID = 195A
ID = 195A
VDS = 12V
VGS = 10V
ID = 195A, VDS =0V, VGS = 10V
VDD = 16V
ID = 195A
RG = 2.7Ω
VGS = 10V
VGS = 0V
VDS = 24V
g
g
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 19V
VGS = 0V, VDS = 0V to 19V
Diode Characteristics
Symbol
IS
Parameter
VSD
trr
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode)
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
ISM
d
Notes:
Calcuted continuous current based on maximum allowable junction
temperature Bond wire current limit is 195A. Note that current
limitation arising from heating of the device leds may occur with
some lead mounting arrangements.
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.014mH
RG = 25Ω, IAS = 195A, VGS =10V. Part not recommended for use
above this value .
ISD ≤ 195A, di/dt ≤ 450 A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
2
Conditions
Min. Typ. Max. Units
c
–––
–––
353
–––
–––
1412
A
i, See Fig. 11
h
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 195A, VGS = 0V
TJ = 25°C
VR = 20V,
IF = 195A
TJ = 125°C
TJ = 25°C
di/dt = 100A/µs
TJ = 125°C
TJ = 25°C
D
g
S
––– –––
1.3
V
–––
46
–––
ns
–––
71
–––
––– 160 –––
nC
––– 430 –––
–––
7.7
–––
A
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
g
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS .
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
Rθ is measured at TJ approximately 90°C
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IRF1324PbF
10000
≤60µs PULSE WIDTH
Tj = 25°C
1000
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
TOP
100
BOTTOM
≤60µs PULSE WIDTH
Tj = 175°C
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
10000
TOP
1000
10
BOTTOM
VGS
15V
10V
8.0V
6.0V
5.5V
5.0V
4.5V
4.0V
100
1
4.0V
4.0V
10
0.1
0.1
1
10
0.1
100
Fig 1. Typical Output Characteristics
100
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID, Drain-to-Source Current (A)
10
Fig 2. Typical Output Characteristics
1000
100
T J = 175°C
T J = 25°C
10
1
VDS = 15V
≤60µs PULSE WIDTH
0.1
ID = 195A
VGS = 10V
1.5
1.0
0.5
2
3
4
5
6
7
8
9
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Junction Temperature (°C)
VGS, Gate-to-Source Voltage (V)
Fig 4. Normalized On-Resistance vs. Temperature
Fig 3. Typical Transfer Characteristics
100000
14.0
VGS = 0V,
f = 1 MHZ
C iss = C gs + C gd, C ds SHORTED
C rss = C gd
VGS, Gate-to-Source Voltage (V)
ID= 195A
C oss = C ds + C gd
C, Capacitance (pF)
1
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Ciss
Coss
10000
Crss
12.0
VDS= 19V
VDS= 12V
10.0
8.0
6.0
4.0
2.0
0.0
1000
1
10
100
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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0
50
100
150
200
QG, Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRF1324PbF
10000
ID, Drain-to-Source Current (A)
ISD, Reverse Drain Current (A)
1000
TJ = 175°C
100
T J = 25°C
10
OPERATION IN THIS AREA
LIMITED BY R DS(on)
1000
100µsec
1msec
100
Limited by
package
10msec
10
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.0
0.5
1.0
1
1.5
Fig 7. Typical Source-Drain Diode
Forward Voltage
300
250
200
150
100
50
0
50
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage (V)
ID, Drain Current (A)
Limited By Package
25
32
Id = 5mA
30
28
26
24
-60 -40 -20 0 20 40 60 80 100120140160180
T J , Temperature ( °C )
T C , Case Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
2.0
EAS , Single Pulse Avalanche Energy (mJ)
1200
1.8
ID
44A
83A
BOTTOM 195A
TOP
1000
1.6
1.4
1.2
Energy (µJ)
100
Fig 8. Maximum Safe Operating Area
400
350
10
VDS, Drain-to-Source Voltage (V)
VSD, Source-to-Drain Voltage (V)
1.0
0.8
0.6
0.4
0.2
0.0
800
600
400
200
0
-5
0
5
10
15
20
25
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
DC
1
1.0
30
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
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IRF1324PbF
Thermal Response ( Z thJC ) °C/W
1
D = 0.50
0.20
0.1
0.10
0.05
τJ
0.02
0.01
0.01
R1
R1
τJ
τ1
R2
R2
R3
R3
τC
τ
τ1
τ2
τ2
τ3
τ3
τ4
τ4
Ci= τi/Ri
Ci i/Ri
1E-005
0.0125
0.000008
0.0822
0.000078
0.2019
0.001110
0.2036
0.007197
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
SINGLE PULSE
( THERMAL RESPONSE )
0.001
1E-006
τi (sec)
Ri (°C/W)
R4
R4
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Avalanche Current (A)
Duty Cycle = Single Pulse
0.01
100
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ∆Τ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
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5
IRF1324PbF
EAR , Avalanche Energy (mJ)
300
TOP
Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 195A
250
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
200
150
100
50
0
25
50
75
100
125
150
175
Starting T J , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
VGS(th) , Gate threshold Voltage (V)
4.5
4.0
3.5
3.0
2.5
2.0
ID = 250µA
ID = 1.0mA
ID = 1.0A
1.5
1.0
-75 -50 -25 0
25 50 75 100 125 150 175 200
T J , Temperature ( °C )
Fig 16. Threshold Voltage vs. Temperature
6
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IRF1324PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
I SD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
VGS
20V
+
V
- DD
IAS
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2µF
.3µF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRF1324PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
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TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 09/2009
8
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