PD -97143
IRFB3006PbF
HEXFET® Power MOSFET
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
G
D
Benefits
l Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
l Fully Characterized Capacitance and Avalanche
SOA
l Enhanced body diode dV/dt and dI/dt Capability
l Lead-Free
S
VDSS
RDS(on) typ.
max.
ID (Silicon Limited)
60V
2.1m:
2.5m:
270A c
ID (Package Limited)
195A
D
G
D
S
TO-220AB
G
D
S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
Parameter
Max.
Units
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
270c
ID @ TC = 100°C
Continuous Drain Current, VGS @ 10V (Silicon Limited)
190 c
ID @ TC = 25°C
Continuous Drain Current, VGS @ 10V (Wire Bond Limited)
195
IDM
Pulsed Drain Current d
1080
PD @TC = 25°C
Maximum Power Dissipation
375
W
Linear Derating Factor
2.5
VGS
Gate-to-Source Voltage
± 20
W/°C
V
dv/dt
TJ
Peak Diode Recovery f
10
V/ns
Operating Junction and
-55 to + 175
TSTG
Storage Temperature Range
A
°C
300
Soldering Temperature, for 10 seconds
(1.6mm from case)
10lbxin (1.1Nxm)
Mounting torque, 6-32 or M3 screw
Avalanche Characteristics
EAS (Thermally limited)
Single Pulse Avalanche Energy e
IAR
Avalanche Currentd
EAR
Repetitive Avalanche Energy g
320
mJ
See Fig. 14, 15, 22a, 22b,
A
mJ
Thermal Resistance
Typ.
Max.
RθJC
Symbol
Junction-to-Case k
–––
0.4
RθCS
Case-to-Sink, Flat Greased Surface
0.50
–––
RθJA
Junction-to-Ambient jk
–––
62
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Parameter
Units
°C/W
1
10/6/08
IRFB3006PbF
Static @ TJ = 25°C (unless otherwise specified)
Symbol
Parameter
V(BR)DSS
ΔV(BR)DSS/ΔTJ
RDS(on)
VGS(th)
IDSS
Drain-to-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Static Drain-to-Source On-Resistance
Gate Threshold Voltage
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Internal Gate Resistance
RG
Min. Typ. Max. Units
60
–––
–––
2.0
–––
–––
–––
–––
–––
–––
0.07
2.1
–––
–––
–––
–––
–––
2.0
–––
–––
2.5
4.0
20
250
100
-100
–––
Conditions
V VGS = 0V, ID = 250μA
V/°C Reference to 25°C, ID = 5mAd
mΩ VGS = 10V, ID = 170A g
V VDS = VGS, ID = 250μA
μA VDS = 60V, VGS = 0V
VDS = 60V, VGS = 0V, TJ = 125°C
nA VGS = 20V
VGS = -20V
Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol
gfs
Qg
Qgs
Qgd
Qsync
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss eff. (ER)
Coss eff. (TR)
Parameter
Min. Typ. Max. Units
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Total Gate Charge Sync. (Qg - Qgd)
280
–––
–––
–––
–––
Turn-On Delay Time
–––
Rise Time
–––
Turn-Off Delay Time
–––
Fall Time
–––
Input Capacitance
–––
Output Capacitance
–––
Reverse Transfer Capacitance
–––
Effective Output Capacitance (Energy Related) –––
Effective Output Capacitance (Time Related)h –––
–––
200
37
60
140
16
182
118
189
8970
1020
534
1480
1920
–––
300
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
S
nC
ns
pF
Conditions
VDS = 25V, ID = 170A
ID = 170A
VDS =30V
VGS = 10V g
ID = 170A, VDS =0V, VGS = 10V
VDD = 39V
ID = 170A
RG = 2.7Ω
VGS = 10V g
VGS = 0V
VDS = 50V
ƒ = 1.0 MHz, See Fig. 5
VGS = 0V, VDS = 0V to 48V i, See Fig. 11
VGS = 0V, VDS = 0V to 48V h
Diode Characteristics
Symbol
Parameter
IS
Continuous Source Current
ISM
(Body Diode)
Pulsed Source Current
VSD
trr
(Body Diode)d
Diode Forward Voltage
Reverse Recovery Time
Qrr
Reverse Recovery Charge
IRRM
ton
Reverse Recovery Current
Forward Turn-On Time
Min. Typ. Max. Units
–––
–––
–––
1080
Conditions
A
MOSFET symbol
A
showing the
integral reverse
D
G
p-n junction diode.
TJ = 25°C, IS = 170A, VGS = 0V g
TJ = 25°C
VR = 51V,
IF = 170A
TJ = 125°C
di/dt = 100A/μs g
TJ = 25°C
––– –––
1.3
V
–––
44
–––
ns
–––
48
–––
–––
63
–––
nC
TJ = 125°C
–––
77
–––
–––
2.4
–––
A TJ = 25°C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Bond wire current limit is 195A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements. (Refer to AN-1140)
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.022mH
RG = 25Ω, IAS = 170A, VGS =10V. Part not recommended for use
above this value .
2
––– 270c
S
ISD ≤ 170A, di/dt ≤ 1360A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400μs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C.
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IRFB3006PbF
1000
1000
100
BOTTOM
TOP
ID, Drain-to-Source Current (A)
ID, Drain-to-Source Current (A)
TOP
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
10
3.5V
≤ 60μs PULSE WIDTH
Tj = 25°C
1
10
100
3.5V
≤ 60μs PULSE WIDTH
Tj = 175°C
10
1
0.1
BOTTOM
0.1
100
Fig 1. Typical Output Characteristics
10
100
Fig 2. Typical Output Characteristics
2.5
RDS(on) , Drain-to-Source On Resistance
1000
TJ = 175°C
100
(Normalized)
ID, Drain-to-Source Current(Α)
1
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
TJ = 25°C
10
VDS = 25V
≤ 60μs PULSE WIDTH
1
2.0
3.0
4.0
5.0
6.0
ID = 170A
VGS = 10V
2.0
1.5
1.0
0.5
7.0
-60 -40 -20
VGS, Gate-to-Source Voltage (V)
16000
Ciss
8000
Coss
Crss
10
100
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
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ID= 170A
VDS = 48V
VDS = 30V
12
8
4
0
0
1
Fig 4. Normalized On-Resistance vs. Temperature
VGS, Gate-to-Source Voltage (V)
Coss = Cds + Cgd
4000
20 40 60 80 100 120 140 160 180
16
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
12000
0
TJ , Junction Temperature (°C)
Fig 3. Typical Transfer Characteristics
C, Capacitance (pF)
VGS
15V
10V
8.0V
6.0V
5.0V
4.5V
4.0V
3.5V
0
40
80
120
160
200
240
280
QG Total Gate Charge (nC)
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
3
IRFB3006PbF
10000
TJ = 175°C
ID, Drain-to-Source Current (A)
ISD , Reverse Drain Current (A)
1000
100
10
TJ = 25°C
1
OPERATION IN THIS AREA
LIMITED BY R DS (on)
1000
100μsec
100
LIMITED BY PACKAGE
10
10msec
1
Tc = 25°C
Tj = 175°C
Single Pulse
VGS = 0V
0.0
0.4
0.8
1.2
1.6
0.1
2.0
LIMITED BY PACKAGE
ID , Drain Current (A)
250
200
150
100
50
0
75
100
125
150
175
V(BR)DSS , Drain-to-Source Breakdown Voltage
300
50
10
100
Fig 8. Maximum Safe Operating Area
Fig 7. Typical Source-Drain Diode
Forward Voltage
25
1
VDS , Drain-toSource Voltage (V)
VSD , Source-to-Drain Voltage (V)
80
ID = 5mA
75
70
65
60
55
-60 -40 -20
TC , Case Temperature (°C)
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 10. Drain-to-Source Breakdown Voltage
1400
EAS, Single Pulse Avalanche Energy (mJ)
2.0
1.5
Energy (μJ)
DC
0.1
0.1
1.0
0.5
0.0
ID
20A
27A
BOTTOM 170A
1200
TOP
1000
800
600
400
200
0
0
10
20
30
40
50
VDS, Drain-to-Source Voltage (V)
Fig 11. Typical COSS Stored Energy
4
1msec
60
25
50
75
100
125
150
175
Starting TJ, Junction Temperature (°C)
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
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IRFB3006PbF
Thermal Response ( Z thJC )
1
D = 0.50
0.1
0.20
0.10
0.05
0.01
0.02
0.01
τJ
R1
R1
τJ
τ1
R2
R2
τC
τ1
τ2
τ2
SINGLE PULSE
( THERMAL RESPONSE )
τι (sec)
0.175365 0.000343
0.22547
Ci= τi/Ri
0.001
Ri (°C/W)
0.006073
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
0.0001
1E-006
1E-005
0.0001
0.001
0.01
0.1
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1000
Avalanche Current (A)
Duty Cycle = Single Pulse
100
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔTj = 150°C and
Tstart =25°C (Single Pulse)
0.01
0.05
0.10
10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming ΔΤ j = 25°C and
Tstart = 150°C.
1
1.0E-06
1.0E-05
1.0E-04
1.0E-03
1.0E-02
1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
EAR , Avalanche Energy (mJ)
400
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ΔT = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
TOP
Single Pulse
BOTTOM 1% Duty Cycle
ID = 170A
300
200
100
0
25
50
75
100
125
150
175
Starting TJ , Junction Temperature (°C)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB3006PbF
20
ID = 1.0A
ID = 1.0mA
3.5
16
ID = 250μA
3.0
IRRM - (A)
VGS(th) Gate threshold Voltage (V)
4.0
2.5
12
8
2.0
IF = 112A
VR = 51V
4
1.5
TJ = 125°C
TJ = 25°C
0
1.0
-75
-50
-25
0
25
50
75
100
100 125 150 175
200
300
400
500
600
700
800
dif / dt - (A / μs)
TJ , Temperature ( °C )
Fig 16. Threshold Voltage Vs. Temperature
Fig. 17 - Typical Recovery Current vs. dif/dt
20
700
600
16
12
QRR - (nC)
IRRM - (A)
500
8
4
0
400
300
IF = 170A
VR = 51V
200
IF = 112A
VR = 51V
TJ = 125°C
TJ = 25°C
100
TJ = 125°C
TJ = 25°C
0
100
200
300
400
500
600
700
800
100
dif / dt - (A / μs)
200
300
400
500
600
700
800
dif / dt - (A / μs)
Fig. 18 - Typical Recovery Current vs. dif/dt
Fig. 19 - Typical Stored Charge vs. dif/dt
700
600
QRR - (nC)
500
400
300
200
IF = 170A
VR = 51V
100
TJ = 125°C
TJ = 25°C
0
100
200
300
400
500
600
700
800
dif / dt - (A / μs)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB3006PbF
Driver Gate Drive
D.U.T
-
-
-
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
+
RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
VDD
P.W.
Period
VGS=10V
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D=
Period
P.W.
+
+
-
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor
Current
Inductor Curent
ISD
Ripple ≤ 5%
* VGS = 5V for Logic Level Devices
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
V(BR)DSS
15V
DRIVER
L
VDS
tp
D.U.T
RG
+
V
- DD
IAS
VGS
20V
A
0.01Ω
tp
I AS
Fig 22a. Unclamped Inductive Test Circuit
RD
VDS
Fig 22b. Unclamped Inductive Waveforms
VDS
90%
VGS
D.U.T.
RG
+
- VDD
V10V
GS
10%
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
td(on)
Fig 23a. Switching Time Test Circuit
tr
t d(off)
Fig 23b. Switching Time Waveforms
Id
Current Regulator
Same Type as D.U.T.
Vds
Vgs
50KΩ
12V
tf
.2μF
.3μF
D.U.T.
+
V
- DS
Vgs(th)
VGS
3mA
IG
ID
Current Sampling Resistors
Fig 24a. Gate Charge Test Circuit
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Qgs1 Qgs2
Qgd
Qgodr
Fig 24b. Gate Charge Waveform
7
IRFB3006PbF
TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
ASS EMBLED ON WW 19, 2000
IN T HE ASS EMBLY LINE "C"
Note: "P" in as sembly line position
indicates "Lead - Free"
INT ERNAT IONAL
RECT IFIER
LOGO
AS SEMBLY
LOT CODE
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 19
LINE C
TO-220AB packages are not recommended for Surface Mount Application.
Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/08
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