19-4994; Rev 0; 10/09 KIT ATION EVALU LE B A IL A AV 76V, APD, Bias Output Stage with Current Monitoring The DS1842A integrates the discrete high-voltage components necessary for avalanche photodiode (APD) bias and monitor applications. A switch FET and precision voltage-divider network are used in conjunction with an external DC-DC controller to create a boost DC-DC converter. A current clamp limits current through the APD and also features an external shutdown. The precision voltage-divider network is provided for precise control of the APD bias voltage. The device also includes a dual current mirror to monitor the APD current. Features ♦ 76V Maximum Boost Voltage ♦ Switch FET ♦ Current Monitor with a Wide 1µA to 2mA Range, Fast 50ns Time Constant, and 10:1 and 5:1 Ratio ♦ 2mA Current Clamp with External Shutdown ♦ Precision Voltage Feedback ♦ Multiple External Filtering Options ♦ 3mm x 3mm, 14-Pin TDFN Package with Exposed Pad Ordering Information Applications TEMP RANGE PIN-PACKAGE DS1842AN+ PART -40°C to +85°C 14 TDFN-EP* DS1842AN+T&R -40°C to +85°C 14 TDFN-EP* APD Biasing GPON ONU and OLT +Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad. Typical Application Circuit 3.3V LX FBIN CBULK DS1842A GATE SW MIRIN R1 PGND CURRENT MIRROR FBOUT FB MIR1 R2 CCOMP R COMP COMP D2 CLAMP EP GND CURRENT LIMIT MIR2 EXTERNAL MONITOR MIROUT DS1875 ROSA APD TIA MON3 NOTE: SEE THE LAYOUT CONSIDERATIONS SECTION. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 DS1842A General Description DS1842A 76V, APD, Bias Output Stage with Current Monitoring ABSOLUTE MAXIMUM RATINGS Voltage Range on GATE and CLAMP Relative to GND...................................................-0.3V to +12V Voltage Range on MIRIN, MIROUT, FBIN MIR1, and MIR2 Relative to GND........................-0.3V to +80V Voltage Range on FBOUT Relative to GND ..........-0.3V to +6.0V Voltage Range on LX Relative to GND...................-0.3V to +85V Operating Junction Temperature Range ...........-40°C to +150°C Storage Temperature Range .............................-55°C to +135°C Soldering Temperature ..........................Refer to the IPC JEDEC J-STD-020 Specification. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C, unless otherwise noted.) PARAMETER Switching Frequency FET Capacitance FET Gate Resistance FET On-Resistance SYMBOL f SW C GATE CLX RDSON VGS Switching Current ILX LX Voltage VLX CLAMP Voltage CLAMP Threshold Maximum MIROUT Current MIN I IL(LX) TYP 0 VGS = 0V, VDS = 25V 40 f SW = 1MHz 90 RG GATE Voltage LX Leakage CONDITIONS MAX UNITS 1.2 MHz pF 22 VGS = 3V, ID = 170mA 1 2 VGS = 10V, ID = 170mA 0.75 1.4 0 Duty cycle = 10%, f SW = 100kHz 11 V 680 mA 80 V μA -1 +1 VCLAMP 0 11 V VCLT 1.25 1.8 2.35 V 1.8 2.75 3.85 mA IMIROUT VGATE = 0V, VLX = 76V CLAMP = low CLAMP = high μA MIR1 to MIROUT Ratio KMIR1 MIR2 to MIROUT Ratio KMIR2 MIR1, MIR2 Rise Time (20%/80%) tRC (Note 1) 30 Shutdown Temperature T SHDN (Note 2) +150 °C Hysteresis Temperature THYS (Note 2) 5 °C Leakage on GATE and CLAMP IIL Resistor-Divider Ratio (R1/R2) KR 15V < VMIRIN < 76V, IMIROUT > 1μA 15V < VMIRIN < 76V, IMIROUT > 1μA 10 TA = +25°C, VFBIN = 76V 0.096 0.100 0.104 A/A 0.192 0.200 0.208 A/A -1 +1 59.5 60.25 Resistor-Divider Tempco Resistor-Divider End-to-End Resistance ±50 RRES TA = +25°C, VFBIN = 76V 308 385 Note 1: Rising MIROUT transition from 10µA to 1mA; VMIRIN = 40V, 2.5kΩ load. Note 2: Not production tested. Guaranteed by design. 2 ns _______________________________________________________________________________________ μA ppm/°C 481 k 76V, APD, Bias Output Stage with Current Monitoring MIRIN CURRENT vs. MIROUT CURRENT (VMIRIN = 40V) 1000 100 DS1842A toc02 DS1842A toc01 100 90 80 MIRIN CURRENT (μA) MIRIN CURRENT (μA) 10,000 MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 250nA) 70 60 50 40 30 20 10 10 0 10 1 100 1000 10,000 -20 0 40 60 80 MIRIN CURRENT vs. TEMPERATURE (VMIRIN = 40V, IMIROUT = 2mA) MIR ERROR vs. TEMPERATURE (IMIROUT = 1μA) DS1842A toc04 VMIRIN = 40V ERROR (%) 1 3 2 100 2 DS1842A toc03 4 MIR2 0 MIR1 -1 1 -2 0 -20 0 20 40 60 80 -40 100 -20 0 MIR ERROR vs. TEMPERATURE (IMIROUT = 1mA) 40 60 80 100 MIR ERROR vs. MIROUT CURRENT 2 VMIRIN = 40V DS1842A toc05 2 VMIRIN = 40V 1 ERROR (%) 1 0 20 TEMPERATURE (°C) TEMPERATURE (°C) MIR2 DS1842A toc06 -40 ERROR (%) 20 TEMPERATURE (°C) 5 MIRIN CURRENT (mA) -40 MIROUT CURRENT (μA) MIR2 0 MIR1 MIR1 -1 -1 -2 -2 -40 -20 0 20 40 60 TEMPERATURE (°C) 80 100 1 10 100 1000 10,000 MIROUT CURRENT (μA) _______________________________________________________________________________________ 3 DS1842A Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) Typical Operating Characteristics (continued) (TA = +25°C, unless otherwise noted.) MIROUT CLAMP CURRENT vs. MIRIN VOLTAGE MIR ERROR vs. MIRIN VOLTAGE 3.4 3.3 IMIR2 = 1mA 3.2 IMIROUT (mA) ERROR (%) DS1842A toc08 IMIR2 = 1μA 1 3.5 DS1842A toc07 2 0 IMIR1 = 1μA IMIR1 = 1mA TA = -40°C 3.1 3.0 TA = +25°C 2.9 2.8 -1 TA = +85°C 2.7 2.6 2.5 10 20 30 40 50 60 70 10 80 20 30 40 50 MIRIN VOLTAGE (V) FET ON-RESISTANCE vs. DRAIN CURRENT FET ON-RESISTANCE vs. TEMPERATURE 2.0 DS1842A toc09 2.0 VGS = 2.5V VGS = 2.5V VGS = 3.6V 1.0 VGS = 3.0V VGS = 5.0V VGS = 5V VGS = 3.6V VGS = 10V VGS = 10V 0 0.5 1 10 1000 100 -40 -20 0 20 40 60 TEMPERATURE (°C) RESISTOR-DIVIDER RATIO vs. FBIN VOLTAGE RESISTOR-DIVIDER RATIO vs. TEMPERATURE DS1842A toc11 100 80 100 VFBIN = 40V 59.95 RATIO (KR) 60.0 60.00 80 DS1842A toc12 IDS (mA) 60.1 59.9 59.90 59.8 59.85 59.7 59.80 10 20 30 40 50 FBIN VOLTAGE (V) 4 80 VGS = 3.0V RDSON (Ω) RDSON (Ω) 1.5 1.0 70 ID = 170mA 1.5 0.5 60 MIRIN VOLTAGE (V) DS1842A toc10 -2 RATIO (KR) DS1842A 76V, APD, Bias Output Stage with Current Monitoring 60 70 80 -40 -20 0 20 40 60 TEMPERATURE (°C) _______________________________________________________________________________________ 76V, APD, Bias Output Stage with Current Monitoring Block Diagram TOP VIEW DS1842A 1 MIR2 2 GND 3 FBOUT 4 CLAMP 5 GATE 6 14 MIROUT + MIR1 13 MIRIN FBIN MIRIN LX R2 CURRENT MIRROR 12 FBIN GATE DS1842A 11 N.C. 9 N.C. 7 8 LX MIR1 MIR2 PGND 10 N.C. CURRENT LIMIT CLAMP *EP PGND R1 FBOUT THERMAL SHUTDOWN TDFN *EXPOSED PAD. EP GND MIROUT Pin Description PIN NAME 1 MIR1 2 MIR2 Current Mirror Monitor Output, 5:1 Ratio GND Ground Connection for Device. Connect directly to ground plane. Connect GND to PGND at a single point. See the Layout Considerations section for more information. 3 FUNCTION Current Mirror Monitor Output, 10:1 Ratio 4 FBOUT Feedback Output. Resistor-divider output. 5 CLAMP Clamp Input. Disables the current mirror output (MIROUT). 6 GATE FET Gate Connection 7 PGND Source of Switch FET. Also connect to boost converter’s input and output capacitors. Connect PGND to GND at a single point. See the Layout Considerations section for more information. 8 LX 9, 10, 11 N.C. FET Drain Connection. Connect to switching inductor. No Connection 12 FBIN Feedback Input. Resistor-divider input. 13 MIRIN Current Mirror Input 14 MIROUT — EP Current Mirror Output. Connect to APD bias pin. Exposed Pad. Connect directly to the same ground plane as GND. Detailed Description The DS1842A contains discrete high-voltage components required to create an APD bias voltage and to monitor the APD bias current. The device’s mirror outputs are a current that is a precise ratio of the output current across a large dynamic range. The mirror response time is fast enough to comply with GPON Rx burst-mode monitoring requirements. The device has a built-in current-limiting feature to protect APDs. The APD current can also be shut down by CLAMP or thermal shutdown. The internal FET and resistor-divider are used in conjunction with a DC-DC boost controller to precisely create the APD bias voltage. Current Mirror The DS1842A has two current mirror outputs. One is a 10:1 mirror connected at MIR1, and the other is a 5:1 mirror connected to MIR2. _______________________________________________________________________________________ 5 DS1842A Pin Configuration DS1842A 76V, APD, Bias Output Stage with Current Monitoring Thermal Shutdown MIR1 CLAMP As a safety feature, the DS1842A has a thermal-shutdown circuit that turns off the MIROUT and MIRIN currents when the internal die temperature exceeds TSHDN. These currents resume after the device has cooled. Switch FET The DS1842A switching FET is designed to complement the DS1875 controller’s built-in DC-DC boost controller. APD biasing of 16V to 76V can be achieved using the DS1842A. REF Figure 1. Current Clamp from Current Feedback The mirror output is typically connected to an ADC using a resistor to convert the mirrored current into a voltage. The resistor to ground should be selected such that the maximum full-scale voltage of the ADC is reached when the maximum mirrored current is reached. For example, if the maximum monitored current through the APD is 2mA with a 1V ADC full scale, and the 10:1 mirror is used, then the correct resistor is approximately 5kΩ. If both MIR1 and MIR2 are connected together, the correct resistor is 1.6kΩ. The mirror response time is dominated by the amount of capacitance placed on the output. For burst-mode Rx systems where the fastest response times are required (approximately a 50ns time constant), a 3.3pF capacitor and external op amp should be used to buffer the signal sent to the ADC. For continuous mode applications, a 10nF capacitor is all that is required on the output. Current Clamp The DS1842A has a current clamping circuit to protect the APD by limiting the amount of current from MIROUT. There are three methods of current clamping available: 1) Internally Defined Current Limit The device’s current clamp circuit automatically clamps the current when it exceeds the maximum MIROUT current. 2) External Shutdown Signal The CLAMP pin can completely shut down the current from MIROUT. The CLAMP pin is active high. 3) Precise Level Set by External Feedback Circuit A feedback circuit is used to control the level applied to the CLAMP pin. Figure 1 shows an example feedback circuit. Precision Voltage-Divider The DS1842A includes a resistor-divider to use as the feedback network for the boost converter. The DS1842A resistor-divider ratio, KR (R1/R2), is tightly controlled, allowing the boost converter output to be set with very high precision. KR can pair with the DS1875’s internal DC-DC boost controller. KR can also be easily modified by adding external series/parallel resistors; however, the temperature coefficient of the external resistors must be considered. Applications Information Layout Considerations Proper PCB layout helps reduce switching noise in the system. PGND is the connection of the switching FET and thus carries high current pulses. PGND should also be connected to the boost converter’s input capacitor and output bulk capacitor. Ensure that the PGND trace is low impedance and able to carry the high current from the FET. To keep the switching noise on PGND isolated from GND, a star ground configuration should be used. PGND and GND should only be connected together at one point on the PCB. This point can be either the ground side of the output bulk capacitor or the common ground point of the PCB. Keeping all PCB traces as short as possible reduces radiated noise, stray capacitance, and trace resistance. Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 14 TDFN-EP T1433+2 21-0137 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.