19-2555; Rev 1; 12/02 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply The MAX1932 generates a low-noise, high-voltage output to bias avalanche photodiodes (APDs) in optical receivers. Very low output ripple and noise is achieved by a constant-frequency, pulse-width modulated (PWM) boost topology combined with a unique architecture that maintains regulation with an optional RC or LC post filter inside its feedback loop. A precision reference and error amplifier maintain 0.5% output voltage accuracy. The MAX1932 protects expensive APDs against adverse operating conditions while providing optimal bias. Traditional boost converters measure switch current for protection, whereas the MAX1932 integrates accurate high-side current limiting to protect APDs under avalanche conditions. A current-limit flag allows easy calibration of the APD operating point by indicating the precise point of avalanche breakdown. The MAX1932 control scheme prevents output overshoot and undershoot to provide safe APD operation without data loss. The output voltage can be accurately set with either external resistors, an internal 8-bit DAC, an external DAC, or other voltage source. Output span and offset are independently settable with external resistors. This optimizes the utilization of DAC resolution for applications that may require limited output voltage range, such as 4.5V to 15V, 4.5V to 45V, 20V to 60V, or 40V to 90V. Features ♦ Small Circuit Footprint ♦ Circuit Height < 2mm ♦ 2.7V to 5.5V Input ♦ ♦ ♦ ♦ 4.5V to 90V Output No Overshoot Accurate High-Side Current Limit Avalanche Indicator Flag ♦ ♦ ♦ ♦ 8-Bit SPI-Compatible DAC Compatible with External DAC 0.5% Accurate Output Low Ripple Output (< 1mV) ♦ Small 12-Pin, 4mm ✕ 4mm Thin QFN Package Ordering Information PART TEMP RANGE MAX1932ETC PIN-PACKAGE -40°C to +85°C 12 Thin QFN Applications Optical Receivers and Modules Fiber Optic Network Equipment Telecom Equipment Laser Range Finders PIN Diode Bias Supply Typical Application Circuit Pin Configuration INPUT 2.7V TO 5.5V SCLK 1 DIN 2 VIN GATE 12 11 10 MAX1932 COMP 9 GND 8 COMP 7 4 5 6 CS- DACOUT 3 APD BIAS OUTPUT 4.5V TO 90V MAX1932 GATE CS DAC INPUTS CS+ CL CS VIN FB SCLK CS+ CS- DIN AVALANCHE INDICATOR FLAG CL FB GND DACOUT ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX1932 General Description MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply ABSOLUTE MAXIMUM RATINGS VIN to GND...............................................................-0.3V to +6V DIN, SCLK, CS, FB to GND ......................................-0.3V to +6V COMP, DACOUT, GATE, CL to GND ...........-0.3V to (VIN +0.3V) CS+, CS- to GND .................................................-0.3V to +110V Continuous Power Dissipation (TA = +70°C) 12-Pin Thin QFN (derate 16.9mW/°C above +70°C) .1349mW Operating Temperature Range ...........................-40°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +150°C Lead Temperature (soldering 10s) ..................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS GENERAL Input Supply Range VIN VIN Undervoltage Lockout UVLO Operating Supply Current IIN VIN Shutdown Supply Current ISHDN Input Resistance for CS+/CS- Both rise/fall, hysteresis = 100mV CS+ = 3V to 100V Gate-Driver Resistance Gate high or low, IGATE = ±50mA FB Input Bias Current VFB 1 mA 25 65 µA 0.5 1 2.0 MΩ 1.80 2.00 2.20 V ±0.005 5 1.24250 1.2500 1.25750 0.0007 DAC code = 00 hex DACOUT to FB Voltage Difference DAC code = FF hex DACOUT Differential Nonlinearity (Note 1) DAC Code = 01 to FF hex, DAC guaranteed monotonic 50 tON %/°C µS 100 Ω -3 +3 mV -1 +1 LSB 0.0007 DAC code = 0F to FF hex, source or sink 50µA fOSC 110 V 200 TCVDACOUT GATE Maximum On-Time Ω nA 1.24375 1.2500 1.25625 COMP Pulldown Resistance in Shutdown Switching Frequency 10 +25 TA = 0°C to +85°C TCVFB DACOUT Load Regulation %/V TA = +25°C COMP = 1.5V 2 V -25 FB to COMP Transconductance DACOUT Voltage Temperature Coefficient V 2.6 00 hex loaded to DAC Resistance from either pin to ground Common-Mode Rejection of Current Threshold FB Voltage Temperature Coefficient 5.5 2.1 0.5 Current-Limit Threshold for CS+/CS- FB Voltage 2.7 -1 250 300 3 _______________________________________________________________________________________ %/°C +1 mV 340 kHz µs Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply (VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = 0°C to +85°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 0.6 V DIGITAL INPUTS (DIN, SCLK, CS) Input Low Voltage Input High Voltage 1.4 Input Hysteresis V 200 TA = +25°C Input Leakage Current -1 TA = 0°C to +85°C Input Capacitance mV +1 µA 10 nA 5 pF DIGITAL OUTPUT (CL) Output Low Voltage ISINK = 1mA Output High Voltage ISOURCE = 0.5mA 0.1 VIN - 0.5 V V SPI TIMING (FIGURE 5) SCLK Clock Frequency fSCLK 2 MHz SCLK Low Period tCL 125 ns SCLK High Period tCH 125 ns Data Hold Time tDH 0 ns Data Setup Time tDS 125 ns CS Assertion to SCLK Rising Edge Setup Time tCSS0 200 ns CS Deassertion to SCLK Rising Edge Setup Time tCSS1 200 ns SCLK Rising Edge to CS Deassertion tCSH1 200 ns SCLK Rising Edge to CS Assertion tCSH0 200 ns CS High Period tCSW 300 ns ELECTRICAL CHARACTERISTICS (VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.7 5.5 V 2.1 2.6 V 1 mA 65 µA 0.5 2 MΩ 1.80 2.20 V 10 Ω +30 nA GENERAL Input Supply Range VIN VIN Undervoltage Lockout UVLO Operating Supply Current IIN VIN Shutdown Supply Current Input Resistance for CS+/CS- ISHDN Both rise/fall, hysteresis = 100mV 00 hex loaded to DAC Resistance from either pin to ground Current-Limit Threshold for CS+/CSGate-Driver Resistance FB Input Bias Current Gate high or low, IGATE = ±50mA -30 _______________________________________________________________________________________ 3 MAX1932 ELECTRICAL CHARACTERISTICS (continued) MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply ELECTRICAL CHARACTERISTICS (continued) (VIN = 3.3V, CS = SCLK = DIN = 3.3V, CS+ = CS- = 45V, Circuit of Figure 2, TA = -40°C to +85°C, unless otherwise noted.) (Note 2) PARAMETER FB Voltage SYMBOL CONDITIONS VFB FB to COMP Transconductance COMP = 1.5V COMP Pulldown Resistance in Shutdown DAC code = 00 hex MAX UNITS 1.23875 MIN TYP 1.26125 V 50 200 µS 100 Ω DACOUT to FB Voltage Difference DAC code = FF hex -4 +4 mV DACOUT Differential Nonlinearity (Note 1) DAC Code = 01 to FF hex, DAC guaranteed monotonic -1 +1 LSB DACOUT Load Regulation DAC code = 0F to FF hex, source or sink 50µA -1 +1 mV 240 360 kHz 0.6 V Switching Frequency fOSC DIGITAL INPUTS (DIN, SCLK, CS) Input Low Voltage Input High Voltage 1.4 V DIGITAL OUTPUT (CL) Output Low Voltage ISINK = 1mA Output High Voltage ISOURCE = 0.5mA 0.1 VIN - 0.5 V V SPI TIMING (FIGURE 5) SCLK Clock Frequency fSCLK 2 MHz SCLK Low Period tCL 125 ns SCLK High Period tCH 125 ns Data Hold Time tDH 0 ns Data Setup Time tDS 125 ns CS Assertion to SCLK Rising Edge Setup Time tCSS0 200 ns CS Deassertion to SCLK Rising Edge Setup Time tCSS1 200 ns SCLK Rising Edge to CS Deassertion tCSH1 200 ns SCLK Rising Edge to CS Assertion tCSH0 200 ns CS High Period tCSW 300 ns Note 1: DACOUT = DAC code x (1.25V/256) + 1.25V/256. Note 2: Specifications to -40°C are guaranteed by design and not production tested. 4 _______________________________________________________________________________________ Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply SWITCHING WAVEFORM WITH LC FILTER SWITCHING WAVEFORMS MAX1932 toc01 VLX MAX1932 toc03 VLX 50V/div 50V/div IL IL VOUT RIPPLE (AC-COUPLED) VOUT RIPPLE (AC-COUPLED) 0.002V/div 50V/div INPUT CURRENT 50mA/div 0.002V/div VOUT = 90V, L = 300µH, C = 1µF, FIGURE 7 1µs/div 1µs/div OUTPUT VOLTAGE vs. INPUT VOLTAGE VFB vs. TEMPERATURE OUTPUT VOLTAGE vs. LOAD CURRENT 1.2515 1.2510 VFB (V) 1.2505 90 1.2500 1.2495 89 88 4.5 80 75 70 65 60 1.2485 55 5.5 CURRENT LIMIT ACTIVATED 85 1.2490 1.2480 3.5 90 OUTPUT VOLTAGE (V) 91 95 MAX1932 toc05 1.2520 MAX1932 toc04 92 20ms/div MAX1932 toc06 VOUT = 90V 2.5 OUTPUT VOLTAGE 0.05A/div 0.05A/div OUTPUT VOLTAGE (V) STARTUP AND SHUTDOWN WAVEFORMS MAX1932 toc02 VCC = 5V, INDUCTOR = 100µH, R1 = 806Ω FEEDBACK DIVIDER CURRENT AND CSCURRENT INCLUDED 50 -60 -40 -20 0 20 40 60 80 100 0 0.5 1.0 1.5 2.0 2.5 INPUT VOLTAGE (V) TEMPERATURE (°C) LOAD CURRENT (mA) OUTPUT VOLTAGE STEP-DOWN DUE TO DAC CHANGE OUTPUT VOLTAGE STEP-UP DUE TO DAC CHANGE OUTPUT VOLTAGE STEP DUE TO DACOUT CHANGE MAX1932 toc07 MAX1932 toc08 OFFSET = 62.962V = 88 hex STEP DOWN FROM 80 hex TO 88 hex 3.0 MAX1932 toc09 OFFSET = 62.962V = 88 hex STEP VALUE = 64.233 = 80 hex 20V/div VOUT AT 64.233V VOUT AT 1V/div 62.692V OFFSET 1V/div DACOUT EXTERNAL SOURCE 0.5V/div 10ms/div 10ms/div 20ms/div _______________________________________________________________________________________ 5 MAX1932 Typical Operating Characteristics (VIN = 5V, Circuit of Figure 2, TA =+25°C, unless otherwise noted) Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932 Pin Description PIN NAME FUNCTION 1 SCLK DAC Serial Clock Input 2 DIN DAC Serial Data Input 3 CL Current-Limit Indicator Flag. CL = 0 indicates that the part is in current limit. Logic high level = VIN. 4 CS+ Current-Limit Plus Sense Input. Connect a resistor from CS+ to CS- in series with the output. The differential threshold is 2V. CS+ has typically 1MΩ resistance to ground. 5 CS- Current-Limit Minus Sense Input. CS- has typically 1MΩ resistance to ground. 6 DACOUT 7 FB 8 COMP Internal DAC Output. Generates a control voltage for adjustable output operation. DACOUT can source or sink 50µA. Feedback input. Connect to a resistive voltage-divider between the output voltage (VOUT) and FB to set the output voltage. The feedback set point is 1.25V. Compensation Pin. Compensates the DC-DC converter control loop with a series RC to GND. COMP is actively discharged to ground during shutdown or undervoltage conditions. 9 GND 10 GATE Ground 11 VIN IC Supply Voltage (2.7V to 5.5V). Bypass VIN with a 1µF or greater ceramic capacitor. 12 CS DAC Chip-Select Input Gate-Driver Output for External N-FET Detailed Description Fixed Frequency PWM The MAX1932 uses a constant frequency, PWM, controller architecture. This controller sets the switch ontime and drives an external N-channel MOSFET (see Figure 1). As the load varies, the error amplifier sets the inductor peak current necessary to supply the load and regulate the output voltage. Output Current Limit The MAX1932 uses an external resistor at CS+ and CSto sense the output current (see Figure 2). The typical current-limit threshold is 2V. CL is designed to help find the optimum APD bias point by going low to indicate when the APD reaches avalanche and that current limit has been activated. To minimize noise, CL only changes state on an internal oscillator edge. Output Control DAC An internal digital-to-analog converter can be used to control the output voltage of the DC-DC converter (Figure 2). The DAC output is changed through an SPI™ serial interface using an 8-bit control byte. On power-up, the DAC defaults to FF hex (1.25V), which corresponds to a minimum boost converter output voltage. Alternately, the output voltage can be set with external resistors, an external DAC, or a voltage source. Output span and offset are independently settable with exter- nal resistors. See the Applications Information section for output control equations. SPI Interface/Shutdown Use an SPI-compatible 3-wire serial interface with the MAX1932 to control the DAC output voltage and to shut down the MAX1932. Figures 4 and 5 show timing diagrams for the SPI protocol. The MAX1932 is a write-only device and uses CS along with SCLK and DIN to communicate. The serial port is always operational when the device is powered. To shut down the DC-DC converter portion only, update the DAC registers to 00 hex. Applications Information Voltage Feedback Sense Point Feedback can be taken from in front of, or after, the current-limit sense resistor. The current-limit sense resistor forms a lowpass filter with the output capacitor. Taking feedback after the current-limit sense resistor (see Figure 2), optimizes the output voltage accuracy, but requires overcompensation, which slows down the control loop response. For faster response, the feedback can be taken from in front of the current-sense resistor (see Figure 3). This configuration however, makes the output voltage more sensitive to load variation and degrades output accuracy by an amount equal to the load current times the current-sense resistor value. SPI is a trademark of Motorola, Inc. 6 _______________________________________________________________________________________ Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply The inductance value is given by: L= (VIN )2 × D2 × T × η 2IOUT(MAX) × VOUT The DAC output voltage is given by the following equation: 1.25V 1.25V VDACOUT = CODE × + 256 256 On power-up, DACOUT defaults to FF hex or 1.25V, which corresponds to the minimum VOUT output voltage. The voltage generated at DACOUT is coupled to FB through R6. DACOUT can sink only 50µA so: 1.25V R6 ≥ 50µA Select the minimum output voltage (VOUTFF), and the maximum output voltage (V OUT01 ) for the desired adjustment range. R5 sets the adjustment span using the following equation: R5 = (VOUTFF - VOUT01) (R6/1.25V) R8 sets the minimum output of the adjustment range with the following equation: R8 = (1.25V ✕ R5)/(VOUTFF) Setting the Output Voltage without the DAC Adjust the output voltage by connecting a voltagedivider from the output (VOUT) to FB (Figure 2 with R6 omitted). Select R8 between 10kΩ to 50kΩ. Calculate R5 with the following equation: VOUT R5 = R8 − 1 1.25V Inductor Selection Optimum inductor selection depends on input voltage, output voltage, maximum output current, switching frequency, and inductor size. Inductors are typically specified by their inductance (L), peak current (IPK), and resistance (LR). where VIN is the input voltage, IOUT(MAX) is the maximum output current delivered, VOUT is the output voltage, and T is the switching period (3.3µs), η is the estimated power conversion efficiency, and D is the maximum duty cycle: D < (VOUT - VIN)/VOUT up to a maximum of 0.9 Since the L equation factors in efficiency, for inductor calculation purposes, an η of 0.5 to 0.75 is usually suitable. For example, with a maximum DC load current of 2.5mA, a 90V output, VIN = 5V, D = 0.9, T = 3.3µs, and η estimated at 0.75, the above equation yields an L of 111µH, so 100µH would be a suitable value. The peak inductor current is given by: V ×D× T IPK = IN L These are typical calculations. For worst case, refer to the article titled “Choosing the MAX1932 External Indicator, Diode, Current Sense Resistor, and Output Filter Capacitor for Worst Case Conditions” located on the Maxim website in the Application Notes section (visit www.maxim-ic.com/an1805). External Power-Transistor Selection An N-FET power switch is required for the MAX1932. The N-FET switch should be selected to have adequate onresistance with the MOSFET VGS = VIN(MIN). The breakdown voltage of the N-FET must be greater than VOUT. For higher-current output applications (such as 5mA at 90V), SOT23 high-voltage low-gate-threshold N-FETs may not have adequate current capability. For example, with a 5V input, a 90V, 5mA output requires an inductor peak of 240mA. For such cases it may be necessary to simply parallel two N-FETs to achieve the required current rating. With SOT23 devices this often results in smaller and lower cost than using a larger N-FET device. Diode Selection The output diode should be rated to handle the output voltage and the peak switch current. Make sure that the diode’s peak current rating is at least IPK and that its breakdown voltage exceeds VOUT. Fast reverse recovery time (t rr < 10ns) and low junction capacitance _______________________________________________________________________________________ 7 MAX1932 Output and DAC Adjustments Range Many biasing applications require an adjustable output voltage, which is easily obtained using the MAX1932’s DAC output (Figure 2). MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply (<10pF) are recommended to minimize losses. A smallsignal silicon switching diode is suitable if efficiency is not critical. Output Filter Capacitor Selection The output capacitors of the MAX1932 must have high enough voltage rating to operate with the V OUT required. Output capacitor effective series resistance (ESR) determines the amplitude of the high-frequency ripple seen on the output voltage. In the typical application circuit, a second RC formed by R1 and C3 further reduces ripple. Input Bypass Capacitor Selection The input bypass capacitor reduces the peak currents drawn from the voltage source and reduces noise caused by the MAX1932’s switching action. The input source impedance determines the size of the capacitor required at the input (VIN). A low ESR capacitor is recommended. A 1µF ceramic capacitor is adequate for most applications. Place the bypass capacitor as close as possible to the VIN and GND pins. Current-Sense Resistor Selection Current limit is used to set the maximum delivered output current. In the typical application circuit, MAX1932 is designed to current limit at: R1 = 2V ILIMIT Note that ILIMIT must include current drawn by the feedback divider (if sensing feedback after R1) and the input current of CS-. Stability and Compensation Component Selection Compensation components, R7 and C4, introduce a pole and a zero necessary to stabilize the MAX1932 (see Figure 6). The dominant pole, POLE1, is formed by the output impedance of the error amplifier (REA) and C4. The R7/C4 zero, ZERO1, is selected to cancel the pole formed by the output filter cap C3 and output load R LD, POLE2. The additional pole of R1/C3, POLE3, should be at least a decade past the crossover frequency to not affect stability: POLE1 (dominant pole) = 1 / (2π ✕ REA ✕ C4) ZERO1 (integrator zero) = 1 / (2π ✕ R7 ✕ C4) POLE2 (output load pole) = K1 / (2π ✕ RLD ✕ (C2 + C3)) POLE3 (output filter pole) = 1 / (2π ✕ R1 ✕ C3) The DC open-loop gain is given by: AOL = K2 ✕ Gm ✕ REA 8 where REA = 310MΩ, gM = 110µS, RLD is the parallel combination of feedback network and the load resistance. K1 = 2 × VOUT - VIN VOUT - VIN 2 × VIN V (Volts) K2 = FB × × 0.75 (Volts) 2 × VOUT - VIN VOUT RLD × T(second) VOUT - VIN 2 × L (Henries) A properly compensated MAX1932 results in a gain vs. frequency plot that crosses 0dB with a single pole slope (20dB per decade). See Figure 6. Table 1 lists suggested component values for several typical applications. Further Noise Reduction The current-limit sense resistor is typically used as part of an output lowpass filter to reduce noise and ripple. For further reduction of noise, an LC filter can be added as shown in Figure 7. Output ripple and noise with and without the LC filter are shown in the Typical Operating Characteristics. If a post LC filter is used, it is best to use a coil with fairly large resistance (or a series resistor) so that ringing at the response peak of the LC filter is damped. For a 330µH and 1µF filter, 22Ω accomplishes this, but a resistor is not needed if the coil resistance is greater than 15Ω. Output Accuracy and Feedback Resistor Selection The MAX1932 features 0.5% feedback accuracy. The total voltage accuracy of a complete APD bias circuit is the sum of the FB set-point accuracy, plus resistor ratio error and temperature coefficient. If absolute accuracy is critical, the best resistor choice is an integrated network with specified ratio tolerance and temperature coefficient. If using discrete resistors in high-accuracy applications, pay close attention to resistor tolerance and temperature coefficients. Temperature Compensation APDs exhibit a change in gain as a function of temperature. This gain change can be compensated with an appropriate adjustment in bias voltage. For this reason it may be desirable to vary the MAX1932 output voltage as a function of temperature. This can be done in soft- _______________________________________________________________________________________ Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932 Table 1. Compensation Components for Typical Circuits (Figure 2) INDUCTOR L1 (µH) CSNS C2 (µF) 5VIN, 40-90VOUT at 2.5mA 100 0.047 5VIN, 20-60VOUT at 2.5mA 150 0.10 VIN, VOUT, IOUT(MAX) RSNS R1 (Ω) COUT C3 (µF) RCOMP R7 (kΩ) CCOMP C4 (µF) 806 0.1 20 0.22 806 0.047 15 0.22 5VIN, 20-60VOUT at 5mA 82 0.22 392 0.10 10 0.47 3VIN, 40-90VOUT at 2.5mA 33 0.047 806 0.1 20 0.22 3VIN, 4.5-15VOUT at 2.5mA 220 0.47 806 0.01 7.5 0.47 ware by the system through the on-chip DAC, but can also be accomplished in hardware using an external thermistor or IC temperature sensor. Figure 8 shows how an NTC thermistor can be connected to make the bias voltage increase with temperature. Chip Information TRANSISTOR COUNT: 1592 PROCESS: BICMOS PC Board Layout and Grounding Careful PC board layout is important for minimizing ground bounce and noise. In addition, keep all connections to FB as a short as possible. In particular, locate feedback resistors (R5, R6, and R8) as close to FB as possible. Use wide, short traces to interconnect large current paths for N1, D1, L1, C1, C2. Do not share these connections with other signal paths. Refer to the MAX1932 EV kit for a PC board layout example. _______________________________________________________________________________________ 9 MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply COMP VIN UVLO REF 1.25V PWM CONTROL AND GATE DRIVER FB GATE ERROR AMPLIFIER RAMP ERROR COMPARATOR GND OSC 987kΩ CS+ CLIM CL 13kΩ BUFFER 987kΩ CS13kΩ REF SCLK DIN SPI SERIAL INTERFACE DACOUT 8 8-BIT DAC CS Figure 1. Functional Diagram 10 ______________________________________________________________________________________ Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply L1 100µH VIN CL COMP R7 20kΩ MAX1932 C1 1µF INPUT 2.7V TO 5.5V D1 100V R1 806Ω VOUT 40V TO 90V MAX1932 C4 0.22µF C2 0.047 GATE C3 0.1µF N1 BSS123 CS CS+ CS- SCLK R5 1MΩ DIN FB GND DACOUT R6 24.9kΩ R8 32.4kΩ Figure 2. Typical Operating Circuit INSTRUCTION EXECUTED VOUT CS GATE 1 FB 8 SCLK MAX1932 DIN D7 CS+ D6 D5 D4 D3 D2 D1 DO CS- Figure 3. Taking Feedback Ahead of Output Filter Figure 4. Serial Interface Timing Diagram ______________________________________________________________________________________ 11 MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply CS tCSW tCSH0 tCSS0 tCSH1 tCH SCLK tCL tDS tCSS1 tDH DIN Figure 5. Detailed Serial Interface Timing Diagram 12 ______________________________________________________________________________________ Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply MAX1932 120 100 80 90V, 1mA 90V, 2.5mA POLE1 0.0023Hz 0.0023Hz ZERO1 36Hz 36Hz POLE2 36Hz 91Hz POLE3 4.2kHz 4.2kHz AOL 102dB 98dB MAGNITUDE (dB) 60 40 36Hz 91Hz 20 0.01 0.1 1.0 FREQUENCY (Hz) 10 100 1k 10k 4.2k Figure 6. Loop Response ______________________________________________________________________________________ 13 MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply VIN 330µH VOUT 0.1µF 1µF GATE FB MAX1932 CS+ CS- Figure 7. Adding a Post LC Filter VIN TO CS+ TO CSR1 VOUT GATE R5 MAX1932 FB R8 R9 R10 NTC THERMISTOR Figure 8. Adding an NTC Thermistor for Hardware Temperature Compensation; Output Voltage Increases with Temperature Rise 14 ______________________________________________________________________________________ Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A ______________________________________________________________________________________ 15 MAX1932 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX1932 Digitally Controlled, 0.5% Accurate, Safest APD Bias Supply Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) PACKAGE OUTLINE 12,16,20,24L QFN THIN, 4x4x0.8 mm 21-0139 A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.