LT3581 3.3A Boost/Inverting DC/DC Converter with Fault Protection Features n n n n n n n n n n n n Description 3.3A, 42V Combined Power Switch Master/Slave (1.9A/1.4A) Switch Design Output Short Circuit Protection Wide Input Range:2.5V to 22V Operating, 40V Maximum Transient Switching Frequency Up to 2.5MHz Easily Configurable as a Boost, SEPIC, Inverting or Flyback Converter User Configurable Undervoltage Lockout Low VCESAT Switch: 250mV at 2.75A (Typical) Can be Synchronized to External Clock Can Be Synchronized to other Switching Regulators High Gain SHDN Pin Accepts Slowly Varying Input Signals 14-Pin 4mm × 3mm DFN and 16-Lead MSE Packages The LT®3581 is a PWM DC/DC converter with built-in fault protection features to aid in protecting against output shorts, input/output overvoltages, and overtemperature conditions. The part consists of a 42V master switch, and a 42V slave switch that can be tied together for a total current limit of 3.3A. The LT3581 is ideal for many local power supply designs. It can be easily configured in Boost, SEPIC, Inverting or Flyback configurations, and is capable of generating 12V at 830mA, or –12V at 625mA from a 5V input. In addition, the LT3581’s slave switch allows the part to be configured in high voltage, high power charge pump topologies that are very efficient and require fewer components than traditional circuits. The LT3581’s switching frequency range can be set between 200kHz and 2.5MHz. The part may be clocked internally at a frequency set by the resistor from the RT pin to ground, or it may be synchronized to an external clock. A buffered version of the clock signal is driven out of the CLKOUT pin, and may be used to synchronize other compatible switching regulator ICs to the LT3581. Applications n n n n Local Power Supply Vacuum Fluorescent Display (VFD) Bias Supplies TFT-LCD Bias Supplies Automotive Engine Control Unit (ECU) Power The LT3581 also features innovative SHDN pin circuitry that allows for slowly varying input signals and an adjustable undervoltage lockout function. Additional features such as frequency foldback and soft-start are integrated. The LT3581 is available in 14-Pin 4mm × 3mm DFN and 16-Lead MSE packages. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7579816. Typical Application Efficiency and Power Loss vs Load Current Output Short Protected, 5V to 12V Boost Converter Operating at 2MHz 1.5µH 18.7k 4.7µF 10k 43.2k 100k FB VIN FAULT GATE SHDN CLKOUT RT LT3581 SYNC VC SS GND 6.04k 130k 56pF 0.1µF EFFICIENCY (%) 4.7µF SW1 SW2 VOUT 12V 830mA VIN 4.7µF 10.5k 1nF 2000 95 1800 90 1600 85 1400 80 1200 75 1000 70 800 65 600 60 400 55 200 50 3581 TA01 0 200 600 800 400 LOAD CURRENT (mA) POWER LOSS (mW) VIN 5V 100 0 1000 3581 TA01b 3581f LT3581 Absolute Maximum Ratings (Note 1) VIN Voltage.................................................. –0.3V to 40V SW1/SW2 Voltage ..................................... –0.4V to 42V RT Voltage.................................................... –0.3V to 5V SS, FB Voltage........................................... –0.3V to 2.5V VC Voltage..................................................... –0.3V to 2V SHDN Voltage............................................. –0.3V to 40V SYNC Voltage............................................. –0.3V to 5.5V GATE Voltage.............................................. –0.3V to 80V FAULT Voltage............................................. –0.3V to 40V FAULT Current......................................................±500µA CLKOUT Voltage........................................... –0.3V to 3V CLKOUT Current.......................................................1mA Operating Junction Temperature Range LT3581E (Notes 2, 4).......................... –40°C to 125°C LT3581I (Notes 2, 4)........................... –40°C to 125°C Storage Temperature Range................... –65°C to 150°C Pin Configuration TOP VIEW FB 1 14 SYNC VC 2 13 SS GATE 3 12 RT FAULT 4 15 GND TOP VIEW FB VC GATE FAULT VIN SW1 SW1 SW1 11 SHDN 10 CLKOUT VIN 5 SW1 6 9 SW2 SW1 7 8 SW2 DE14 PACKAGE 14-PIN (4mm s 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 43°C/W, θJC = 4.3°C/W EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB 1 2 3 4 5 6 7 8 17 GND 16 15 14 13 12 11 10 9 SYNC SS RT SHDN CLKOUT SW2 SW2 SW2 MSE PACKAGE 16-LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 45°C/W, θJC = 10°C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3581EDE#PBF LT3581EDE#TRPBF 3581 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3581IDE#PBF LT3581IDE#TRPBF 3581 14-Lead (4mm × 3mm) Plastic DFN –40°C to 125°C LT3581EMSE#PBF LT3581EMSE#TRPBF 3581 16-Lead Plastic MSOP –40°C to 125°C LT3581IMSE#PBF LT3581IMSE#TRPBF 3581 16-Lead Plastic MSOP –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3581f LT3581 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2). PARAMETER CONDITIONS Minimum Input Voltage MIN TYP MAX 2.3 2.5 V 22.1 23.5 25 V V l VIN Overvoltage Lockout UNITS Positive Feedback Voltage l 1.195 1.215 1.230 Negative Feedback Voltage l 3 9 16 mV µA Positive FB Pin Bias Current VFB = Positive Feedback Voltage, Current into Pin l 81 83.3 85 Negative FB Pin Bias Current VFB = Negative Feedback Voltage, Current out of Pin l 81 83.3 85.5 Error Amp Transconductance ΔI = 10μA Error Amp Voltage Gain µA 270 µmhos 70 V/V Quiescent Current Not Switching Quiescent Current in Shutdown VSHDN = 0V Reference Line Regulation 2.5V ≤ VIN ≤ 20V 0.01 0.05 %/V Switching Frequency, fOSC RT = 34k l 2.25 2.5 2.75 MHz RT = 432k l 180 200 220 kHz Switching Frequency in Foldback Compared to Normal fOSC Switching Frequency Range Free-Running or Synchronizing 2.3 mA 0 1 µA 1/6 l 200 SYNC High Level for Synchronization l 1.3 SYNC Low Level for Synchronization l SYNC Clock Pulse Duty Cycle 1.9 VSYNC = 0V to 2V ratio 2500 kHz V 20 0.4 V 80 % Recommended Minimum SYNC Ratio fSYNC/fOSC 3/4 Minimum Off-Time 45 ns Minimum On-Time 55 ns SW1 Current Limit At All Duty Cycles l 1.9 Current Sharing (SW2/SW1) 2.4 3 78 3.3 4.3 A % 5.4 A SW1 + SW2 Current Limit At All Duty Cycles, SW2/SW1 = 78% (Note 3) Switch VCESAT SW1 & SW2 Tied Together, ISW1 + ISW2 = 2.75A 250 SW1 Leakage Current VSW1 = 5V 0.01 1 µA SW2 Leakage Current VSW2 = 5V 0.01 1 µA l mV 3581f LT3581 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 5V, VSHDN = VIN, VFAULT = VIN, unless otherwise noted. (Note 2). PARAMETER CONDITIONS MIN TYP MAX UNITS Soft-Start Charge Current VSS = 30mV, Current Flows Out of SS pin l 5.7 8.7 11.3 µA Soft-Start Discharge Current Part in FAULT, VSS = 2.1V, Current Flows into SS Pin l 5.7 8.7 11.3 µA Soft-Start High Detection Voltage Part in FAULT l 1.65 1.8 1.95 V Soft-Start Low Detection Voltage Part Exiting FAULT l 30 50 85 SHDN Minimum Input Voltage High Active Mode, SHDN Rising Active Mode, SHDN Falling l l 1.27 1.24 1.33 1.3 1.41 1.38 SHDN Input Voltage Low Shutdown Mode l 0.3 V SHDN Pin Bias Current VSHDN = 3V VSHDN = 1.3V VSHDN = 0V 9.7 40 11.4 0 60 13.4 0.1 µA µA µA CLKOUT Output Voltage High CCLKOUT = 50pF 1.9 2.1 2.3 V CLKOUT Output Voltage Low CCLKOUT = 50pF 5 200 mV CLKOUT Duty Cycle TJ = 25°C 42 % CLKOUT Rise Time CCLKOUT = 50pF 12 ns CLKOUT Fall Time CCLKOUT = 50pF 8 ns GATE Pull Down Current VGATE = 3V VGATE = 80V GATE Leakage Current VGATE = 50V, GATE Off FAULT Output Voltage Low 100μA into FAULT Pin FAULT Leakage Current VFAULT = 40V, FAULT Off l l 800 800 l mV V V 933 933 1100 1100 µA µA 0.01 1 µA 150 300 mV 0.01 1 µA FAULT Input Voltage Low l 700 750 800 mV FAULT Input Voltage High l 950 1000 1050 mV Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3581E is guaranteed to meet performance specifications from 0°C to 125°C. Specifications over the –40°C to 125°C junction temperature range are assured by design, characterization and correlation with statistical process controls. Note 3: Current limit guaranteed by design and/or correlation to static test. Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation over the specified maximum operating junction temperature may impair device reliability. 3581f LT3581 Typical Performance Characteristics Switch Fault Current Limit vs Duty Cycle Switch Saturation Voltage with SW1 and SW2 Tied Together 4 3 2 1 450 100 400 90 350 300 250 200 150 100 50 0 20 60 50 40 DUTY CYCLE (%) 30 70 0 80 0 1 2 3 4 SW1 + SW2 CURRENT (A) 3581 G01 Switch Fault Current Limit vs Temperature 80 70 60 50 40 30 20 10 0 5 0 1 2 3 4 SW1 + SW2 CURRENT (A) 3581 G02 Positive Feedback Voltage vs Temperature 5 3581 G03 CLKOUT Duty Cycle vs Temperature 1.2200 6 80 70 5 4 3 2 1.2175 60 CLKOUT DC (%) POSITIVE FB VOLTAGE (V) SW1 + SW2 FAULT CURRENT LIMIT (A) Current Sharing Between SW1 and SW2 When Tied Together CURRENT SHARING = SW2/SW1 (%) 5 SATURATION VOLTAGE (mV) SW1 + SW2 FAULT CURRENT LIMIT (A) 6 1.2150 50 40 30 1.2125 1 20 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 1.2100 –50 –25 0 Oscillator Frequency 3581 G06 Frequency Foldback Gate Current vs Gate Voltage 1000 RT = 34k 2400 2000 1600 1200 800 400 RT = 432k 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G07 900 –40°C 800 GATE CURRENT (µA) SWITCHING FREQUENCY RATIO (fSW/fOSC) 1 2800 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G05 3200 0 –50 –25 10 –75 –50 –25 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G04 FREQUENCY (kHz) TA = 25°C, unless otherwise noted. 1/2 1/3 1/4 1/5 1/6 0 25°C 700 125°C 600 500 400 300 200 INVERTING CONFIGURATIONS 0 0.2 BOOSTING CONFIGURATIONS 0.4 0.6 0.8 FB VOLTAGE (V) 1.0 100 1.2 3581 G08 0 0 20 40 60 GATE VOLTAGE (V) 80 3581 G09 3581f LT3581 Typical Performance Characteristics TA = 25°C, unless otherwise noted. Commanded Current Limit vs SS Voltage Gate Current vs SS Voltage SHDN Voltage Threshold with Hysteresis 1.40 5 1000 1.38 900 700 600 500 400 300 200 4 1.36 SHDN VOLTAGE (V) SW1 + SW2 CURRENT (A) GATE CURRENT (µA) 800 3 2 SHDN FALLING 1.28 1.26 0 1.20 –50 –25 1.22 0.25 0.50 0.75 1.00 SS VOLTAGE (V) 1.25 1.50 0 0.2 0.4 0.6 0.8 SS VOLTAGE (V) 25°C SHDN PIN CURRENT (µA) 24 20 16 12 8 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G12 SHDN Pin Current 250 125°C 4 1.2 3580 G11 SHDN Pin Current 28 1.0 Internal UVLO 2.40 –40°C 2.38 200 2.36 25°C VIN VOLTAGE (V) 0 32 SHDN PIN CURRENT (µA) 1.30 1.24 3581 G10 0 1.32 1 100 0 SHDN RISING 1.34 150 125°C 100 50 2.34 2.32 2.30 2.28 2.26 2.24 2.22 –40°C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 SHDN VOLTAGE (V) 0 5 10 15 20 25 30 SHDN VOLTAGE (V) 35 2.20 –50 –25 40 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G14 3581 G15 3581 G13 CLKOUT Rise Time at 1MHz 50 30 CLKOUT RISE TIME 26 30 25 20 15 CLKOUT FALL TIME 10 24 22 20 0 50 100 150 200 CLKOUT CAPACITIVE LOAD (pF) 250 3581 G16 16 –50 –25 0.75 FAULT FALLING 0.50 0.25 18 5 FAULT RISING 1.00 FAULT VOLTAGE (V) 35 0 1.25 28 40 VIN VOLTAGE (V) CLKOUT RISE OR FALL TIME (ns) 45 FAULT Input Voltage Threshold with Hysteresis VIN OVLO 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G17 0 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3581 G18 3581f LT3581 Pin Functions (DFN/MSOP) FB (Pin 1/Pin 1): Positive and Negative Feedback Pin. For a Boost or Inverting Converter, tie a resistor from the FB pin to VOUT according to the following equations: – 1.215V V RFB = OUT ; Boost or SEPIC Converter 83.3 • 10 –6 | V | + 9mV RFB = OUT ; Inverting Converter 83.3 • 10 –6 VC (Pin 2/Pin 2): Error Amplifier Output Pin. Tie external compensation network to this pin. GATE (Pin 3/Pin 3): PMOS Gate Drive Pin. The GATE pin is a pull-down current source, used to drive the gate of an external PMOS for output short circuit protection or output disconnect. The GATE pin current increases linearly with the SS pin’s voltage, with a maximum pull-down current of 933µA at SS voltages exceeding 500mV. Note that if the SS voltage is greater than 500mV and the GATE pin voltage is less than 2V, then the GATE pin looks like a 2kΩ impedance to ground. See the Appendix for more information. FAULT (Pin 4/Pin 4): Fault Indication Pin. This active low, bidirectional pin can either be pulled low (below 750mV) by an external source, or internally by the chip to indicate a fault. When pulled low, this pin causes the power switches to turn off, the GATE pin to become high impedance, the CLKOUT pin to become disabled, and the SS pin to go through a charge/discharge sequence. The end/absence of a fault is indicated when the voltage on this pin exceeds 1V. A pull-up resistor or current source is needed on this pin to pull it above 1V in the absence of a fault. VIN (Pin 5/Pin 5): Input Supply Pin. Must be locally bypassed. SW1 (Pins 6, 7/Pins 6,7, 8): Master Switch Pin. This is the collector of the internal master NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. CLKOUT (Pin 10/Pin 12): Clock Output Pin. Use this pin to synchronize one or more other compatible switching regulator ICs to the LT3581. The clock that this pin outputs runs at the same frequency as the internal oscillator of the part or as the SYNC pin. CLKOUT may also be used as a temperature monitor since the CLKOUT pin’s duty cycle varies linearly with the part’s junction temperature. Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF. SHDN (Pin 11/Pin 13): Shutdown Pin. In conjunction with the UVLO (undervoltage lockout) circuit, this pin is used to enable/disable the chip and restart the soft-start sequence. Drive below 300mV to disable the chip. Drive above 1.33V (typical) to activate the chip and restart the soft-start sequence. Do not float this pin. RT (Pin 12/Pin 14): Timing Resistor Pin. Adjusts the LT3581’s switching frequency. Place a resistor from this pin to ground to set the frequency to a fixed free running level. Do not float this pin. SS (Pin 13/Pin 15): Soft-Start Pin. Place a soft-start capacitor here. Upon start-up, the SS pin will be charged by a (nominally) 250k resistor to about 2.1V. During a fault, the SS pin will be slowly charged up and eventually discharged as part of a timeout sequence (see the State Diagram for more information on the SS pin’s role during a fault event). SYNC (Pin 14/Pin 16): To synchronize the switching frequency to an outside clock, simply drive this pin with a clock. The high voltage level of the clock must exceed 1.3V, and the low level must be less than 0.4V. Drive this pin to less than 0.4V to revert to the internal free running clock. See the Applications Information section for more information. GND (Exposed Pad Pin 15/Exposed Pad Pin 17): Ground. Exposed pad must be soldered directly to local ground plane. SW2 (Pins 8, 9/Pins 9, 10, 11): Slave Switch Pin. This is the collector of the internal slave NPN power switch. Minimize the metal trace area connected to this pin to minimize EMI. 3581f LT3581 Block Diagram VIN CIN OPTIONAL D1 L1 M1 COUT1 RFAULT DIE TEMP 165°C 2.1V + – – + 1.8V 250k 750mV STARTUP AND FAULT LOGIC LDO SS VIN ** + – ** + – + – + – VC 22V MIN – + 933µA 50mV RGATE FAULT GATE SOFTSTART VOUT COUT2 + – DRIVER DISABLE CSS SW1 42V MIN SAMPLE MODE BLOCK SW2 42V MIN + – ISW1 FB 1.9A MIN TD ~ 30ns SAMPLE SHDN 1.33V + – + – + – SW2 45mV VBE • 0.9 RFB Q2 SW1 COMPARATOR SR1 – UVLO VIN 1.17V R A3 A3 1.215V REFERENCE + S Q1 Q + + 14.6k ∑ A1 – FB A4 FREQUENCY FOLDBACK A2 RS 20mΩ – RAMP GENERATOR + 14.6k 27mΩ DRIVER GND ÷N ADJUSTABLE OSCILLATOR – SS SYNC BLOCK VC SYNC RT CLKOUT RC CC RT 3581 BD **SW OVERVOLTAGE PROTECTION IS NOT GUARANTEED TO PROTECT THE LT3581 DURING SW OVERVOLTAGE EVENTS Figure 1. Block Diagram 3581f LT3581 State Diagram SHDN < 1.33V (TYPICAL) or VIN < 2.3V (TYPICAL) CHIP OFF • ALL SWITCHES DISABLED • IGATE OFF • FAULTS CLEARED SHDN > 1.33V (TYPICAL) AND VIN > 2.3V (TYPICAL) INITIALIZE • SS PULLED LOW FAULT1 FAULT2 FAULT DETECTED SS < 50mV SOFT START • IGATE ENABLED • SS CHARGES UP • SWITCHER ENABLED FAULT1 • SS CHARGES UP • IGATE OFF • FAULT PIN PULLED LOW INTERNALLY BY LT3581 • SWITCHER DISABLED • CLKOUT DISABLED SS > 1.8V AND NO FAULT1 CONDITIONS STILL DETECTED POST FAULT DELAY • SS SLOWLY DISCHARGES SAMPLE MODE • Q1 & Q2 SWITCHES FORCED ON EVERY CYCLE FOR AT LEAST MINIMUM ON TIME • IGATE FULLY ACTIVATED WHEN SS > 500mV FAULT1 FAULT1 SS < 50mV LOCAL FAULT OVER IF |VOUT| DROPS CAUSING: FB < 1.17V (BOOST) OR FB > 45mV (INVERTING) • INTERNAL FAULT PIN PULLDOWN RELEASED BY LT3581 • SS CONTINUES DISCHARGING TO GND NORMAL MODE • NORMAL OPERATION • CLKOUT ENABLED WHEN SS > 1.8V FAULT1 = OVER VOLTAGE PROTECTION ON VIN (VIN > 22V MIN) OVER TEMPERATURE (TJUNCTION > 165°C) OVER CURRENT ON SW1 (ISW1 > 1.9A MIN) OVER VOLTAGE PROTECTION ON SW1 (VSW1 > 42V MIN) OVER VOLTAGE PROTECTION ON SW2 (VSW2 > 42V MIN) FAULT1 FAULT PIN > 1.0V FAULT1 FAULT2 = FAULT PULLED LOW EXTERNALLY (FAULT < 0.75V) 3581 SD Figure 2. State Diagram 3581f LT3581 Operation Operation – Overview The LT3581 uses a constant-frequency, current mode control scheme to provide excellent line and load regulation. The part’s undervoltage lockout (UVLO) function, together with soft-start and frequency foldback, offers a controlled means of starting up. Fault features are incorporated in the LT3581 to aid in the detection of output shorts, over-voltage, and overtemperature conditions. Refer to the Block Diagram (Figure 1) and the State Diagram (Figure 2) for the following description of the part’s operation. Operation – Start-Up Several functions are provided to enable a very clean start-up for the LT3581: Precise Turn-On Voltage The SHDN pin is compared to an internal voltage reference to give a precise turn on voltage level. Taking the SHDN pin above 1.33V (typical) enables the part. Taking the SHDN pin below 300mV shuts down the chip, resulting in extremely low quiescent current. The SHDN pin has 30mV of hysteresis to protect against glitches and slow ramping. Undervoltage Lockout (UVLO) The SHDN pin can also be used to create a configurable UVLO. The UVLO function sets the turn on/off of the LT3581 at a desired input voltage (VINUVLO). Figure 3 shows how a resistor divider (or single resistor) from VIN to the SHDN pin can be used to set VINUVLO. RUVLO2 is optional. It may be left out, in which case set it to infinite in the equation below. For increased accuracy, set RUVLO2 ≤ 10k. Pick RUVLO1 as follows: RUVLO1 = VINUVLO – 1.33V 1.33V R + 11.6µA UVLO2 VIN VIN 1.33V RUVLO1 SHDN – ACTIVE/ LOCKOUT + 11.6µA AT 1.33V RUVLO2 (OPTIONAL) GND 3581 F03 Figure 3. Configurable UVLO The LT3581 also has internal UVLO circuitry that disables the chip when VIN < 2.3V (typical). Soft-Start of Switch Current The soft-start circuitry provides for a gradual ramp-up of the switch current (refer to Commanded Current Limit vs SS Voltage in Typical Performance Characteristics). When the part is brought out of shutdown, the external SS capacitor is first discharged which resets the states of the logic circuits in the chip. Then an integrated 250k resistor pulls the SS pin to ~1.8V. The ramp rate of the SS pin voltage is set by this 250k resistor and the external capacitor connected to this pin. Once SS gets to 1.8V, the CLKOUT pin is enabled, and an internal regulator pulls the pin up quickly to ~2.1V. Typical values for the external soft-start capacitor range from 100nF to 1μF. Soft-Start of External PMOS (if used) The soft-start circuitry also gradually ramps up the GATE pin pull-down current which allows an external PMOS to slowly turn on (M1 in Block Diagram). The GATE pin current increases linearly with the SS voltage, with a maximum current of 933µA when the SS voltage gets above 500mV. Note that if the GATE pin voltage is less than 2V for SS voltages exceeding 500mV, then the GATE pin impedance to ground is 2kΩ. The soft turn on of the external PMOS helps limit inrush current at start-up, making hot-plugs of LT3581s feasible and safe. 3581f 10 LT3581 Operation Sample Mode Sample Mode is the mechanism used by the LT3581 to aid in the detection of output shorts. It refers to a state of the LT3581 where the master and slave power switches (Q1 and Q2) are turned on for a minimum period of time every clock cycle (or every few clock cycles in frequency foldback) in order to “sample” the inductor current. If the sampled current through Q1 exceeds the master switch current limit of 1.9A (min), the LT3581 triggers an overcurrent fault internally (see Operation-Fault section for details). Sample Mode is active when FB is out of regulation by more than approximately 3.7% (45mV < FB < 1.17V). Frequency Foldback The frequency foldback circuit reduces the switching frequency when 350mV < FB < 900mV (typical). This feature lowers the minimum duty cycle that the part can achieve, thus allowing better control of the inductor current during start-up. When the FB voltage is pulled outside of this range, the switching frequency returns to normal. Note that the peak inductor current at start-up is a function of many variables including load profile, output capacitance, target VOUT, VIN, switching frequency, etc. Test each and every application’s performance at start-up to ensure that the peak inductor current does not exceed the minimum fault current limit. Operation – Regulation The following description of the LT3581’s operation assumes that the FB voltage is close enough to its regulation target so that the part is not in sample mode. Use the Block Diagram as a reference when stepping through the following description of the LT3581 operating in regulation. At the start of each oscillator cycle, the SR latch (SR1) is set, which turns on the power switches Q1 and Q2. The collector current through the master switch, Q1, is ~1.3 times the collector current through the slave switch, Q2, when the collectors of the two switches are tied together. Q1’s emitter current flows through a current sense resistor (RS) generating a voltage proportional to the total switch current. This voltage (amplified by A4) is added to a stabilizing ramp and the resulting sum is fed into the positive terminal of the PWM comparator A3. When the voltage on the positive input of A3 exceeds the voltage on the negative input, the SR latch is reset, turning off the master and slave power switches. The voltage on the negative input of A3 (VC pin) is set by A1 (or A2), which is simply an amplified difference between the FB pin voltage and the reference voltage (1.215V if the LT3581 is configured as a boost converter, or 9mV if configured as an inverting converter). In this manner, the error amplifier sets the correct peak current level to maintain output regulation. As long as the part is not in fault (see Operation – Fault section) and the SS pin exceeds 1.8V, the LT3581 drives its CLKOUT pin at the frequency set by the RT pin or the SYNC pin. The CLKOUT pin can be used to synchronize other compatible switching regulator ICs (including additional LT3581s) with the LT3581. Additionally, CLKOUT’s duty cycle varies linearly with the part’s junction temperature, and may be used as a temperature monitor. Operation – Fault The LT3581’s FAULT pin is an active low, bidirectional pin that is pulled low to indicate a fault. Each of the following events can trigger a fault in the LT3581: A.FAULT1 events: 1.SW Overcurrent: a. ISW1 > 1.9A (minimum) b.(ISW1 + ISW2) > 3.3A (minimum) 2.VIN Voltage > 22V (minimum) 3.SW1 Voltage and/or SW2 Voltage > 42V (minimum) 4.Die Temperature > 165°C B.FAULT2 events: 1.Pulling the FAULT pin low externally 3581f 11 LT3581 Operation Refer to the State Diagram (Figure 2) for the following description of the LT3581’s operation during a fault event. When a fault is detected, in addition to the FAULT pin being pulled low internally, the LT3581 also disables its CLKOUT pin, turns off its power switches, and the GATE pin becomes high impedance. The external PMOS, M1, turns off when the gate of M1 is pulled up to its source by the external RGATE resistor (see Block Diagram). With the external PMOS turned off, the power path from VIN to VOUT is cut off, protecting power components downstream. At the same time, a timeout sequence commences where the SS pin is charged up to 1.8V (the SS pin will continue charging up to 2.1V and be held there in the case of a FAULT1 event that has still not ended), and then discharged to 50mV. This timeout period relieves the part, the PMOS, and other downstream power components from electrical and thermal stress for a minimum amount of time as set by the voltage ramp rate on the SS pin. In the absence of faults, the FAULT pin is pulled high by the external RFAULT resistor (typically 100k). Figure 4 shows the events that accompany the detection of an output short on the LT3581. VOUT 10V/DIV VFAULT 5V/DIV VCLKOUT 2V/DIV IL 2A/DIV 5µs/DIV 3581 F04 Figure 4. Output Short Circuit Protection of the LT3581 3581f 12 LT3581 Applications Information Boost Converter Component Selection D1 20V, 2A L1 1.5µH VIN 5V CIN 4.7µF RFAULT 100k RT 43.2k VIN FB LT3581 FAULT GATE SHDN CLKOUT RT VC SYNC SS GND PARAMETERS/EQUATIONS OPTIONAL PMOS COUT1 4.7µF SW1 SW2 Table 1. Boost Design Equations RGATE 6.04k VOUT 12V IOUT < 0.83A Step 1: Pick VIN, VOUT, and fOSC to calculate equations below. Inputs Step 2: DC RFB 130k COUT2 4.7µF CF 56pF CSS 0.1µF L TYP = RC 10.5k CC 1nF 3581 F05 Table 1 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a boost converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 1. Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current RDSON_PMOS = RDSON of External PMOS (set to 0 if not using PMOS) VOUT – VIN + 0.5V VOUT + 0.5V – 0.3V ( VIN – 0.3V ) • DC (1) fOSC • 1A ( VIN – 0.3V ) • (2 • DC – 1) 2.2A • fOSC • (1 – DC) ( V – 0.3V ) • DC = IN LMIN = Step 3: L1 Figure 5. Boost Converter – The Component Values and Voltages Given Are Typical Values for a 2MHz, 5V to 12V Boost The LT3581 can be configured as a Boost converter as in Figure 5. This topology allows for positive output voltages that are higher than the input voltage. An external PMOS (optional) driven by the GATE pin of the LT3581 can achieve input or output disconnect during a fault event. A single feedback resistor sets the output voltage. For output voltages higher than 40V, see the Charge Pump Aided Regulators section. DC ≅ LMAX (2) (3) fOSC • 0.35A • Pick L1 out of a range of inductor values where the minimum value of the range is set by LTYP or LMIN, whichever is higher. The maximum value of the range is set by LMAX. See appendix on how to choose current rating for inductor value chosen. Step 4: IRIPPLE IRIPPLE = ( VIN – 0.3V ) • DC fOSC • L1 Step 5: IOUT I IOUT = 3.3A – RIPPLE • (1 – DC) 2 Step 6: D1 VR > VOUT ; IAVG > IOUT COUT1 = COUT2 ≥ Step 7: COUT1, COUT2 Step 8: CIN IOUT • DC fOSC 0.01 • VOUT – 0.50 • IOUT • RDSON _ PMOS • If PMOS is not used, then use just one capacitor where COUT = COUT1 + COUT2. CIN ≥ C VIN + CPWR ≥ 3.3A • DC IRIPPLE + 45 • fOSC • 0.005 • VIN 8 • fOSC • 0.005 • VIN • Refer to Input Capacitor Selection in Appendix for definition of CVIN and CPWR. Step 9: RFB Step 10: RT RFB = RT = VOUT – 1.215V 83.3µA 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Only needed for input or output disconnect. See PMOS Selection Step 11: in the Appendix for information on sizing the PMOS, RGATE and PMOS picking appropriae UVLO components. Note 1: The maximum design target for peak switch current is 3.3A and is used in this table. Note 2: The final values for COUT1, COUT2 and CIN may deviate from the above equations in order to obtain desired load transient performance. 3581f 13 LT3581 Applications Information SEPIC Converter Component Selection (Coupled or Un-Coupled Inductors) C1 1µF L1 3.3µH CIN 22µF RFAULT 100k ENABLE RT 124k SW1 SW2 VIN • L2 3.3µH PARAMETERS/EQUATIONS Step 1: Inputs D1 30V, 2A • VIN 3V TO 16V Table 2. SEPIC Design Equations COUT 22µF s2 RFB 45.3k VOUT 5V IOUT < 0.9A (VIN = 3V) IOUT < 1.5A (VIN = 12V) Step 2: DC FB GATE SHDN CLKOUT RT VC SYNC SS GND DC ≅ L TYP = LT3581 FAULT Pick VIN, VOUT, and fOSC to calculate equations below. CSS 1µF RC 7.87k CC 2.2nF ( VIN – 0.3V ) • DC fOSC • 1A ( VIN – 0.3V ) • (2 • DC – 1) 2.2A • fOSC • (1 – DC) ( V – 0.3V ) • DC = IN LMIN = CF 100pF 3581 F06 Step 3: L The LT3581 can also be configured as a SEPIC as shown in Figure 6. This topology allows for positive output voltages that are lower, equal, or higher than the input voltage. Output disconnect is inherently built into the SEPIC topology, meaning no DC path exists between the input and output due to capacitor C1. This implies that a PMOS controlled by the GATE pin is not required in the power path. Table 2 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a SEPIC converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 2. LMAX fOSC • 0.35A (1) (2) (3) • Pick L out of a range of inductor values where the minimum value of the range is set by LTYP or LMIN, whichever is higher. The maximum value of the range is set by LMAX. See Appendix on how to choose current rating for inductor value chosen. • Pick L1 = L2 = L for coupled inductors. • Pick L1L2 = L for un-coupled inductors. Figure 6. SEPIC Converter – The Component Values and Voltages Given Are Typical Values for a 700kHz, Wide Input Range (3V to 16V) SEPIC Converter with 5V Out Step 4: IRIPPLE IRIPPLE = ( VIN – 0.3V ) • DC fOSC • L • L = L1 = L2 for coupled inductors. • L = L1L2 for un-coupled inductors. Step 5: IOUT I IOUT = 3.3A – RIPPLE • (1 – DC) 2 Step 6: D1 VR > VIN + VOUT ; IAVG > IOUT Step 7: C1 C1 ≥ 1µF; VRATING ≥ VIN Step 8: COUT Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current VOUT + 0.5V VIN + VOUT + 0.5V – 0.3V Step 9: CIN COUT ≥ IOUT • DC fOSC • 0.005 • VOUT CIN ≥ C VIN + CPWR ≥ 3.3A • DC IRIPPLE + 45 • fOSC • 0.005 • VIN 8 • fOSC • 0.005 • VIN • Refer to Input Capacitor Selection in Appendix for definition of CVIN and CPWR. Step 10: RFB Step 11: RT RFB = RT = VOUT – 1.215V 83.3µA 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Note 1: The maximum design target for peak switch current is 3.3A and is used in this table. Note 2: The final values for COUT, CIN and C1 may deviate from the above equations in order to obtain desired load transient performance. 3581f 14 LT3581 Applications Information Dual Inductor Inverting Converter Component Selection (Coupled or Un-Coupled Inductors) C1 1µF L1 3.3µH RFAULT 100k ENABLE RT 43.2k VOUT –12V IOUT < 625mA • CIN 3.3µF VIN COUT 4.7µF D1 20V 1A SW1 SW2 PARAMETERS/EQUATIONS Step 1: Inputs Pick VIN, VOUT, and fOSC to calculate equations below. L2 3.3µH • VIN 5V Table 3. Dual Inductor Inverting Design Equations Step 2: DC RFB 143k L TYP = FB LT3581 FAULT GATE SHDN CLKOUT RT VC SYNC SS GND DC ≅ | VOUT | + 0.5V VIN + | VOUT | +0.5V – 0.3V ( VIN – 0.3V ) • DC (1) fOSC • 1A ( VIN – 0.3V ) • (2 • DC – 1) 2.2A • fOSC • (1 – DC) ( V – 0.3V ) • DC = IN LMIN = CSS 100nF RC 11k CC 1nF CF 47pF Step 3: L Figure 7. Dual Inductor Inverting Converter – The Component Values and Voltages Given Are Typical Values for a 2MHz, 5V to –12V Inverting Topology Using Coupled Inductors Table 3 is a step-by-step set of equations to calculate component values for the LT3581 when operating as a dual inductor inverting converter. Input parameters are input and output voltage, and switching frequency (VIN , VOUT and fOSC respectively). Refer to the Appendix for further information on the design equations presented in Table 3. IRIPPLE = Step 4: IRIPPLE ( VIN – 0.3V ) • DC fOSC • L • L = L1 = L2 for coupled inductors. • L = L1L2 for un-coupled inductors. Step 5: IOUT I IOUT = 3.3A – RIPPLE • (1 – DC) 2 Step 6: D1 VR > VIN + | VOUT | ; IAVG > IOUT Step 7: C1 C1 ≥ 1µF; VRATING ≥ VIN + | VOUT | Step 8: COUT COUT ≥ IRIPPLE 8 • fOSC ( 0.005 • | VOUT |) CIN ≥ C VIN + CPWR ≥ Step 9: CIN Variable Definitions: VIN = Input Voltage VOUT = Output Voltage DC = Power Switch Duty Cycle fOSC = Switching Frequency IOUT = Maximum Average Output Current IRIPPLE = Inductor Ripple Current (3) fOSC • 0.35A • Pick L out of a range of inductor values where the minimum value of the range is set by LTYP or LMIN, whichever is higher. The maximum value of the range is set by LMAX. See Appendix on how to choose current rating for inductor value chosen. • Pick L1 = L2 = L for coupled inductors. • Pick L1L2 = L for un-coupled inductors. 3581 F07 Due to its unique FB pin, the LT3581 can work in a Dual Inductor Inverting configuration as in Figure 7. Changing the connections of L2 and the Schottky diode in the SEPIC topology results in generating negative output voltages. This solution results in very low output voltage ripple due to inductor L2 being in series with the output. Output disconnect is inherently built into this topology due to the capacitor C1. LMAX (2) 3.3A • DC IRIPPLE + 45 • fOSC • 0.005 • VIN 8 • fOSC • 0.005 • VIN • Refer to Input Capacitor Selection in Appendix for definition of CVIN and CPWR. RFB = Step 10: RFB Step 11: RT RT = | VOUT | + 5mV 83.3µA 87.6 – 1; fOSC in MHz and R T in kΩ fOSC Note 1: The maximum design target for peak switch current is 3.3A and is used in this table. Note 2: The final values for COUT, CIN and C1 may deviate from the above equations in order to obtain desired load transient performance. 3581f 15 LT3581 Applications Information Layout Guidelines for Boost, SEPIC, and Dual Inductor Inverting Topologies General Layout Guidelines • To optimize thermal performance, solder the exposed ground pad of the LT3581 to the ground plane, with multiple vias around the pad connecting to additional ground planes. • A ground plane should be used under the switcher circuitry to prevent interplane coupling and overall noise. • High speed switching path (see specific topology for more information) must be kept as short as possible. • The VC , FB, and RT components should be placed as close to the LT3581 as possible, while being as far away as practically possible from the switch node. The ground for these components should be separated from the switch current path. • Place the bypass capacitor for the VIN pin as close as possible to the LT3581. • Place the bypass capacitor for the inductor as close as possible to the inductor. • The load should connect directly to the positive and negative terminals of the output capacitor for best load regulation. Boost Topology Specific Layout Guidelines • Keep length of loop (high speed switching path) governing switch, diode D1, output capacitor COUT1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. SEPIC Topology Specific Layout Guidelines • Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, output capacitor COUT, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. Inverting Topology Specific Layout Guidelines • Keep ground return path from the cathode of D1 (to chip) separated from output capacitor COUT’s ground return path (to chip) in order to minimize switching noise coupling into the output. • Keep length of loop (high speed switching path) governing switch, flying capacitor C1, diode D1, and ground return as short as possible to minimize parasitic inductive spikes at the switch node during switching. GND GND 2 CIN A – VIN + 17 15 3 14 4 13 SHDN 5 12 CLKOUT 6 11 7 10 8 L1 SYNC 16 9 B COUT1 M1 D1 A – VIN + 16 2 15 17 SYNC 3 14 4 13 SHDN 5 12 CLKOUT 6 11 7 10 8 9 B – L2 L1 C1 D1 COUT VOUT + • D2 – VOUT + COUT CIN 1 • 1 RGATE 3581 F09 3581 F08 A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT AND COUT1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT AND COUT1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. A: RETURN CIN AND L2 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN AND L2 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT GROUNDS DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE. Figure 8. Suggested Component Placement for Boost Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance Figure 9. Suggested Component Placement for SEPIC Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance 3581f 16 LT3581 Applications Information GND 1 CIN A – VIN + SYNC 16 2 15 17 3 14 4 13 SHDN 5 12 CLKOUT 6 11 7 10 8 9 B GND C C1 COUT L1 • • D1 – VOUT L2 3581 F10 A: RETURN CIN GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE CIN GROUND WITH GND EXCEPT AT THE EXPOSED PAD. B: RETURN COUT GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE COUT GROUND WITH GND EXCEPT AT THE EXPOSED PAD. C: RETURN D1 GROUND DIRECTLY TO LT3581 EXPOSED PAD PIN 17. IT IS ADVISED TO NOT COMBINE D1 GROUND WITH GND EXCEPT AT THE EXPOSED PAD. L1, L2: MOST COUPLED INDUCTOR MANUFACTURERS USE CROSS PINOUT FOR IMPROVED PERFORMANCE. Figure 10. Suggested Component Placement for Dual Inductor Inverting Topology (MSOP Shown, DFN Similar, Not to Scale.) Pin 15 on DFN or Pin 17 on MSOP Is the Exposed Pad Which Must Be Soldered Directly to the Local Ground Plane for Adequate Thermal Performance. Multiple Vias to Additional Ground Planes Will Improve Thermal Performance the heat generated within the package. This can be accomplished by taking advantage of the thermal pad on the underside of the IC. It is recommended that multiple vias in the printed circuit board be used to conduct heat away from the IC and into a copper plane with as much area as possible. Power and Thermal Calculations Power dissipation in the LT3581 chip comes from four primary sources: switch I2R losses, switch dynamic losses, NPN base drive DC losses, and miscellaneous input current losses. These formulas assume continuous mode operation, so they should not be used for calculating thermal losses or efficiency in discontinuous mode or at light load currents. The following example calculates the power dissipation in the LT3581 for a particular boost application (VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz, VD = 0.45V, VCESAT = 0.21V). Thermal Considerations To calculate die junction temperature, use the appropriate thermal resistance number and add in worst-case ambient temperature: Overview TJ = TA + θJA • PTOTAL For the LT3581 to deliver its full output power, it is imp erative that a good thermal path be provided to dissipate Table 4. Power Calculations Example for Boost Converter with VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz, VD = 0.45V, VCESAT = 0.21V DEFINITION OF VARIABLES DC = SWITCH DUTY CYCLE IIN = Average Switch Current η = Power Conversion Efficiency (typically 88% at high currents) EQUATIONS DC = VOUT – VIN + VD VOUT + VD – VCESAT IIN = VOUT • IOUT VIN • η DESIGN EXAMPLE DC = 12V – 5V + 0.45V 12V + 0.45V – 0.21V 12V • 0.83A 5V • 0.88 IIN = 2.3A IIN = PSWDC = Switch I2R Loss (DC) RSW = Switch Resistance (typically 90mΩ combined SW1 and SW2) PSWDC = DC • IIN2 • RSW PSWDC = 0.609 • (2.3A)2 • 90mΩ PSWAC = Switch Dynamic Loss (AC) PSWAC = 13ns • IIN • VOUT • fOSC PSWAC = (13ns ) • 2.3A • 12V • ( 2MHz ) PBDC = Base Drive Loss (DC) PINP = Input Power Loss PBDC = VIN • IIN • DC 45 PINP = 9mA • VIN VALUE DC = 60.9% PBDC = 5V • 2.3A • 0.609 45 PINP = 9mA • 5V PSWDC = 290mW PSWAC = 718mW PBDC = 156mW PINP = 45mW PTOTAL = 1.209W 3581f 17 LT3581 Applications Information where TJ = Die Junction Temperature, TA = Ambient Temperature, PTOTAL is the final result from the calculations shown in Table 4, and θJA is the thermal resistance from the silicon junction to the ambient air. The published (http://www.linear.com/designtools/packaging/Linear_Technology_Thermal_Resistance_Table.pdf) θJA value is 43°C/W for the 4mm × 3mm 14-pin DFN package and 45°C/W for the 16-lead MSOP package. In practice, lower θJA values are realizable if board layout is performed with appropriate grounding (accounting for heat sinking properties of the board) and other considerations listed in the Layout Guidelines section. For instance, a θJA value of ~24°C/W was consistently achieved for both MSE and DFN packages of the LT3581 (at VIN = 5V, VOUT = 12V, IOUT = 0.83A, fOSC = 2MHz) when board layout was optimized as per the suggestions in the Board Layout Guidelines section. Junction Temperature Measurement The duty cycle of the CLKOUT signal is linearly proportional to die junction temperature, TJ. To get a temperature reading, measure the duty cycle of the CLKOUT signal and use the following equation to approximate the junction temperature: TJ = DCCLKOUT – 35% 0.3% where DCCLKOUT is the CLKOUT duty cycle in % and TJ is the die junction temperature in °C. Although the actual die temperature can deviate from the above equation by ±15°C, the relationship between change in CLKOUT duty cycle and change in die temperature is well defined. Basically a 1% change in CLKOUT duty cycle corresponds to a 3.33°C change in die temperature. Note that the CLKOUT pin is only meant to drive capacitive loads up to 50pF. Thermal Lockout A fault condition occurs when the die temperature exceeds 165°C (see Operation Section), and the part goes into thermal lockout. The fault condition ceases when the die temperature drops by ~5°C (nominal). Switching Frequency There are several considerations in selecting the operating frequency of the converter. The first is staying clear of sensitive frequency bands, which cannot tolerate any spectral noise. For example, in products incorporating RF communications, the 455kHz IF frequency is sensitive to any noise, therefore switching above 600kHz is desired. Some communications have sensitivity to 1.1MHz and in that case a 1.5MHz switching converter frequency may be employed. The second consideration is the physical size of the converter. As the operating frequency goes up, the inductor and filter capacitors go down in value and size. The tradeoff is efficiency, since the losses due to switching dynamics (see Thermal Considerations), Schottky diode charge, and other capacitive loss terms increase proportionally with frequency. Oscillator Timing Resistor (RT) The operating frequency of the LT3581 can be set by the internal free-running oscillator. When the SYNC pin is driven low (< 0.4V), the frequency of operation is set by a resistor from the RT pin to ground. An internally trimmed timing capacitor resides inside the IC. The oscillator frequency is calculated using the following formula: fOSC = 87.6 RT + 1 where fOSC is in MHz and RT is in k. Conversely, RT (in k) can be calculated from the desired frequency (in MHz) using: RT = 87.6 –1 fOSC 3581f 18 LT3581 Applications Information Clock Synchronization The operating frequency of the LT3581 can be set by an external source by simply providing a digital clock signal into the SYNC pin (RT resistor still required). The LT3581 will revert to its internal free-running oscillator clock (set by the RT resistor) when the SYNC pin is driven below 0.4V for a few free-running clock periods. Driving SYNC high for an extended period of time effectively stops the operating clock and prevents latch SR1 from becoming set (see Block Diagram). As a result, the switching operation of the LT3581 will stop and the CLKOUT pin will be held at ground. The duty cycle of the SYNC signal must be between 20% and 80% for proper operation. Also, the frequency of the SYNC signal must meet the following two criteria: (1) SYNC may not toggle outside the frequency range of 200kHz to 2.5MHz unless it is stopped low (below 0.4V) to enable the free-running oscillator. (2) The SYNC frequency can always be higher than the free-running oscillator frequency (as set by the RT resistor), fOSC , but should not be less than 25% below fOSC. Clock Synchronization of Additional Regulators The CLKOUT pin of the LT3581 can be used to synchronize one or more other compatible switching regulator ICs as shown in Figure 11. The frequency of the master LT3581 is set by the external RT resistor. The SYNC pin of the slave LT3581 is driven by the CLKOUT pin of the master LT3581. Note that the RT pin of the slave LT3581 must have a resistor tied to ground. It takes a few clock cycles for the CLKOUT signal to begin oscillating, and it’s preferable for all LT3581s to have the same internal free-running frequency. Therefore, in general, use the same value RT resistor for all of the synchronized LT3581s. 2.2µF 1.5µH VOUT –12V 450mA 143k 4.7µF SW1 GATE SW2 FB VIN CLKOUT LT3581 VC SHDN SLAVE SS FAULT RT SYNC GND 0.1µF 100pF 10k 2.2nF 43.2k 1.5µH VIN 5V 6.8µF 6.8µF 10k GATE 4.7µF ENABLE 43.2k LT3581 MASTER FB FAULT VC SHDN SS RT 130k SW1 SW2 CLKOUT VIN 100k VOUT 12V 830mA SYNC GND 0.1µF 10.5k 1nF 56pF 3581 F11 Figure 11. A Single Inductor Inverting Topology Is Synchronized with a Boost Regulator to Generate –12V and 12V Outputs. The External PMOS Helps Disconnect the Input from the Power Paths During Fault Events Also, the FAULT pins can be tied together so that a fault condition from one LT3581 causes all of the LT3581s to enter fault, until the fault condition disappears. Charge Pump Aided Regulators Designing charge pumps with the LT3581 can offer efficient solutions with fewer components than traditional circuits because of the master/slave switch configuration on the IC. Although the slave switch, SW2, operates in phase with the master switch, SW1, it is only the current through the master switch (SW1) that is sensed by the current comparator (A4 in Block Diagram) as part of the current feedback loop. This method of operation by the master/slave switches can offer the following benefits to charge pump designs: 3581f 19 LT3581 Applications Information • The slave switch, by not performing a current sense operation like the master switch, can sustain fairly large current spikes when the flying capacitors charge up. Since this current spike flows through SW2, it does not affect the operation of the current comparator (A4 in Block Diagram). • The master switch, immune from the capacitor current spike (seen only by the slave switch) can sense the inductor current more accurately. • Since the slave switch can sustain large current spikes, the diodes that feed current into the flying capacitors do not need current limiting resistors, leading to efficiency and thermal improvements. 2.2µF VIN 12V 10µH 2.2µF 2.2µF SW1 SW2 100k FB FAULT GATE SHDN CLKOUT RT 43.2k 8.06k VIN 370k 2.2µF VC LT3581 SYNC SS GND 24k 100pF 1nF 0.47µF 3581 F12 Figure 12. High VOUT Charge Pump Topology Can Be Used to Build VFD Bias Supplies D1 L1 VIN C1 D3 D2 CIN SW1 GATE Single Inductor Inverting Topology If there is a need to use just one inductor to generate a negative output voltage whose magnitude is greater than VIN , the single inductor inverting topology (shown in Figure 13) can be used. Since the master and slave switches are isolated by a Schottky diode, the current spike through C1 will flow only through the slave switch, thereby preventing the current comparator, (A4 in the Block Diagram), from falsely tripping. Output disconnect is inherently built into the single inductor topology. 2.2µF VOUT1 65V 70mA 2.2µF High VOUT Charge Pump Topology The LT3581 can be used in a charge-pump topology as shown in Figure 12, multiplying the output of an inductive boost converter. The master switch (SW1) can be used to drive the inductive boost converter (first stage of charge pump), while the slave switch (SW2) can be used to drive one or more other charge pump stages. This topology is useful for high voltage applications including VFD bias supplies. 2.2µF VOUT2 97V 140mA VIN 100k ENABLE SW2 COUT RFB FB CLKOUT LT3581 FAULT VC SHDN SS RT VOUT < 0V AND |VOUT| > |VIN| SYNC GND CSS RVC CVC2 CVC1 RT 3579 F13 Figure 13. Single Inductor Inverting Topology 3581f 20 LT3581 Applications Information Hot-Plug The high inrush current associated with hot-plugging VIN can be largely rejected with the use of an external PMOS. A simple hot-plug controller can be designed by connecting an external PMOS in series with VIN, with the gate of the PMOS being driven by the GATE pin of the LT3581. Since the GATE pin pull-down current is linearly proportional to the SS voltage, and the SS charge up time is relatively slow, the GATE pin pull-down current will increase gradually, thereby turning on the external PMOS slowly. Controlled in this manner, the PMOS acts as an input current limiter when VIN hot-plugs or ramps up sharply. Likewise, when the PMOS is connected in series with the output, inrush currents into the output capacitor can be limited during a hot-plug event. To illustrate this, the circuit in Figure 18 was re-configured by adding a large 1500µF capacitor to the output. An 18Ω resistive load was used and a 2.2µF capacitor was placed on SS. Figure 14 shows the results of hot-plugging this re-configured circuit. Notice how the inductor current is well behaved. VIN 5V/DIV VOUT 10V/DIV IL 5A/DIV SS 1V/DIV 1s/DIV 3581 F14 Figure 14. Inrush Current Is Well Controlled in Spite Of HotPlugging the Re-configured Boost Converter in Figure 18 3581f 21 LT3581 Appendix Setting the Output Voltage The output voltage is set by connecting a resistor (RFB) from VOUT to the FB pin. RFB is determined by using the following equation: RFB = | VOUT – VFB | 83.3µA where VFB is 1.215V (typical) for non-inverting topologies (i.e. boost and SEPIC regulators) and 5mV (typical) for inverting topologies. Power Switch Duty Cycle In order to maintain loop stability and deliver adequate current to the load, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “on” for 100% of each clock cycle. The maximum allowable duty cycle is given by: DCMAX = ( TP – MinOffTime) • 100% TP where TP is the clock period and MinOffTime (found in the Electrical Characteristics) is typically 60ns. Conversely, the power NPNs (Q1 and Q2 in the Block Diagram) cannot remain “off” for 100% of each clock cycle, and will turn on for a minimum on time (MinOnTime) when in regulation. This MinOnTime governs the minimum allowable duty cycle given by: DCMIN = (MinOnTime) • 100% TP Where TP is the clock period and MinOnTime (found in the Electrical Characteristics) is typically 100ns. The application should be designed such that the operating duty cycle is between DCMIN and DCMAX. Duty cycle equations for several common topologies are given below where VD is the diode forward voltage drop and VCESAT is the collector to emitter saturation voltage of the switch. VCESAT, with SW1 and SW2 tied together, is typically 250mV when the combined switch current (ISW1 + ISW2) is 2.75A. For the boost topology (see Figure 5): DCBOOST ≅ For the SEPIC or Dual Inductor Inverting topology (see Figures 6 and 7): DCSEPIC _&_ INVERT ≅ VD + | VOUT | VIN + | VOUT | + VD − VCESAT For the Single Inductor Inverting topology (see Figure 13): DCSI _ INVERT = | VOUT | − VIN + VCESAT + 3 • VD | VOUT | + 3 • VD The LT3581 can be used in configurations where the duty cycle is higher than DCMAX , but it must be operated in the discontinuous conduction mode so that the effective duty cycle is reduced. Inductor Selection General Guidelines: The high frequency operation of the LT3581 allows for the use of small surface mount inductors. For high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. Also to improve efficiency, choose inductors with more volume for a given inductance. The inductor should have low DCR (copper-wire resistance) to reduce I2R losses, and must be able to handle the peak inductor current without saturating. Note that in some applications, the current handling requirements of the inductor can be lower, such as in the SEPIC topology where each inductor only carries one half of the total switch current. Molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2A to 6A range. To minimize radiated noise, use a toroidal or shielded inductor. See Table 5 for a list of inductor manufacturers. Table 5. Inductor Manufacturers Sumida CDR6D28MN and CDR7D28MN Series www.sumida.com Coilcraft MSD7342 Series www.coilcraft.com Vishay IHLP-1616BZ-01, IHLP-2020BZ-01 and IHLP-2525CZ-01 Series www.vishay.com Taiyo Yuden NR Series www.t-yuden.com Wurth WE-PD Series www.we-online.com TDK VLF, SLF and RLF Series www.tdk.com VOUT – VIN + VD VOUT + VD – VCESAT 3581f 22 LT3581 appendix Minimum Inductance Although there can be a tradeoff with efficiency, it is often desirable to minimize board space by choosing smaller inductors. When choosing an inductor, there are three conditions that limit the minimum inductance: (1) providing adequate load current, (2) avoidance of subharmonic oscillations and (3) supplying a minimum ripple current to avoid false tripping of the current comparator. Adequate Load Current Small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to the load. In order to provide adequate load current, L should be at least: LBOOST > DC • ( VIN − VCESAT ) | V |• I 2 • fOSC • IPK − OUT OUT V •η IN Boost Topology or LDUAL > DC • ( VIN − VCESAT ) | V |• I 2• fOSC• IPK − OUT OUT − IOUT VIN • η SEPIC or Inverting Topologies where: LBOOST = L1 for Boost Topologies (see Figure 5) LDUAL = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 6 and 7) LDUAL = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 6 and 7) DC = Switch Duty Cycle (see Power Switch Duty Cycle section in Appendix) IPK = Maximum Peak Switch Current; should not exceed 3.3A for a combined SW1 + SW2 current, or 1.9A of SW1 current if SW1 is being used by itself. η = Power Conversion Efficiency (typically 88% for Boost and 75% for Dual Inductor Topologies at High Currents) fOSC = Switching Frequency IOUT = Maximum Output Current Negative values of LBOOST or LDUAL indicate that the output load current, IOUT, exceeds the switch current limit capability of the LT3581. Avoiding Sub-Harmonic Oscillations The LT3581’s internal slope compensation circuit will prevent sub-harmonic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a certain minimum value. In applications that operate with duty cycles greater than 50%, the inductance must be at least: LMIN = ( VIN − VCESAT ) • (2 • DC − 1) where: 2.2A • fOSC • (1− DC) LMIN = L1 for Boost Topologies (see Figure 5) LMIN = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 6 and 7) LMIN = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 6 and 7) Maximum Inductance Excessive inductance can reduce ripple current to levels that are difficult for the current comparator (A4 in the Block Diagram) to cleanly discriminate, causing duty cycle jitter and/or poor regulation. The maximum inductance can be calculated by: LMAX = VIN − VCESAT DC • 350mA fOSC where: LMAX = L1 for Boost Topologies (see Figure 5) LMAX = L1 = L2 for Coupled Dual Inductor Topologies (see Figures 6 and 7) LMAX = L1 || L2 for Uncoupled Dual Inductor Topologies (see Figures 6 and 7) 3581f 23 LT3581 appendix Inductor Current Rating Inductors must have a rating greater than their peak operating current, or else they could saturate and hence contribute to losses in efficiency. The maximum inductor current (considering start-up and steady-state conditions) is given by: IL _ PEAK = ILIM + where: VIN • TMIN _ PROP L IL_PEAK = Peak Inductor Current in L1 for a Boost Topology, or the Peak of the sum of the Inductor Currents in L1 and L2 for Dual Inductor Topologies. = 3.3A with SW1 and SW2 Tied Together, ILIM** or 1.9A with just SW1 (This assumes usage of an inductor whose core material soft-saturates such as powdered iron core). TMIN_PROP= 100ns (Propagation Delay through the Current Feedback Loop). **If using an inductor whose core material saturates hard (e.g., ferrite), then pick ILIM to be 5.4A with SW1 and SW2 tied together, or 3A when just SW1 is used. Note that these equations offer conservative results for the required inductor current ratings. The current ratings could be lower for applications with light loads, if the SS capacitor is sized appropriately to limit inductor currents at start-up. Diode Selection Schottky diodes, with their low forward voltage drops and fast switching speeds, are recommended for use with the LT3581. Choose a Schottky diode with low parasitic capacitance to reduce reverse current spikes through the power switch of the LT3581. The Central Semiconductor Corp. CMMSH2-40 diode is a very good choice with a 40V reverse voltage rating and an average forward current of 2A. Output Capacitor Selection Low ESR (equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. Multilayer ceramic capacitors are an excellent choice, as they have extremely low ESR and are available in very small packages. X5R or X7R dielectrics are preferred, as these materials retain their capacitance over wide voltage and temperature ranges. A 10μF to 22μF output capacitor is sufficient for most applications, but systems with very low output currents may need only 2.2μF to 10μF. Always use a capacitor with a sufficient voltage rating. Many ceramic capacitors, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. Tantalum Polymer or OS-CON capacitors can be used, but it is likely that these capacitors will occupy more board area than a ceramic, and will have higher ESR with greater output ripple. Input Capacitor Selection Ceramic capacitors make a good choice for the input decoupling capacitor, and should be placed such that it is in close proximity to the VIN of the chip as well as to the inductor connected to the input of the power path. If it is not possible to optimally place a single input capacitor, then use two separate capacitors—use one at the VIN of the chip (see equation for CVIN in Tables 1, 2 and 3) and one at the input to the power path (see equation for CPWR in Tables 1, 2 and 3) A 4.7μF to 20μF input capacitor is sufficient for most applications. Table 6 shows a list of several ceramic capacitor man ufacturers. Consult the manufacturers for detailed infor mation on their entire selection of ceramic parts. Table 6: Ceramic Capacitor Manufacturers AVX www.avxcorp.com Murata www.murata.com Taiyo Yuden www.t-yuden.com PMOS Selection An external PMOS, controlled by the LT3581’s GATE pin, can be used to facilitate input or output disconnect. The GATE pin turns on the PMOS gradually during start-up (see Soft-Start of External PMOS in the Operation section), and turns the PMOS off when the LT3581 is in shutdown or in fault. 3581f 24 LT3581 appendix The use of the external PMOS, controlled by the GATE pin, is particularly beneficial when dealing with unintended output shorts in a boost regulator. In a conventional boost regulator, the inductor, Schottky diode, and power switches are susceptible to damage in the event of an output short to ground. Using an external PMOS in the boost regulator’s power path (path from VIN to VOUT) controlled by the GATE pin, will serve to disconnect the input from the output when the output has a short to ground, thereby helping save the IC, and the other components in the power path from damage. Ensure that both, the diode and the inductor can survive low duty cycle current pulses of 3 to 4 times their steady state levels. event of hard shorts. The resistor divider from VIN to the SHDN pin sets a UVLO of 4V for this application. The PMOS chosen must be capable of handling the maximum input or output current depending on whether the PMOS is used at the input (see Figure 11) or the output (see Figure 18). In contrast, an input connected PMOS works as a simple hot-plug controller (covered in more detail in the Hot-Plug section). The input connected PMOS also functions as an inexpensive means of protecting against multiple output shorts in boost applications that synchronize the LT3581 with other compatible ICs (see Figure 11). Ensure that the PMOS is biased with enough source to gate voltage (VSG) to enhance the device into the triode mode of operation. The higher the VSG voltage that biases the PMOS into triode, the lower the RDSON of the PMOS, thereby lowering power dissipation in the device during normal operation, as well as improving the efficiency of the application in which the PMOS is used. The following equations show the relationship between RGATE (see Block Diagram) and the desired VSG that the PMOS is biased with: RGATE if VGATE < 2V VIN VSG = RGATE + 2kΩ 933µA • R GATE if VGATE ≥ 2V When using a PMOS, it is advisable to configure the specific application for undervoltage lockout (see the Operations section). The goal is to have VIN get to a certain minimum voltage where the PMOS has sufficient headroom to attain a high enough VSG, which prevents it from entering the saturation mode of operation during start-up. Figure 18 shows the PMOS connected in series with the output to act as an output disconnect during a fault condition. The Schottky diode from the VIN pin to the GATE pin is optional and helps turn off the PMOS quicker in the Connecting the PMOS in series with the output offers certain advantages over connecting it in series with the input: • Since the load current is always less than the input current for a boost converter, the current rating of the PMOS goes down. • A PMOS in series with the output can be biased with a higher overdrive voltage than a PMOS used in series with the input, since VOUT > VIN. This higher overdrive results in a lower RDSON rating for the PMOS, thereby improving the efficiency of the regulator. Table 7 shows a list of several discrete PMOS manufa cturers. Consult the manufacturers for detailed information on their entire selection of PMOS devices. Table 7. Discrete PMOS Manufacturers Vishay www.vishay.com Fairchild Semiconductor www.fairchildsemi.com Compensation – Adjustment To compensate the feedback loop of the LT3581, a series resistor-capacitor network in parallel with an optional single capacitor should be connected from the VC pin to GND. For most applications, choose a series capacitor in the range of 1nF to 10nF with 2.2nF being a good starting value. The optional parallel capacitor should range in value from 47pF to 160pF with 100pF being a good starting value. The compensation resistor, RC , is usually in the range of 5k to 50k with 10k being a good starting value. A good technique to compensate a new application is to use a 100k potentiometer in place of the series resistor RC. With the series and parallel capacitors at 2.2nF and 100pF respectively, adjust the potentiometer while observing the transient response and the optimum value for RC can be 3581f 25 LT3581 appendix found. Figures 15a to 15c illustrate this process for the circuit of Figure 18 with a load current stepped between 540mA and 800mA. Figure 15a shows the transient response with RC equal to 1k. The phase margin is poor as evidenced by the excessive ringing in the output voltage and inductor current. In Figure 15b, the value of RC is increased to 3k, which results in a more damped response. Figure 15c shows the results when RC is increased further to 10.5k. The transient response is nicely damped and the compensation procedure is complete. VOUT AC-COUPLED 500mV/DIV IL 1A/DIV 50µs/DIV 3581 F15a Figure 15a. Transient Response Shows Excessive Ringing VOUT AC-COUPLED 500mV/DIV Compensation – Theory Like all other current mode switching regulators, the LT3581 needs to be compensated for stable and efficient operation. Two feedback loops are used in the LT3581: a fast current loop which does not require compensation, and a slower voltage loop which does. Standard Bode plot analysis can be used to understand and adjust the voltage feedback loop. As with any feedback loop, identifying the gain and phase contribution of the various elements in the loop is critical. Figure 16 shows the key equivalent elements of a boost converter. Because of the fast current control loop, the power stage of the IC, inductor and diode have been replaced by a combination of the equivalent transconductance amplifier gmp and the current controlled current source (which converts IVIN to ηVIN/VOUT • IVIN). gmp acts as a current source where the peak input current, IVIN, is proportional to the VC voltage. η is the efficiency of the switching regulator and is typically about 80%. Note that the maximum output currents of the gmp and gma stages are finite. The output of the gmp stage is limited by the minimum switch current limit (see Electrical Specifications) and the output of the gma stage is nominally limited to about ±12μA. – IL 1A/DIV + gmp IVIN VOUT H• VIN VOUT 50µs/DIV • IVIN RESR 3581 F15b COUT Figure 15b. Transient Response is Better + VC CF VOUT AC-COUPLED 500mV/DIV RL RC gma RO CC 1.215V REFERENCE CPL R1 R2 FB – R2 3581 F16 IL 1A/DIV 50µs/DIV 3581 F15c Figure 15c. Transient Response is Well Damped CC: COMPENSATION CAPACITOR COUT: OUTPUT CAPACITOR CPL: PHASE LEAD CAPACITOR CF: HIGH FREQUENCY FILTER CAPACITOR gma: TRANSCONDUCTOR AMPLIFIER INSIDE IC gmp: POWER STAGE TRANSCONDUCTANCE AMPLIFIER RC: COMPENSATION RESISTOR RL: OUTPUT RESISTANCE DEFINED AS VOUT/ILOAD(MAX) RO: OUTPUT RESISTANCE OF gma R1, R2; FEEDBACK RESISTOR DIVIDER NETWORK RESR: OUTPUT CAPACITOR ESR Figure 16. Boost Converter Equivalent Model 3581f 26 LT3581 appendix DC Gain : (Breaking loop at FB pin) ∂V ∂I ∂V ∂V ADC = A OL (0) = C • VIN • OUT • FB = ∂VFB ∂VC ∂IVIN ∂VOUT (gma • RO ) • gmp • η • VVIN • R2L • R 0+.50R.52R 1 2 OUT 2 Output Pole : P1 = 2 • π • RL • COUT Error Amp Pole : P2 = 1 2 • π • RO + RC • CC 1 Error Amp Zero : Z1 = 2 • π • RC • CC ESR Zero : Z2 = RHP Zero : Z3 = 1 2 • π • RESR • COUT VIN2 • RL 2 2 • π • VOUT • L High Frequency Pole : P3 > fS 3 P5 = C 1 , CF < C RC • R O 10 2• π • • CF RC + R O The current mode zero (Z3) is a right half plane zero which can be an issue in feedback control design, but is manageable with proper external component selection. Table 8. Bode Plot Parameters PARAMETER VALUE UNITS COMMENT RL 14.5 Ω Application Specific COUT 9.4 µF Application Specific 1 mΩ Application Specific RO 305 kΩ Not Adjustable CC 1000 pF Adjustable RESR CF 56 pF Optional/Adjustable CPL 0 pF Optional/Adjustable RC 10.5 kΩ Adjustable R1 130 kΩ Adjustable R2 14.6 kΩ Not Adjustable VREF 1.215 V Not Adjustable VOUT 12 V Application Specific VIN 5 V Application Specific gma 270 µmho Not Adjustable gmp 15.1 mho Not Adjustable L 1.5 µH Application Specific 2 MHz Adjustable fOSC From Figure 17, the phase is –130° when the gain reaches 0dB giving a phase margin of 50°. The crossover frequency is 17kHz, which is more than three times lower than the frequency of the RHP zero Z3 to achieve adequate phase margin. 170 0 –40 150 PHASE 130 –80 110 –120 90 –160 70 –180 50 –200 30 –240 GAIN 10 –280 –10 –30 PHASE (DEG) 1 2 • π • R1• CPL 1 Phase Lead Pole : P4 = R2 R1• 2 •C 2• π • R2 PL R1+ 2 Error Amp Filter Pole : Phase Lead Zero : Z 4 = Using the circuit in Figure 18 as an example, Table 8 shows the parameters used to generate the Bode plot shown in Figure 17. GAIN (dB) From Figure 16, the DC gain, poles and zeros can be calculated as follows: –320 10 100 1k 10k FREQUENCY (Hz) 100k 1M –360 3851 F17 Figure 17. Bode Plot for Example Boost Converter 3581f 27 LT3581 Typical Applications L1 1.5µH VIN 5V D1 SW1 SW2 18.7k FB VIN 100k C1 4.7µF FAULT GATE SHDN CLKOUT RT 10k LT3581 SYNC 43.2k VOUT 12V 830mA M1 C2 4.7µF 6.04k D2 130k VIN VC 56pF SS GND C3 4.7µF 10.5k 0.1µF 1nF 3581 F18 C1: 4.7µF, 16V, X7R, 1206 C2, C3: 4.7µF, 25V, X7R, 1206 D1: DIODES INC. PD3S230H-7 D2: VISHAY MSS2P3 L1: SUMIDA CDR6D28MN-IR5 M1: VISHAY SILICONIX SI7123DN Figure 18. 2MHz, 5V to 12V, 830mA Boost Converter with Output Short Circuit Protection Transient Response with 430mA to 830mA to 430mA Load Step Switching Waveforms with 830mA Load VOUT AC-COUPLED 200mV/DIV IL 1A/DIV VOUT AC-COUPLED 1V/DIV IL 1A/DIV VSW 0.5A/DIV LOAD 0.5A/DIV VCLKOUT (BW LIMIT) 2V/DIV 3581 TA02a 50µs/DIV 3581 TA02b 500ns/DIV 2MHz, 5V, 1.1A Boost Converter Operates from an Input Range of 2.8V to 4.2V L1 0.68µH VIN 2.8V TO 4.2V D1 Efficiency and Power Loss at VIN = 3.3V VOUT 5V 1.1A SW1 SW2 43.2k FAULT GATE SHDN CLKOUT RT VC SYNC SS GND 45.3k 68pF 0.1µF C2 22µF 6.98k 1.5nF 3581 TA03a C1: 3.3µF, 16V, X7R, 1206 C2: 22µF, 16V, X7R, 1210 D1: DIODES INC. PD3S230H-7 L1: VISHAY IHLP1616 BZ-01-OR68 (ONLY 4.1mm s 4.5mm s 2mm) 2000 85 1800 1600 80 1400 75 1200 70 1000 65 800 600 60 400 55 50 POWER LOSS (mW) 100k FB LT3581 EFFICIENCY (%) VIN C1 3.3µF 90 200 0 200 600 800 400 LOAD CURRENT (mA) 1000 0 1200 3581 TA03b 3581f 28 LT3581 Typical Applications High Efficiency, VFD (Vacuum Fluorescent Display) Power Supply Switches at 2MHz to Avoid AM Band DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY D6 C7 2.2µF D5 C5 2.2µF D4 C6 2.2µF D3 C4 2.2µF D2 D7 L1 10µH VIN 9V TO 16V C1 2.2µF 32.6k D1 FB 100k FAULT GATE SHDN CLKOUT RT 10k LT3581 SYNC 43.2k GND 365k 8.06k D9* 10V D8* VIN VC SS VOUT1 65V 60mA (VIN = 9V) 70mA (VIN = 12V) 90mA (VIN = 16V) M1* C2 2.2µF SW1 SW2 VIN VOUT2 97V 90mA (VIN = 9V) 140mA (VIN = 12V) 180mA (VIN = 16V) 100pF C3 2.2µF 24k 1nF 0.47µF 3581 TA04a C1: 2.2µF, 25V, X7R, 1206 C2 TO C7: 2.2µF, 50V, X7R, 1206 D1 TO D7: CENTRAL SEMI SOD123F D8: CENTRAL SEMI CMDSH-3TR D9: CENTRAL SEMI CMHZ5240B-LTZ L1: TAIYO YUDEN NR6045T100M M1: VISHAY SILICONIX SI7611DN *OPTIONAL, FOR OUTPUT SHORT-CIRCUIT PROTECTION Transient Response with 60mA to 140mA to 60mA Load Step on VOUT2 (VIN = 12V) VOUT AC-COUPLED 2V/DIV Start-Up Waveforms VOUT2 50V/DIV VOUT1 50V/DIV IL 0.5A/DIV IL 0.5A/DIV ILOAD 0.1A/DIV VSS 1V/DIV 3581 TA04b 100ms/DIV 3581 TA04c Efficiency and Power Loss at VIN = 12V 90 3.0 85 2.5 80 2.0 75 1.5 70 0 4 12 16 8 TOTAL OUTPUT POWER (W) 20 POWER LOSS (mW) EFFICIENCY (%) 100µs/DIV 1.0 3581 TA04d 3581f 29 LT3581 Typical Applications 2MHz, 12V SEPIC Converter Can Accept Input Voltages from 9V to 16V C2 2.2µF L1 3.3µH D1 VOUT 12V 1A (VIN = 9V) 1.1A (VIN = 12V) 1.3A (VIN = 16V) • VIN 9V TO 16V SW1 VIN C1 3.3µF 100k 43.2k • SW2 LT3581 L2 3.3µH FB SHDN GATE FAULT CLKOUT RT VC SYNC SS GND 130k C3 10µF 100pF 10k 0.1µF 2.2nF 3581 TA06a C1: 3.3µF, 25V, X7R, 1206 C2: 2.2µF, 50V, X7R, 1206 C3: 10µF, 25V, X7R, 1210 D1: CENTRAL SEMI CTLSH2-40M832 L1, L2: COILCRAFT MSD7342-332MLB Efficiency Line Regulation with No Load 100 12.000 LINE REGULATION ~0.0044%/V 95 11.998 VIN = 9V 85 VIN = 16V 80 75 VOUT (V) EFFICIENCY (%) 90 VIN = 12V 70 11.996 11.994 65 60 11.992 55 50 0 300 1200 600 900 LOAD CURRENT (mA) 11.990 1500 8 9 3581 TA06b 10 11 12 13 VIN (V) 14 15 16 17 3581 TA06c Load Regulation at VIN = 12 12.01 LOAD REGULATION ~0.25%/A VOUT (V) 12.00 11.99 11.98 11.97 11.96 0 200 400 600 800 1000 1200 1400 ILOAD (mA) 3581 TA06d 3581f 30 LT3581 Typical Applications Wide Input Range, 3.3V SEPIC Converter Can Operate from 3V to 36V D3 C4 2.2µF D2 VOUT 3.3V 0.9A (3V < VBAT < 9V) 1.5A (VBAT = 9V) • VBAT 3V TO 36V (VBAT AT START-UP = 6V TO 16V) L1 3.3µH C1 10µF 200k 10k SW1 M1 VIN 100k D1 18V C3 4.7µF C2 10nF 174k Q1 470pF SW2 LT3581 FB • 24.9k SHDN GATE FAULT VC RT SS 47pF CLKOUT GND 1µF SYNC L2 3.3µH C5 47µF s2 10k 2.2nF 10k 3581 TA07a C1: 10µF, 50V, X7R, 1210 C2: 10nF, 25V, X7R, 0603 C3: 4.7µF, 25V, X7R, 1206 C4: 2.2µF, 50V, X7R, 1206 C5: 47µF, 10V, X7R, 1210 D1: CENTRAL SEMI CMHZ5248B-LTZ Efficiency Wide Input Range SEPIC Can Ride Through VBAT Voltages that Are Higher than VIN_OVP 80 VBAT = 9V VBAT = 12V EFFICIENCY (%) 75 70 VBAT 10V/DIV VBAT = 3V VOUT 2V/DIV 65 60 VBAT = 17V VBAT = 31V VOUT = 3.3V IL 2A/DIV 55 50 D2: CENTRAL SEMI CMMSH2-40 D3: DIODES INC. PD3S230H-7 L1, L2: COILCRAFT MSD7342-332MLB M1: 2N7002 Q1: MMBT3904 1s/DIV 0 800 1200 400 LOAD CURRENT (mA) 3581 TA07c 1600 3581 TA07b 3581f 31 LT3581 Typical Applications 1MHz, ±12V Charge Pump Topology Uses Only Single Inductor D5 C5 10µF D4 L1 8.2µH D1 D3 R1 *2.4k VOUT+ 12V 0.27A D2 SW1 LT3581 VIN C1 3.3µF 100k 86.6k SW2 FB SHDN GATE FAULT CLKOUT RT VC SYNC SS GND 130k C4 10µF 100pF 1800 85 1600 1400 80 1200 75 1000 70 800 65 600 60 400 55 16.9k 0.1µF 90 50 2.2nF 200 0 50 3581 TA08a C1: 3.3µF, 25V, X7R, 1206 C2, C3: 1µF, 25V, X7R, 1206 C4, C5: 10µF, 50V, X7R, 1210 D1 TO D5: DIODES INC. PD3S230H-7 L1: VISHAY IHLP-2525CZ-01-8R2 R1: 2.4k, 2W POWER LOSS (mW) VIN 5V C2 1µF Efficiency and Power Loss with Symmetric Load VOUT– –12V 0.27A EFFICIENCY (%) C3 1µF 150 100 200 LOAD CURRENT (mA) 0 300 250 3581 TA08b *IF DRIVING ASYMMMETRICAL LOADS, PLACE A 2.4k, 2W RESISTOR FROM THE 12V OUTPUT TO THE –12V OUTPUT FOR IMPROVED LOAD REGULATION OF THE –12V OUTPUT 700kHz, –5V Inverting Converter Can Accept Input Voltages from 3V to 16V VOUT –5V 0.9A (VIN = 3.3V) 1.5A (VIN = 12V) 1.6A (VIN = 16V) • • VIN 3V TO 16V Efficiency L2 3.3µH D1 SW1 VIN C1 22µF 100k 124k SW2 LT3581 FB SHDN GATE FAULT CLKOUT RT VC SYNC SS GND 60.4k C3 22µF 56pF 0.1µF 6.19k 2.2nF 3581 TA09a C1: 22µF, 25V, X7R, 1210 C2: 1µF, 50V, X7R, 1206 C3: 22µF, 16V, X7R, 1210 D1: VISHAY SSB44 L1, L2: COILCRAFT MSD7342-332MLB 90 85 VIN = 12V VIN = 3.3V 80 EFFICIENCY (%) C2 1µF L1 3.3µH 75 VIN = 16V 70 65 60 55 50 0 300 600 900 1200 LOAD CURRENT (mA) 1500 1800 3581 TA09b 3581f 32 LT3581 Typical Applications 700kHz, 5V SEPIC Can Accept Input Voltages from 3V to 16V D1 SW1 VIN C1 22µF 100k 124k • SW2 LT3581 FB SHDN GATE FAULT CLKOUT RT VC SYNC SS GND L2 3.3µH 1µF C3 22µF s2 7.87k 2.2nF 3581 TA10a C1: 22µF, 25V, X7R, 1210 C2: 1µF, 50V, X7R, 1206 C3: 22µF, 16V, X7R, 1210 D1: DIODES INC. B230LA L1, L2: COILCRAFT MSD7342-332MLB 90 85 VIN = 12V VIN = 3.3V 80 45.3k 100pF Efficiency VOUT 5V 0.9A (VIN = 3V) 1.5A (12V ≤ VIN ≤ 16V) • VIN 3V TO 16V EFFICIENCY (%) C2 1µF L1 3.3µH 75 VIN = 16V 70 65 60 55 50 0 400 800 1200 LOAD CURRENT (mA) 1600 3581 TA10b 3581f 33 LT3581 Package Description MSE Package 16-Lead Plastic MSOP, Exposed Die Pad (Reference LTC DWG # 05-08-1667 Rev A) BOTTOM VIEW OF EXPOSED PAD OPTION 2.845 p 0.102 (.112 p .004) 5.23 (.206) MIN 2.845 p 0.102 (.112 p .004) 0.889 p 0.127 (.035 p .005) 8 1 1.651 p 0.102 (.065 p .004) 1.651 p 0.102 3.20 – 3.45 (.065 p .004) (.126 – .136) 0.305 p 0.038 (.0120 p .0015) TYP 16 0.50 (.0197) BSC 4.039 p 0.102 (.159 p .004) (NOTE 3) RECOMMENDED SOLDER PAD LAYOUT 0.254 (.010) 0.35 REF 0.12 REF DETAIL “B” CORNER TAIL IS PART OF DETAIL “B” THE LEADFRAME FEATURE. FOR REFERENCE ONLY 9 NO MEASUREMENT PURPOSE 0.280 p 0.076 (.011 p .003) REF 16151413121110 9 DETAIL “A” 0o – 6o TYP 3.00 p 0.102 (.118 p .004) (NOTE 4) 4.90 p 0.152 (.193 p .006) GAUGE PLANE 0.53 p 0.152 (.021 p .006) DETAIL “A” 1.10 (.043) MAX 0.18 (.007) SEATING PLANE 0.17 – 0.27 (.007 – .011) TYP 1234567 8 0.50 (.0197) BSC NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX 0.86 (.034) REF 0.1016 p 0.0508 (.004 p .002) MSOP (MSE16) 0608 REV A 3581f 34 LT3581 Package Description DE Package 14-Lead Plastic DFN (4mm × 3mm) (Reference LTC DWG # 05-08-1708 Rev B) 4.00 p0.10 (2 SIDES) R = 0.05 TYP 0.70 p0.05 3.60 p0.05 2.20 p0.05 3.30 p0.05 PACKAGE OUTLINE 0.25 p 0.05 0.50 BSC 1.70 p 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF (DE14) DFN 0806 REV B 7 0.75 p0.05 1 0.25 p 0.05 0.50 BSC 3.00 REF 3.00 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 0.40 p 0.10 14 3.30 p0.10 3.00 p0.10 (2 SIDES) 1.70 p 0.05 R = 0.115 TYP 8 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3581f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 35 LT3581 Typical Application 5V to –12V Inverting Converter Switches at 2MHz C2 1µF L1 3.3µH VOUT –12V 625mA • • VIN 5V Efficiency and Power Loss L2 3.3µH D1 SW1 SW2 100k 43.2k FB SHDN GATE FAULT CLKOUT RT 143k C3 4.7µF VC SYNC 85 1800 1600 80 47pF SS GND 0.1µF 11k EFFICIENCY (%) C1 3.3µF LT3581 2000 1400 75 1200 70 1000 65 800 600 60 400 55 1nF 3581 TA05a 50 POWER LOSS (mW) VIN 90 200 0 C1: 3.3µF, 16V, X7R, 1206 C2: 1µF, 25V, X7R, 1206 C3: 4.7µF, 25V, X7R, 1206 D1: DIODES INC. PD3S230H-7 L1, L2: COILCRAFT MSD7342-332MLB 125 375 500 250 LOAD CURRENT (mA) 0 625 3581 TA05b Related Parts PART NUMBER DESCRIPTION COMMENTS LT3580 2A (ISW), 2.5MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.5V to 32V, VOUT(MAX) = 42V, IQ = 1mA, ISD < 1µA, 3mm × 3mm DFN-8, MSOP-8E Packages LT3471 Dual Output 1.3A (ISW), 1.2MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.4V to 16V, VOUT(MAX) = ±40V, IQ = 2.5mA, ISD < 1µA, 3mm × 3mm DFN-10 Package LT3479 40V, 3A, Full Featured DC/DC Converter with Soft-Start and Inrush Current Protection VIN = 2.5V to 24V, VOUT(MAX) = 40V, IQ = Analog/PWM, ISD < 1µA, DFN, TSSOP Packages LT3477 40V, 3A, Full Featured DC/DC Converter VIN = 2.5V to 25V, VOUT(MAX) = 40V, IQ = Analog/PWM, ISD < 1µA, QFN, TSSOP-20E Packages LT1946/LT1946A 1.5A (ISW), 1.2MHz/2.7MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.6V to 16V, VOUT(MAX) = 34V, IQ = 3.2mA, ISD < 1µA, MS8E Package LT1935 2A (ISW), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1µA, ThinSOT Package LT1310 2A (ISW), 40V, 1.2MHz, High Efficiency Step-Up DC/DC Converter VIN = 2.3V to 16V, VOUT(MAX) = 40V, IQ = 3mA, ISD < 1µA, ThinSOT Package LT3436 3A (ISW), 800kHz, 34V Step-Up DC/DC Converter VIN = 3V to 25V, VOUT(MAX) = 34V, IQ = 0.9mA, ISD < 6µA, TSSOP-16E Package 3581f 36 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0310 • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2010