CY2DP818 1:8 Clock Fanout Buffer 1:8 Clock Fanout Buffer Features Description ■ Low-voltage operation VDD = 3.3 V The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. ■ 1:8 fanout ■ Operation to350 MHz ■ Single input configurable for LVDS, LVPECL, or LVTTL ■ 8 pair of LVPECL outputs ■ Drives a 50 ohm load ■ Low input capacitance ■ Low output skew ■ Low propagation delay (tpd = 4 ns, typical) ■ Commercial and Industrial temperature ranges ■ 38-pin TSSOP Package Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals. The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input. Logic Block Diagram Q1A Q1B Q2A Q2B Q3A Q3B INPUT (LVPECL / LVDS / LVTTL) Q4A INPUT A INPUT B Q4B Q5A InConfig Q5B Q6A Q6B Q7A Q7B Q8A Q8B OUTPUT (LVPECL) Cypress Semiconductor Corporation Document Number: 38-07061 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 20, 2012 CY2DP818 Contents Pin Configuration ............................................................. 3 Pin Description ................................................................. 3 Maximum Ratings ............................................................. 5 DC Electrical Specifications ............................................ 6 AC Switching Characteristics ......................................... 7 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Drawing and Dimensions ............................... 10 Document Number: 38-07061 Rev. *D Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Page 2 of 13 CY2DP818 Pin Configuration GND VDD VDD VDD VDD VDD InConfig VDD GND INPUT A INPUT B GND VDD VDD VDD VDD VDD GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CY2DP818 Figure 1. 38-pin TSSOP pinout 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 GND Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B VDD Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B GND Pin Description Pin Number 1, 9, 12, 18, 19, 20, 38 2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 10, 11 Pin Name 37, 36, 35, 34, 33, 32, 31, 30, 28, 27, 26, 25, 24, 23, 22, 21 Q1(A,B), Q2(A,B), Q3(A,B), Q4(A,B), Q5(A,B), Q6(A,B), Q7(A,B), Q8(A,B) InConfig 7 Type Description GND POWER Ground VDD POWER Power Supply Input A, Input B Default: LVPECL/LDVS Clock Input. Either differential LVPECL/LVDS or single-ended Optional: LVTTL/LVCMOS single pin LVTTL/LVCMOS, as determined by InConfig. See Table 1 and Table 2 for details. LVPECL Differential Output Clocks LVTTL/LVCMOS Document Number: 38-07061 Rev. *D Control Input. Selects input type: either differential LVPECL/LVDS or single-ended LVTTL/LVCMOS. See Table 1 and Table 2 for details. Page 3 of 13 CY2DP818 Table 1. Input Receiver Configuration for Differential or LVTTL/LVCMOS InConfig (Pin 7) Input Receiver Family Input Receiver Type 1 LVTTL or LVCMOS Single ended, non-inverting or inverting, void of bias resistors 0 LVDS or LVPECL Differential, void of internal termination Table 2. Single ended LVTTL/LVCMOS Input Logic (InConfig = 1) Input A (+) Pin 10 Input B (–) Pin 11 Output Clock QnA Pins Input Ground True Input VDD Invert Ground Input Invert VDD Input True Document Number: 38-07061 Rev. *D Page 4 of 13 CY2DP818 Maximum Ratings Exceeding maximum ratings [1] may shorten the useful life of the device. These user guidelines are not tested. Storage Temperature: .............................. –65 C to +150 C Ambient Temperature: ............................... –40 C to +85 C Supply Voltage to Ground Potential (Inputs and VDD only) ....................................–0.3 V to 4.6 V Supply Voltage to Ground Potential (Outputs only) ..................................... –0.3 V to VDD + 0.3 V DC Input Voltage ................................ –0.3 V to VDD + 0.3 V DC Output Voltage .............................. –0.3 V to VDD + 0.9 V Power Dissipation ...................................................... 0.75 W Table 3. Power Supply Characteristics Parameter Description Test Conditions Min Typ Max Unit ICC Dynamic Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs Open – 1.5 2.0 mA IC Total Power Supply Current VDD = Max Input toggling 50% Duty Cycle, Outputs 50 ohms fL = 100 MHz – – 350 mA IC(Core) Core current when output loads are disabled VDD = Max Input toggling 50% Duty Cycle, Outputs not connected to VTT fL = 100 MHz – – 50 mA Note 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Document Number: 38-07061 Rev. *D Page 5 of 13 CY2DP818 DC Electrical Specifications Table 4. LVDS Input, VDD = 3.3 V ± 5%, TA = 0C to 70 C or –40 C to 85 C Parameter Description Conditions VID Magnitude of Differential Input Voltage VIC Common-mode of Differential Input VoltageIVIDI (min and max) VIH Input High Voltage Guaranteed Logic High Level VIL Input Low Voltage IIH IIL Min Typ Max Unit 100 – 600 mV IVIDI/2 2.4–(IVIDI/2) V 2 – – V Guaranteed Logic Low Level – – 0.8 V Input High Current VDD = Max, VIN = VDD – ±10 ±20 A Input Low Current VDD = Max, VIN = VSS – ±10 ±20 A Min Typ Max Unit Table 5. LVPECL Input, VDD = 3.3 V ± 5%, TA = 0 C to 70 C or –40 C to 85 C Parameter Description Conditions VID Differential Input Voltage p-p Guaranteed Logic High Level 400 – 2600 mV VIH Input High Voltage Guaranteed Logic High Level 2.15 – 2.4 V VIL Input Low Voltage Guaranteed Logic Low Level 1.5 – 1.8 V IIH Input High Current VDD = Max, VIN = VDD – ±10 ±20 A IIL Input Low Current VDD = Max, VIN = VSS VCM Common-mode Voltage – ±10 ±20 A – – 225 mV Table 6. LVTTL/LVCMOS Input, VDD = 3.3 V ± 5%, TA = 0 C to 70 C or –40 C to 85 C Min Typ Max Unit VIH Parameter Input High Voltage Description Conditions 2 – – V VIL Input Low Voltage – – 0.8 V IIH Input High Current VDD = Max, VIN = 2.7 V – – 1 A IIL Input Low Current VDD = Max, VIN = 0.5 V – – –1 A II Input High Current VDD = Max, VIN = VDD(Max) – – 20 A VIK Clamp Diode Voltage VDD = Min, IIN = –18 mA – –0.7 –1.2 V VH Input Hysteresis – 80 – mV Document Number: 38-07061 Rev. *D Page 6 of 13 CY2DP818 Table 7. LVPECL Output, VDD = 3.3 V ± 5%, TA = 0 C to 70C or –40 C to 85 C Parameter Min Typ Max Unit Driver Differential Output voltage VDD = Min, VIN = VIH or VIL, p-p RL = 50 Driver common-mode p-p VDD = Min, VIN = VIH or VIL, RL = 50 1000 – 3600 mV – – 300 mV tR Rise Time – 1200 ps Fall Time Differential 20% to 80%, CL = 10 pF to GND, RL = 50 to GND 300 tF VOH Output High Voltage VDD = Min, VIN = VIH or VIL, IOH = –12 mA 2.1 – 3.0 V VOL[2] Output Low Voltage VDD = Min, VIN = VIH or VIL IOS Short Circuit Current VDD = Max, VOUT = GND VOD VOC Description Conditions 0.8 – 1.3 V –125 – –150 mA AC Switching Characteristics Table 8. VDD = 3.3 V ± 5%, TA = 0 C to 70 C or –40 C to 85 C Min Typ Max Unit tPLH Parameter Propagation Delay – Low to High VID = 100 mV Description Conditions 3 4 5 ns tPHL Propagation Delay – High to Low VID = 100 mV 3 4 5 ns tSK(0) Output Skew: Skew between outputs of the same package (in phase) – – 0.2 ns tSK(p) Pulse Skew: Skew between opposite transitions of the same output (tPHL–tPLH) – 0.2 – ns tSK(t) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Same input signal level and output load. – – 1 ns Min Typ Max Unit – – 350 MHz VID = 100 mV Table 9. High frequency Parametrics Parameter Fmax Description Maximum frequency VDD = 3.3 V Conditions 45%–55% duty cycle Standard load circuit Note 2. VOL levels are dependent on the termination voltage VTT and termination resistance RTT. Changing either of these values will affect VOL. Document Number: 38-07061 Rev. *D Page 7 of 13 CY2DP818 Figure 2. Driver Design Figure 3. Standard Termination A TPA 150 Pulse Generator B 50 10pF TPC VDD-2V 50 GND 150 TPB Figure 4. Differential Receiver to Driver Propagation Delay and Driver Transition Time[3,4,5,6] 1.4 V INPUT A INPUT B 1.0 V QnA QnB tPLH tPHL 80% 0V Differential 20% QnA - QnB tR tF Figure 5. Test Circuit and Voltage Definitions for the Driver Common Mode Output Voltage [3, 4, 5, 6] A TPA 150 Pulse Generator 50 TPC B 150 50 GND TPB VOC Standard Termination INPUT A 2.0V INPUT B 1.6V VOD Next Device Notes 3. All input pulses are supplied by a frequency generator with the following characteristics: tR and tF 1 ns; pulse rerate = 50 Mpps; pulse width = 10 0.2 ns. 4. RL = 50 ohm1%; Zline = 50 ohm 6”. 5. CL includes instrumentation and fixture capacitance within 6 mm of the UT. 6. TPA and B are used for prop delay and Rise/Fall measurements. TPC is used for VOC measurements only and is otherwise connected to VDD – 2V. Document Number: 38-07061 Rev. *D Page 8 of 13 CY2DP818 Ordering Information Part Number Package Type Product Flow Pb-free CY2DP818ZXI 38-pin TSSOP Industrial, –40 C to 85 C CY2DP818ZXC 38-pin TSSOP Commercial, 0 C to 70 C Ordering Code Definitions CY 2DP818 Z X X X X = blank or T blank = Bulk; T = Tape and Reel Temperature Range: X = I or C I = Industrial = –40 C to 85 C C = Commercial = 0 C to 70 C Pb-free Package Type: Z = 38-pin TSSOP Part Identifier Company ID : CY = Cypress Document Number: 38-07061 Rev. *D Page 9 of 13 CY2DP818 Package Drawing and Dimensions Figure 6. 38-pin TSSOP (9.7 × 4.4 × 1.1 mm) Z3817 / ZZ3817 Package Outline, 51-85151 51-85151 *C Document Number: 38-07061 Rev. *D Page 10 of 13 CY2DP818 Acronyms Acronym LVCMOS Document Conventions Description low-voltage complementary metal oxide semiconductor Units of Measure Symbol Unit of Measure °C degree Celsius MHz megahertz µA microampere LVDS low-voltage differential signaling LVPECL low-voltage pseudo (positive) emitter-coupled logic LVTTL low-voltage transistor-transistor logic mV millivolt thin shrink small outline package ns nanosecond ohm % percent TSSOP Document Number: 38-07061 Rev. *D pF picofarad ps picosecond V volt W watt Page 11 of 13 CY2DP818 Document History Page Document Title: CY2DP818, 1:8 Clock Fanout Buffer Document Number: 38-07061 Rev. ECN Orig. of Change Submission Date ** 107086 06/07/01 IKA Description of Change New Data Sheet *A 115913 07/11/02 CTK IC, VCM, VOC, Rise/Fall Time Fmax (20) *B 2748606 08/05/09 KVM Deleted references to ComLink Minor edits to page 1 text Instances of VCC changed to VDD Changed table sequence to be more logical Edited Table 1 on page 4 and reformatted Table 2 on page 4 for clarity Added voltage and temperature specs to heading of all DC and AC tables Added commercial temp range to DC and AC table headings Clarified wording for IC Core Removed duplicate II (input high current) parameter from LVPECL & LVDS Removed TPE and TPD parameters from AC table Cleaned up waveform drawings Removed figures showing inputs for different InConfig values because Table 1 on page 4 and Table 2 on page 4 are more complete Updated Ordering Information (Added part numbers CY2DP818ZXC, CY2DP818ZXCT, CY2DP818ZXI and CY2DP818ZXIT to the ordering information table). Updated Package Drawing and Dimensions. *C 2899846 KVM 03/26/10 Updated Ordering Information (Removed inactive parts in ordering information table). Updated Package Drawing and Dimensions. *D 3717888 PURU 08/20/2012 Document Number: 38-07061 Rev. *D Added Ordering Code Definitions. Updated Package Drawing and Dimensions (spec 51-85151 (Changed revision from *B to *C)). Added Acronyms and Units of Measure. Updated in new template. Page 12 of 13 CY2DP818 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07061 Rev. *D Revised August 20, 2012 Page 13 of 13 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.