CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Features Functional Description ■ Select one of two low-voltage positive emitter-coupled logic (LVPECL) input pairs to distribute to 10 LVPECL output pairs ■ 40-ps maximum output-to-output skew ■ 600-ps maximum propagation delay ■ 0.11-ps maximum additive RMS phase jitter at 156.25 MHz (12-kHz to 20-MHz offset) The CY2DP1510 is an ultra-low noise, low skew, low-propagation delay 1:10 LVPECL fanout buffer targeted to meet the requirements of high-speed clock distribution applications. The CY2DP1510 can select between two separate LVPECL input clock pairs using the IN_SEL pin. The device has a fully differential internal architecture that is optimized to achieve low additive jitter and low skew at operating frequencies of up to 1.5 GHz. ■ Up to 1.5-GHz operation ■ 32-Pin thin quad flat pack (TQFP) package ■ 2.5-V or 3.3-V operating voltage[1] ■ Commercial and industrial operating temperature range Logic Block Diagram VDD Q0 Q0# Q1 Q1# VDD VSS Q2 Q2# IN0 IN0# Q3 Q3# IN1 IN1# Q4 Q4# Q5 Q5# IN_SEL 100k Q6 Q6# VBB Q7 Q7# Q8 Q8# Q9 Q9# Note 1. Input AC-coupling capacitors are required for voltage-translation applications. Cypress Semiconductor Corporation Document Number: 001-55566 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 25, 2011 [+] Feedback CY2DP1510 Contents Pinouts .............................................................................. 3 Absolute Maximum Ratings ............................................ 4 Operating Conditions....................................................... 4 DC Electrical Specifications ............................................ 5 AC Electrical Specifications ............................................ 6 Ordering Information........................................................ 9 Ordering Code Definition............................................. 9 Package Dimension......................................................... 10 Acronyms ........................................................................ 11 Document Number: 001-55566 Rev. *G Document Conventions ................................................. Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 11 12 13 13 13 13 Page 2 of 13 [+] Feedback CY2DP1510 Pinouts Q3 Q3# Q4 Q4# Q5 Q5# Q6 Q6# Figure 1. Pin Diagram – 32-Pin TQFP Package 24 23 22 21 20 19 18 17 VDD 25 16 VDD Q2# 26 15 Q7 Q2 27 14 Q7# Q1# 28 13 Q8 CY2DP1510 Q0 31 10 Q9# VDD 32 9 VDD 1 2 3 4 5 6 7 8 VSS Q9 IN1# 11 IN1 30 VBB Q0# IN0# Q8# IN0 12 IN_SEL 29 VDD Q1 Table 1. Pin Definitions Pin No. Pin Name Pin Type Description 1, 9, 16, 25, 32 VDD Power Power supply 2 IN_SEL Input Input clock select pin. Low-voltage complementary metal oxide semiconductor (LVCMOS)/low-voltage transistor-transistor-logic (LVTTL). When IN_SEL = Low, the IN0/IN0# differential input pair is active When IN_SEL = High, the IN1/IN1# differential input pair is active 3 IN0 Input LVPECL input clock. Active when IN_SEL = Low 4 IN0# Input LVPECL complementary input clock. Active when IN_SEL = Low 5 VBB Output LVPECL reference voltage output 6 IN1 Input LVPECL input clock. Active when IN_SEL = High 7 IN1# Input LVPECL complementary input clock. Active when IN_SEL = High 8 VSS Power Ground 10,12,14,17,19,21, Q(0:9)# 23,26,28,30 Output LVPECL complementary output clocks 11,13,15,18,20,22, Q(0:9) 24,27,29,31 Output LVPECL output clocks – – Exposed paddle. Connect to ground plane for package heat dissipation. No electrical connection. EPAD Document Number: 001-55566 Rev. *G Page 3 of 13 [+] Feedback CY2DP1510 Absolute Maximum Ratings Parameter Description Condition Min Max Unit VDD Supply voltage Nonfunctional –0.5 4.6 V VIN[2] Input voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0 or VDD + 0.4 V VOUT[2] DC output or I/O voltage, relative to VSS Nonfunctional –0.5 lesser of 4.0 or VDD + 0.4 V TS Storage temperature Nonfunctional –55 150 °C ESDHBM Electrostatic discharge (ESD) protection (Human body model) JEDEC STD 22-A114-B 2000 – V LU Latch up UL–94 Flammability rating MSL Moisture sensitivity level Meets or exceeds JEDEC Spec JESD78B IC latch up test At 1/8 in V–0 3 Operating Conditions Parameter VDD TA tPU Description Supply voltage Ambient operating temperature Power ramp time Condition Min Max Unit 2.5-V supply 2.375 2.625 V 3.3-V supply 3.135 3.465 V 0 70 °C Industrial Commercial –40 85 °C Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic). 0.05 500 ms Note 2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required. Document Number: 001-55566 Rev. *G Page 4 of 13 [+] Feedback CY2DP1510 DC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition Min Max Unit All LVPECL outputs floating (internal IDD) – 120 mA IDD Operating supply current VIH1 Input high voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# – VDD + 0.3 V VIL1 Input low voltage, LVPECL input clocks IN0 and IN0#, IN1 and IN1# –0.3 – V VIH2 Input high voltage, IN_SEL VDD = 3.3 V 2.0 VDD + 0.3 V VIL2 Input low voltage, IN_SEL VDD = 3.3 V –0.3 0.8 V VIH3 Input high voltage, IN_SEL VDD = 2.5 V 1.7 VDD + 0.3 V VIL3 Input low voltage, IN_SEL VDD = 2.5 V –0.3 0.7 V VID[3] Input differential amplitude See Figure 2 on page 7 0.4 1.0 V VICM Input common mode voltage See Figure 2 on page 7 0.5 VDD – 0.2 V – 150 μA –150 – μA [4] IIH Input high current, All inputs Input = VDD IIL Input low current, All inputs Input = VSS[4] LVPECL output high voltage VOL Terminated with 50 Ω to VDD – 2.0[5] VDD – 1.20 VDD – 0.70 V LVPECL output low voltage Terminated with 50 Ω to VDD – 2.0[5] VDD – 2.0 VDD – 1.63 V VBB Output reference voltage 0 to 150 μA output current RP Internal pull-down resistance IN_SEL pin 60 140 kΩ CIN Input capacitance Measured at 10 MHz; per pin – 3 pF VOH VDD – 1.40 VDD – 1.16 V Notes 3. VID minimum of 400 mV is required to meet all output AC electrical specifications. The device is functional with VID minimum of greater than 200 mV. 4. Positive current flows into the input pin, negative current flows out of the input pin. 5. Refer to Figure 3 on page 7. Document Number: 001-55566 Rev. *G Page 5 of 13 [+] Feedback CY2DP1510 AC Electrical Specifications (VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial)) Parameter Description Condition FIN Input frequency FOUT Output frequency VPP LVPECL differential output voltage peak Fout = DC to 150 MHz to peak, single ended. Terminated with 50 Ω to VDD – 2.0[6] Fout = >150 MHz to 1.5 GHz tPD [7] FOUT = FIN Min Typ Max Unit DC – 1.5 GHz DC – 1.5 GHz 600 – – mV 400 – – mV Propagation delay input pair to output pair Input rise/fall time < 1.5 ns (20% to 80%) – – 600 ps tODC[8] Output duty cycle 50% duty cycle at input Frequency range up to 1 GHz 48 – 52 % tSK1[9] Output-to-output skew Any output to any output, with same load conditions at DUT – – 40 ps tSK1 D[9] Device-to-device output skew Any output to any output between two or more devices. Devices must have the same input and have the same output load. – – 150 ps PNADD Additive RMS phase noise 156.25-MHz input Rise/fall time < 150 ps (20% to 80%) VID > 400 mV Offset = 1 kHz – – –120 dBc/Hz Offset = 10 kHz – – –130 dBc/Hz Offset = 100 kHz – – –140 dBc/Hz Offset = 1 MHz – – –150 dBc/Hz Offset = 10 MHz – – –154 dBc/Hz Offset = 20 MHz – – –155 dBc/Hz tJIT[10] Additive RMS phase jitter (Random) 156.25 MHz, 12 kHz to 20 MHz offset; input rise/fall time < 150 ps (20% to 80%), VID > 400 mV – – 0.11 ps tR,tF[11] Output rise/fall time 50% duty cycle at input, 20% to 80% of full swing (VOL to VOH) Input rise/fall time < 1.5 ns (20% to 80%) – – 300 ps Notes 6. Refer to Figure 3 on page 7. 7. Refer to Figure 4 on page 7. 8. Refer to Figure 5 on page 7. 9. Refer to Figure 6 on page 8. 10. Refer to Figure 7 on page 8. 11. Refer to Figure 8 on page 8. Document Number: 001-55566 Rev. *G Page 6 of 13 [+] Feedback CY2DP1510 Figure 2. Input Differential and Common Mode Voltages VA IN VICM = (VA + VB)/2 VID IN# VB Figure 3. Output Differential Voltage VOH Q VPP Q# VOL Figure 4. Input to Any Output Pair Propagation Delay IN IN # QX Q X# t PD Figure 5. Output Duty Cycle QX Q X# tPW tPERIOD tODC = Document Number: 001-55566 Rev. *G tPW tPERIOD Page 7 of 13 [+] Feedback CY2DP1510 Figure 6. Output-to-Output and Device-to-Device Skew QX Q X# Device 1 QY Q Y# tSK1 QZ Device 2 Q Z# tSK1 D Figure 7. RMS Phase Jitter Phase noise Noise Power Phase noise mark Offset Frequency f2 f1 RMS Jitter ∝ Area Under the Masked Phase Noise Plot Figure 8. Output Rise/Fall Time QX 80% 80% VPP 20% QX# 20% tR Document Number: 001-55566 Rev. *G tF Page 8 of 13 [+] Feedback CY2DP1510 Ordering Information Part Number Type Production Flow Pb-free CY2DP1510AXC 32-Pin TQFP Commercial, 0 °C to 70 °C CY2DP1510AXCT 32-Pin TQFP tape and reel Commercial, 0 °C to 70 °C CY2DP1510AXI 32-Pin TQFP Industrial, –40 °C to 85 °C CY2DP1510AXIT 32-Pin TQFP tape and reel Industrial, –40 °C to 85 °C Ordering Code Definition CY 2DP15 10 AX C/I T Tape and reel Temperature range C = Commercial I = Industrial Pb-free TQFP package Number of differential output pairs Base part number Company ID: CY = Cypress Document Number: 001-55566 Rev. *G Page 9 of 13 [+] Feedback CY2DP1510 Package Dimension Figure 9. 32-Pin Thin Plastic Quad Flat Pack 7 × 7 × 1.0 mm 001-54497 *A Document Number: 001-55566 Rev. *G Page 10 of 13 [+] Feedback CY2DP1510 Acronyms Document Conventions Table 2. Acronyms Used in this Document Table 3. Units of Measure Acronym Description Symbol Unit of Measure ESD electrostatic discharge °C degree Celsius HBM human body model dBc decibels relative to the carrier JEDEC Joint electron devices engineering council GHz giga hertz LVDS low-voltage differential signal Hz hertz LVCMOS low-voltage complementary metal oxide semiconductor KΩ kilo ohm µA microamperes LVPECL low-voltage positive emitter-coupled logic µF micro Farad LVTTL low-voltage transistor-transistor logic OE Output enable RMS root mean square TQFP thin quad flat pack Document Number: 001-55566 Rev. *G µs microsecond mA milliamperes ms millisecond mV millivolt MHz megahertz ns nanosecond Ω ohm pF pico Farad ps pico second V volts W watts Page 11 of 13 [+] Feedback CY2DP1510 Document History Page Document Title: CY2DP1510 1:10 LVPECL Fanout Buffer with Selectable Clock Input Document Number: 001-55566 Revision ECN Orig. of Change Submission Date Description of Change ** 2782891 CXQ 10/09/09 *A 2838916 CXQ 01/05/2010 Changed status from “ADVANCE” to “PRELIMINARY”. Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page 1 and in tJIT in the AC Electrical Specs table on page 5. Added tPU spec to the Operating Conditions table on page 3. Changed VOH in the DC Electrical Specs table on page 4: minimum from VDD - 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V. Removed VOD spec in the DC Electrical Specs table on page 4. Changed VBB max spec in the DC Electrical Specs table on page 4 from VDD - 1.38V to VDD - 1.40V. Added RP spec in the DC Electrical Specs table on page 4. Min = 60 kΩ, Max = 140 kΩ. Added a measurement definition for CIN in the DC Electrical Specs table on page 4. Added VPP spec to the AC Electrical Specs table on page 5. VPP min = 600 mV for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz. Changed letter case and some names of all the timing parameters in the AC Electrical Specs table on page 5 to be consistent with EROS. Lowered all additive phase noise mask specs by 3 dB in the AC Electrical Specs table on page 5. Added condition to tR and tF specs in the AC Electrical specs table on page 5 that input rise/fall time must be less than 1.5 ns (20% to 80%). Changed letter case and some names of all the timing parameters in Figures 3, 4, 5, 6 and 8, to be consistent with EROS. New Datasheet. *B 2885033 CXQ 02/26/2010 Updated 32-Pin TQFP package diagram. *C 3011766 CXQ 08/23/2010 Changed from 0.25 ps to 0.11 ps maximum additive jitter in “Features” on page 1 and in tJIT in the AC Electrical Specs table on page 6. Added description of EPAD to Table 1 pin definitions. Added note 3 to describe IIH and IIL specs. Changed VBB max from VDD - 1.26V to VDD - 1.16V in DC Electrical Specs. Removed reference to data distribution from “Functional Description”. Changed RP for differential inputs from 100 kΩ to 150 kΩ in the Logic Block Diagram and from 60 kΩ min / 140 kΩ max to 90 kΩ min / 210 kΩ max in the DC Electrical Specs table. Added max VID of 1.0V in DC Electrical Specs table. Changed tPD max spec from 480 ps to 600 ps. Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to -120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs table. Added “Frequency range up to 1 GHz” condition to tODC spec. Updated package drawing to 001-54497 to reflect use of EPAD package. Added Acronyms and Ordering Code Definition. *D 3017258 CXQ 08/27/2010 Corrected Output Rise/Fall time diagram. *E 3100234 CXQ 11/18/2010 Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4” Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec JESD78B IC Latchup Test” Removed RP spec for differential input clock pins INX and INX#. Changed CIN condition to “Measured at 10 MHz”. Changed PNADD specs for 100kHz, 10MHz, and 20MHz offsets. *F 3135201 CXQ 01/12/2011 Removed “Preliminary” status heading. Removed pull-up/pull-down resistors from INx/INx# pins in Logic Block Diagram. *G 3090938 CXQ 02/25/2011 Post to external web. Document Number: 001-55566 Rev. *G Page 12 of 13 [+] Feedback CY2DP1510 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive psoc.cypress.com/solutions cypress.com/go/clocks PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-55566 Rev. *G Revised February 25, 2011 Page 13 of 13 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback