CY2DP1504
1:4 LVPECL Fanout Buffer
with Selectable Clock Input
1:4 LVPECL Fanout Buffer with Selectable Clock Input
Features
Functional Description
■
Select one of two differential (LVPECL, LVDS, HCSL, or CML)
input pairs to distribute to four LVPECL output pairs
■
Translates any single-ended input signal to 3.3 V LVPECL
levels with resistor bias on INx# input
■
30 ps maximum output-to-output skew
■
480 ps maximum propagation delay
■
0.15 ps maximum additive RMS phase jitter at 156.25 MHz
(12 kHz to 20 MHz offset)
■
Up to 1.5 GHz operation
■
Synchronous clock enable function
■
20-pin TSSOP
■
2.5 V or 3.3 V operating voltage [1]
■
Commercial and industrial operating temperature range
The CY2DP1504 is an ultra-low noise, low-skew,
low-propagation delay, 1:4 LVPECL fanout buffer targeted to
meet the requirements of high-speed clock distribution
applications. The CY2DP1504 can select between separate
differential (LVPECL, LVDS, HCSL, or CML) input clock pairs
using the IN_SEL pin. The synchronous clock enable function
ensures glitch-free output transitions during enable and disable
periods. The device has a fully differential internal architecture
that is optimized to achieve low additive jitter and low skew at
operating frequencies of up to 1.5 GHz.
For a complete list of related documentation, click here.
Logic Block Diagram
Q0
Q0#
VDD
VSS
Q1
Q1#
IN0
IN0#
Q2
Q2#
IN1
IN1#
Q3
Q3#
IN_SEL
RP
VDD
Q
RP
CLK_EN
D
Note
1. Input AC-coupling capacitors are required for voltage-translation applications.
Cypress Semiconductor Corporation
Document Number: 001-56215 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 13, 2016
CY2DP1504
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Absolute Maximum Ratings ............................................ 4
Operating Conditions ....................................................... 4
DC Electrical Specifications ............................................ 5
Thermal Resistance .......................................................... 5
AC Electrical Specifications ............................................ 6
Switching Waveforms ...................................................... 8
Application Information ................................................. 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagram ............................................................ 12
Document Number: 001-56215 Rev. *N
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 16
Worldwide Sales and Design Support ....................... 16
Products .................................................................... 16
PSoC®Solutions ....................................................... 16
Cypress Developer Community ................................. 16
Technical Support ..................................................... 16
Page 2 of 16
CY2DP1504
Pinouts
Figure 1. 20-pin TSSOP pinout
1
20
Q0
CLK_EN
2
19
Q0#
IN_SEL
3
18
VDD
IN0
4
17
Q1
IN0#
5
16
Q1#
IN1
IN1#
6
15
Q2
14
13
Q2#
CY2DP1504
VSS
NC
7
8
NC
9
12
Q3
VDD
10
11
Q3#
VDD
Pin Definitions
Pin No.
Pin Name
Pin Type
1
VSS
Power
Description
2
CLK_EN
Input
Synchronous clock enable. LVCMOS/LVTTL.
When CLK_EN = Low, Q(0:3) outputs are held Low and Q(0:3)# outputs are held High
3
IN_SEL
Input
Input clock select pin. LVCMOS/LVTTL;
When IN_SEL = Low, the IN0/IN0# differential input pair is active
When IN_SEL = High, the IN1/IN1# differential input pair is active
4
IN0
Input
Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL = Low
5
IN0#
Input
Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active when
IN_SEL = Low
Ground
6
IN1
Input
Differential (LVPECL, HCSL, LVDS, or CML) input clock. Active when IN_SEL = High
7
IN1#
Input
Differential (LVPECL, HCSL, LVDS, or CML) complementary input clock. Active when
IN_SEL = High
8, 9
NC
No connection
10, 13, 18
VDD
Power
Power supply
11, 14, 16, 19
Q(0:3)#
Output
LVPECL complementary output clocks
12, 15, 17, 20
Q(0:3)
Output
LVPECL output clocks
Document Number: 001-56215 Rev. *N
Page 3 of 16
CY2DP1504
Absolute Maximum Ratings
Parameter
Description
Condition
Min
Max
Unit
VDD
Supply voltage
Non functional
–0.5
4.6
V
VIN[2]
Input voltage, relative to VSS
Non functional
–0.5
Lesser of 4.0 or
VDD + 0.4
V
VOUT[2]
DC output or I/O voltage, relative Non functional
to VSS
–0.5
Lesser of 4.0 or
VDD + 0.4
V
TS
Storage temperature
Non functional
–55
150
°C
ESDHBM
Electrostatic discharge (ESD)
protection (Human body model)
JEDEC STD 22-A114-B
2000
–
V
LU
Latch up
UL–94
Flammability rating
MSL
Moisture sensitivity level
Meets or exceeds JEDEC Spec JESD78B
IC Latch up Test
At 1/8 in
V-0
3
Operating Conditions
Parameter
VDD
TA
tPU
Description
Supply voltage
Ambient operating temperature
Power ramp time
Condition
Min
Max
Unit
2.5-V supply
2.375
2.625
V
3.3-V supply
3.135
3.465
V
0
70
°C
Industrial
Commercial
–40
85
°C
Power-up time for VDD to reach
minimum specified voltage (power
ramp must be monotonic).
0.05
500
ms
Note
2. The voltage on any I/O pin cannot exceed the power pin during power up. Power supply sequencing is not required.
Document Number: 001-56215 Rev. *N
Page 4 of 16
CY2DP1504
DC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
Description
Min
Max
Unit
–
61
mA
Input high voltage, differential
input clocks IN0 and IN0#, IN1
and IN1#
–
VDD + 0.3
V
VIL1
Input low voltage, differential
input clocks IN0 and IN0#, IN1
and IN1#
–0.3
–
V
VIH2
Input high voltage, CLK_EN,
IN_SEL
VDD = 3.3 V
2.0
VDD + 0.3
V
VIL2
Input low voltage, CLK_EN,
IN_SEL
VDD = 3.3 V
–0.3
0.8
V
VIH3
Input high voltage, CLK_EN,
IN_SEL
VDD = 2.5 V
1.7
VDD + 0.3
V
VIL3
Input low voltage, CLK_EN,
IN_SEL
VDD = 2.5 V
–0.3
0.7
V
VID_LDVS[3]
LVDS input differential amplitude See Figure 2 on page 8
0.4
0.8
V
VID_LVPECL[3]
LVPECL/CML/HSCL input
differential amplitude
See Figure 2 on page 8
0.4
1.0
V
VICM
Input common mode voltage
See Figure 2 on page 8
0.2
VDD – 0.2
V
IIH
Input high current, all inputs
Input = VDD [4]
–
150
A
IIL
Input low current, all inputs
Input = VSS [4]
–150
–
A
IDD
Operating supply current
VIH1
VOH
LVPECL output high voltage
Condition
All LVPECL outputs floating (internal IDD)
Terminated with 50 to VDD – 2.0
[5]
VDD – 1.20 VDD – 0.70
Terminated with 50 to VDD – 2.0
[5]
VDD – 2.0 VDD – 1.63
V
VOL
LVPECL output low voltage
RP
Internal pull-up/pull-down
CLK_EN has pull-up only
resistance, LVCMOS logic inputs IN_SEL has pull-down only
60
165
k
CIN
Input capacitance
–
3
pF
Measured at 10 MHz; per pin
V
Thermal Resistance
Parameter [6]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
20-pin TSSOP Unit
80
°C/W
16
°C/W
Notes
3. VID minimum of 400 mV is required to meet all output AC Electrical Specifications. The device is functional with VID minimum of greater than 200 mV.
4. Positive current flows into the input pin, negative current flows out of the input pin.
5. Refer to Figure 3 on page 8.
6. These parameters are guaranteed by design and are not tested.
Document Number: 001-56215 Rev. *N
Page 5 of 16
CY2DP1504
AC Electrical Specifications
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
FIN
FOUT
VPP
Description
Input frequency
Output frequency
LVPECL differential output
voltage peak to peak,
single-ended. Terminated with
50 to VDD – 2.0 [8]
Min
Typ
Max
Unit
Differential Input
Condition
DC
–
1.5
GHz
Single-ended CMOS Input [7]
DC
250
MHz
FOUT = FIN, Differential Input
DC
–
1.5
GHz
FOUT = FIN,
Single-ended CMOS Input [7]
DC
–
250
MHz
Fout = DC to 150 MHz
600
–
–
mV
Fout = >150 MHz to 1.5 GHz
400
–
–
mV
tPD[9]
Propagation delay differential
Input rise/fall time < 1.5 ns
input pair to differential output pair (20% to 80%)
–
–
480
ps
tODC[10]
Output duty cycle
50% duty cycle at input,
Frequency range up to 1 GHz,
Differential input
48
–
52
%
50% duty cycle at input,
Frequency range up to 250 MHz,
Single-ended CMOS input [7]
45
–
55
%
tSK1[11]
Output-to-output skew
Any output to any output, with same
load conditions at DUT
–
–
30
ps
tSK1 D[11]
Device-to-device output skew
Any output to any output between
two or more devices. Devices must
have the same input and have the
same output load.
–
–
150
ps
PNADD
Additive RMS phase noise,
156.25-MHz input,
Rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV or
Input Swing = 3.0 V [7]
Offset = 1 kHz
–
–
–120
dBc/
Hz
Offset = 10 kHz
–
–
–130
dBc/
Hz
Offset = 100 kHz
–
–
–135
dBc/
Hz
Offset = 1 MHz
–
–
–145
dBc/
Hz
Offset = 10 MHz
–
–
–153
dBc/
Hz
Offset = 20 MHz
–
–
–155
dBc/
Hz
Notes
7. Refer to Application Information on page 10.
8. Refer to Figure 3 on page 8.
9. Refer to Figure 4 on page 8.
10. Refer to Figure 5 on page 8.
11. Refer to Figure 6 on page 9.
Document Number: 001-56215 Rev. *N
Page 6 of 16
CY2DP1504
AC Electrical Specifications (continued)
(VDD = 3.3 V ± 5% or 2.5 V ± 5%; TA = 0 °C to 70 °C (Commercial) or –40 °C to 85 °C (Industrial))
Parameter
tJIT[12]
Description
Additive RMS phase jitter
(random)
Min
Typ
Max
Unit
156.25 MHz,
12 kHz to 20 MHz offset;
input rise/fall time < 150 ps
(20% to 80%),
VID > 400 mV
Condition
–
–
0.15
ps
156.25 MHz Sinewave,
12 kHz to 20 MHz offset,
input rise/fall time < 150 ps
(20% to 80%),
Input Swing = 3.0 V [13]
–
–
0.15
ps
tR, tF[14]
Output rise/fall time
50% duty cycle at input,
20% to 80% of full swing
(VOL to VOH)
Input rise/fall time < 1.5 ns
(20% to 80%)
–
–
300
ps
tSOD
Time from clock edge to outputs Synchronous clock enable
disabled
(CLK_EN) switched Low
–
–
700
ps
tSOE
Time from clock edge to outputs Synchronous clock enable
enabled
(CLK_EN) switched High
–
–
700
ps
Notes
12. Refer to Figure 7 on page 9.
13. Refer to Application Information on page 10.
14. Refer to Figure 8 on page 9.
Document Number: 001-56215 Rev. *N
Page 7 of 16
CY2DP1504
Switching Waveforms
Figure 2. Input Differential and Common Mode Voltages
VA
IN
VICM = (VA + VB)/2
VID
IN#
VB
Figure 3. Output Differential Voltage
VOH
Q
VPP
Q#
VOL
Figure 4. Input to Any Output Pair Propagation Delay
IN
IN#
QX
QX#
tPD
Figure 5. Output Duty Cycle
QX
QX#
tPW
tPERIOD
tODC =
Document Number: 001-56215 Rev. *N
tPW
tPERIOD
Page 8 of 16
CY2DP1504
Switching Waveforms (continued)
Figure 6. Output-to-Output and Device-to-Device Skew
QX
QX#
Device 1
QY
QY#
tSK1
QZ
Device 2
QZ#
tSK1 D
Figure 7. RMS Phase Jitter
Phase noise
Noise Power
Phase noise mark
Offset Frequency
f2
f1
RMS Jitter
Area Under the Masked Phase Noise Plot
Figure 8. Output Rise/Fall Time
QX
80% 80%
VPP
20%
QX#
20%
tR
tF
Figure 9. Synchronous Clock Enable Timing
CLK_EN
IN
IN#
tSOD
tPD
tSOE
QX
QX#
Document Number: 001-56215 Rev. *N
Page 9 of 16
CY2DP1504
Application Information
CY2DP1504 can be used with a single-ended CMOS input by biasing the Complementary Input Clock (INx#). “True” input pins (INx)
of differential input pair can be fed with a single-ended CMOS input signal. The “complementary” input pin (INx#) of the same
differential input pair can be biased with Vref.
Figure 10 shows the schematic which can be used to give single-ended CMOS input to the CY2DP1504.
The reference voltage Vref = VDD/2 is generated by the bias resistors R1, R2 and capacitor C0. This bias circuit should be located
as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the Vref in the center of the input
voltage swing. For example, if the input clock swing is 2.5 V and VDD = 3.3 V, Vref should be 1.25 V and R2/R1 = 0.609.
Figure 10. Application Example
VDD
R1
1K
Single Ended Clock Input
INx
Vref
INx#
C0
0.1 u
Document Number: 001-56215 Rev. *N
R2
1K
Page 10 of 16
CY2DP1504
Ordering Information
Part Number
Type
Production Flow
Pb-free
CY2DP1504ZXC
20-pin TSSOP
Commercial, 0 °C to 70 °C
CY2DP1504ZXCT
20-pin TSSOP – Tape and Reel
Commercial, 0 °C to 70 °C
CY2DP1504ZXI
20-pin TSSOP
Industrial, –40 °C to 85 °C
CY2DP1504ZXIT
20-pin TSSOP – Tape and Reel
Industrial, –40 °C to 85 °C
Ordering Code Definitions
CY 2DP15
04
Z
X X
X
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type:
Z = 20-pin TSSOP
Number of differential output pairs
Base part number
Company ID: CY = Cypress
Document Number: 001-56215 Rev. *N
Page 11 of 16
CY2DP1504
Package Diagram
Figure 11. 20-pin TSSOP 4.40 mm Body Z20.173/ZZ20.173 Package Outline, 51-85118
51-85118 *E
Document Number: 001-56215 Rev. *N
Page 12 of 16
CY2DP1504
Acronyms
Acronym
Document Conventions
Description
Units of Measure
ESD
electrostatic discharge
HBM
human body model
°C
degree Celsius
HCSL
high-speed current steering logic
dBc
decibels relative to the carrier
JEDEC
joint electron devices engineering council
GHz
gigahertz
LVCMOS
low-voltage complementary metal oxide
semiconductor
Hz
hertz
LVPECL
low-voltage positive emitter-coupled logic
LVTTL
low-voltage transistor-transistor logic
RMS
root mean square
TSSOP
thin shrunk small outline package
Document Number: 001-56215 Rev. *N
Symbol
Unit of Measure
k
kilohm
µA
microampere
µF
microfarad
µs
microsecond
mA
milliampere
ms
millisecond
mV
millivolt
MHz
megahertz
ns
nanosecond
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Page 13 of 16
CY2DP1504
Document History Page
Document Title: CY2DP1504, 1:4 LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-56215
Revision
ECN
Orig. of
Change
Submission
Date
**
2782891
CXQ
10/09/09
*A
2838916
CXQ
01/05/2010
Changed status from “ADVANCE” to “PRELIMINARY”.
Changed from 0.34 ps to 0.25 ps maximum additive jitter in “Features” on page
1 and in tJIT in the AC Electrical Specs table on page 5.
Added tPU spec to the Operating Conditions table on page 3.
Changed max IDD spec in the DC Electrical Specs table on page 4 from 60 mA
to 61 mA.
Change VOH in the DC Electrical Specs table on page 4: minimum from VDD 1.15V to VDD - 1.20V; maximum from VDD - 0.75V to VDD - 0.70V.
Removed VOD spec from the DC Electrical Specs table on page 4.
Added RP spec in the DC Electrical Specs table on page 4. Min = 60 k, Max
= 140 k.
Added a measurement definition for CIN in the DC Electrical Specs table on
page 4.
Added VPP spec to the AC Electrical Specs table on page 5. VPP min = 600 mV
for DC - 150 MHz and min = 400 mV for 150 MHz to 1.5 GHz.
Changed letter case and some names of all the timing parameters in the AC
Electrical Specs table on page 5 to be consistent with EROS.
Lowered all additive phase noise mask specs by 3 dB in the AC Electrical
Specs table on page 5.
Added condition to tR and tF specs in the AC Electrical specs table on page 5
that input rise/fall time must be less than 1.5 ns (20% to 80%).
Changed letter case and some names of all the timing parameters in Figures
3, 4, 5, 6 and 8, to be consistent with EROS.
*B
3011766
CXQ
08/20/2010
Changed maximum additive jitter from 0.25 ps to 0.11 ps in “Features” on page
1 and in tJIT in the AC Electrical Specs table.
Added note 3 to describe IIH and IIL specs.
Removed reference to data distribution from “Functional Description”.
Changed RP for differential inputs from 100 k to 150 k in the Logic Block
Diagram and from 60 k min / 140 k max to 90 k min / 210 k max in the
DC Electrical Specs table.
Added max VID of 1.0V in DC Electrical Specs table.
Updated phase noise specs for 1 k/10 k/100 k/1 M/10 M/20 MHz offset to
-120/-130/-135/-150/-150/-150dBc/Hz, respectively, in the AC Electrical Specs
table.
Added “Frequency range up to 1 GHz” condition to tODC spec.
Added Ordering Code Definition.
Updated package diagram.
Added Acronyms.
*C
3017258
CXQ
08/27/2010
Corrected Output Rise/Fall time diagram.
*D
3100234
CXQ
11/18/2010
Updated Phase jitter to 0.15ps max from 0.11ps max.
Changed VIN and VOUT specs from 4.0V to “lesser of 4.0 or VDD + 0.4”
Removed 200mA min LU spec, replaced with “Meets or exceeds JEDEC Spec
JESD78B IC Latchup Test”
Removed RP spec for differential input clock pins INX and INX#.
Changed CIN condition to “Measured at 10 MHz”.
Changed PNADD specs for 1MHz, 10MHz, and 20MHz offsets.
Removed tS and tH specs from AC specs table.
*E
3135201
CXQ
01/12/2011
Removed “Preliminary” status heading.
Removed resistors from INx/INx# in Logic Block Diagram.
Added Figure 9 to describe TSOE and TSOD.
*F
3090938
CXQ
02/25/2011
Post to external web.
Document Number: 001-56215 Rev. *N
Description of Change
New data sheet.
Page 14 of 16
CY2DP1504
Document History Page (continued)
Document Title: CY2DP1504, 1:4 LVPECL Fanout Buffer with Selectable Clock Input
Document Number: 001-56215
Revision
ECN
Orig. of
Change
Submission
Date
*G
3208968
CXQ
03/29/2011
Changed RP max from 140 k to 165 k and updated RP in Logic Block
Diagram.
*H
3308039
CXQ
07/11/2011
Updated supported differential input clock types to include
LVPECL/LVDS/CML in Features, Functional Description, Pin Definitions, and
DC specs table sections.
Broke out VID spec into VID_LVDS and VID_LVPECL specs.
*I
3395868
PURU
10/05/11
Updated supported differential input clock types to include HCSL in Features,
Pinouts, and DC Electrical Specifications table.
Changed Min value of VICM.
*J
3740406
CINM
09/11/2012
Minor text edits.
*K
3799048
PURU
12/05/2012
Updated Features:
Added “Translates any single-ended input signal to 3.3 V LVPECL levels with
resistor bias on INx# input”.
Updated AC Electrical Specifications:
Added Note 7 and Note 13.
Added FIN parameter values for “Single Ended CMOS Input” condition
(Minimum value = DC, Maximum value = 250 MHz).
Added FOUT parameter values for “Single Ended CMOS Input” condition
(Minimum value = DC, Maximum value = 250 MHz).
Updated tPD parameter (Changed description from “Propagation delay input
pair to output pair” to “Propagation delay differential input pair to differential
output pair”).
Added tODC parameter values for “Single Ended CMOS Input” condition
(Minimum value = 45%, Maximum value = 55%).
Updated description of PNADD parameter (Replaced “Additive RMS phase
noise, 156.25-MHz input, Rise/fall time < 150 ps (20% to 80%), VID > 400 mV”
with “Additive RMS phase noise, 156.25-MHz input, Rise/fall time < 150 ps
(20% to 80%), VID > 400 mV or Input Swing = 3.0 V[7]”).
Added tJIT parameter values for the Condition “156.25 MHz Sinewave,
12 kHz to 20 MHz offset, input rise/fall time < 150 ps (20% to 80%),
Input Swing = 3.0 V [13]” (Maximum value = 0.15 ps).
Added Application Information.
Updated to new template.
*L
4586288
PURU
12/04/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
Updated Package Diagram:
spec 51-85118 – Changed revision from *D to *E.
*M
4959240
TAVA
10/12/2015
Updated to new template.
Completing Sunset Review.
*N
5267558
PSR
05/13/2016
Added Thermal Resistance.
Updated to new template.
Document Number: 001-56215 Rev. *N
Description of Change
Page 15 of 16
CY2DP1504
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
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Document Number: 001-56215 Rev. *N
Revised May 13, 2016
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